Distributed Arithmetic Research Articles

Low power area efficient adaptive FIR filter for hearing aids using distributed arithmetic architecture

In this paper, we propose a low complex architectural design for hearing aid applications. In this, we recast the hearing aid using distributed arithmetic (DA), which enables the implementation of hearing aid without multipliers. The design is based on the distributed arithmetic based formulation of it. It is further shown that high order filters, which are required to implement high-speed hearing aid can be realized using only look-up-tables and shift-accumulate operations. A novel approach was proposed to replace the decimation filter of a hearing aid using multiplier less architecture with a single DA unit. By proper initialization, it is shown that low complexity hearing aid architecture can be obtained. The proposed distributed arithmetic architecture is implemented in ASIC SAED 90 nm technology. The application of hearing aid is implemented in Matlab Simulink and Xilinx system generator tool. The obtained results show $$20\%$$ less area delay product and $$40\%$$ less power delay product when compared with the existing architecture.

ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems

Digital signal processing (DSP) systems are becoming popular with the emergence of artificial intelligence and machine learning based applications. Residue number system is one of most sought representation for implementing the high speed DSP systems. This paper presents an efficient implementation of memory less distributed arithmetic (MLDA) architecture in finite impulse response filter with residual number system. The input data and filter coefficients of MLDA are in residue number form and the output data from MLDA is converted into binary form using Chinese remainder theorem. In addition, compressor adders are used to reduce the area. For real time validation, the proposed design has been simulated and synthesized in application specific integrated circuit platform using synopsis design compiler with CMOS 90 nm technology. The results show that the proposed design has very high computation speed with total delay of only 20 ns and occupies 20% less area in comparison with the existing designs.

Design of 4:2 Compressor for Parallel Distributed Arithmetic FIR Filter

Distributed arithmetic (DA) calculation is generally utilized for FIR channel execution. In the starting, DA was proposed as successive DA (SDA), and at that point was stretched out to parallel DA (PDA) for higher throughput. This paper introduces a novel PDA FIR channel design in view of 4:2 compressors which can be mapped on Xilinx FPGAs effectively. Overall, our proposed FIR models accomplish 17.5% decrease in asset use and 20.7% change in execution contrasted with the cutting edge PDA FIR channel. Additionally, overall, there is 57.9% decrease in asset utilization and 23.0% change in execution contrasted with PDA FIR. Another 4:2 compressor design in light of changing some inward conditions are proposed. Furthermore, utilizing an efficient full-snake (FA) square is considered to have a fast blower. Three 4:2 compressors are considered for examination. The proposed engineering is contrasted and the best existing plans exhibited in the best in class writing regarding force, deferral and territory. The paper presents compressors that are broadly utilized as building squares of multipliers.

VLSI implementation of distributed arithmetic based block adaptive finite impulse response filter

In this paper, an efficient VLSI architecture of distributed arithmetic (DA) based block least mean square (BLMS) adaptive finite impulse response (ADFIR) filter implementation with parallel processing is proposed. In DA scheme, the filter partial products are precomputed and saved in lookup table (LUT) and then by using shift and accumulation operations filtering can be done. To improve the efficiency, a high level of parallelism is incorporated in the design of variable coefficient ADFIR filter. The parallel LUT followed by shift-accumulate operations replaces multiply and accumulate (MAC) operations. By using BLMS algorithm in ADFIR filter with block length P gives P times fast throughput. Since memory reuse concept is used, the design requires less number of registers to calculate output vector and coefficient increment vector. The proposed design is implemented on FPGA. The implementation results indicate that the proposed design is a low power and high speed architecture. The proposed structure provides 47.4% less power and 22.7% less delay when compared to existing designs.

Memory Efficient High Speed Systolic Array Architecture Design with Multiplexed Distributed Arithmetic for 2D DTCWT Computation on FPGA

This paper presents customized Systolic Array Architecture (SAA) design of Dual Tree Complex Wavelet (DTCWT) sub band computation based on multiplexed Distributive Arithmetic Algorithm (DAA). The proposed architecture is memory efficient and operates at frequencies greater than 300 MHz in decomposing 256 x 256 input images. Three architectures such as reduced order structure, multiplexed DA structure and zero pad structure are designed and evaluated for its performances for DTCWT computation minimizing arithmetic operations with improved latency. The proposed design is modeled in Verilog HDL and is implemented on Spartan-6 and Virtex-5 FPGA considering Xilinx ISE FPGA design flow. The latency of proposed architectures is evaluated to be 15 clock cycles and throughput is estimated to be 4 outputs for every 5 clock cycles. The SAA architecture occupies less than 12% of FPGA resources and consumes less than 10 mW of power on FPGA platform.

High speed low area OBC DA based decimation filter for hearing aids application

This brief presents a decimation filter for hearing aid application using distributed arithmetic (DA) approach. In this paper, we propose a reconfigurable offset-binary code (OBC) DA based finite impulse response (FIR) filter with a shared look-up table (LUT) updating scheme. The size of the LUTs in DA increases exponentially with the order of filters. Shared LUT based DA structure is a solution to reduce this large memory requirement for higher order filters. The proposed shared LUT updating scheme uses LUT partitioning in which coefficients are spilt into small length vectors and it ensures a drastic reduction in the size of LUTs. The proposed DA filter is synthesized on CMOS 90 nm technology using Synapsis ASIC Design Compiler. The proposed design achieves high speed at a reduced area-delay product (ADP) when compared with recent designs. The proposed architecture is implemented and tested on Virtex 5vsx95-1ff1136 FPGA and the results show that the proposed design involves less number of slices and offers high speed than existing designs. A three-stage decimation filter of hearing aids is designed with the proposed FIR filter and is implemented on the target device by Matlab simulink and Xilinx system generator.

An Analytical Framework and Approximation Strategy for Efficient Implementation of Distributed Arithmetic-Based Inner-Product Architectures

Distributed arithmetic (DA)-based approximate structures are used for efficient implementation of inner-products in various error-resilient applications. In the existing literature, most of these approximate architectures are developed by truncating the least significant bits (LSBs) of the inputs and/or the multiplying coefficients. The existing works do not provide any analytical study to evaluate and design an approximate structure. To address this issue, an analytical framework is proposed in this paper. It is shown that the analytical results match very closely with the Monte Carlo simulation results. The proposed framework reveals that the truncation of the LSBs of partial inner-products is a promising alternative to design more efficient DA architectures with less error. Following these observations, a novel approach to truncate the LSBs of partial inner-products, namely, a weight-dependent truncation strategy and its two variants with a suitable error compensation function are presented in this paper. Synthesis results, accuracy analysis, and evaluation in two commonly used error-tolerant applications demonstrate the superiority of the proposed architectures over the state-of-the-art DA-based approximate structures.

Cost-effective multi-standard video transform core using time-sharing architecture

This paper presents a cost-effective two-dimensional (2-D) inverse discrete cosine transform (IDCT) for supporting multiple standards of MPEG 1/2/4, H.264, VC-1, and HEVC. The proposed approach employs a time allocation scheme to enable the simultaneous processing of the first and second dimensions in order to enhance data throughput and attain hardware utilization of 100%. The proposed one-dimensional (1-D) IDCT uses distributed arithmetic (DA) in conjunction with factor sharing (FS) within a hardware sharing architecture. Four parallel computation streams are employed to enhance the throughput rate as four times of operation frequency. The efficacy of this approach was verified by fabricating a test chip using the Taiwan Semiconductor Manufacturing Company Limited (TSMC) 90 nm Complementary Metal-Oxide-Semiconductor (CMOS) process. The inverse transform core has an operating frequency of 200 MHz and a throughput of 800 M-pels/s with a gate count of 27.2 K.

Low-Complexity Distributed-Arithmetic-Based Pipelined Architecture for an LSTM Network

Long short-term memory (LSTM) networks have addressed the shortcomings of recurrent neural networks, such as vanishing gradients and the lack of ability in developing connections across discontinuous parts of sequences. However, the implementations of state-of-the-art LSTM networks face the computational bottleneck of having multiple high-order matrix-vector multiplications (MVMs). This article presents a generalized approach to accelerate a circulant MVM (C-MVM), and hence, it is applicable to many neural networks. The proposed scheme presents a novel low-complexity distributed arithmetic (DA) architecture for optimizing C-MVMs. Unlike conventional offset binary coding-based DA (OBC-DA), it is based on separate generation and selection of partial products. Only one partial product generator (PPG) with several partial product selectors (PPSs) is required. The complexity of PPSs is reduced by sharing the minterms across Boolean expressions. Fine-grained pipelining is employed to achieve approximately one adder delay. From the implementation results, the proposed design with 512 × 512 LSTM layer occupies 74.54% less core area, consumes 68.66% less core power, offers 2.61 times more throughput, and 3.89 times more hardware efficiency over the best existing design.

Efficient Real-Time Digital Subcarrier Cross-Connect (DSXC) Based on Distributed Arithmetic DSP Algorithm

Two real-time functions of digital subcarrier cross-connect (DSXC) are experimentally demonstrated for the first time using distributed arithmetic (DA) in a field programmable gate array (FPGA) platform. Both frequency translation and channel selection in DSXC are implemented using DA-based resampling filters, achieving flexible modulation format and fine data-rate granularity of many concurrent subcarrier channels. Compared with traditional resampling filters that leverage multipliers, the DA-based approach eliminates the need for DSP slices in the FPGA implementation and significantly reduces the hardware cost. By requiring only a few clock periods, the DA-based resampling filter is also significantly faster when compared to conventional FIR filters, whose overall latency is proportional to the filter order. The DA-based DSXC is therefore able to achieve improved spectral efficiency and programmability of multiple orthogonal subcarrier channels, while keeping low cross-connection latency and requiring low cost hardware resources when implemented in a FPGA platform.

Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

Distributed Arithmetic (DA) based architecture is an efficient technique to attain high throughput without hardware multiplier and also it is essential for bit serial operation. The DA based Finite Impulse Response (FIR) adaptive filter is well suited for hardware implementation in Field Programmable Gate Array (FPGA) device. In conventional DA the partial products of the filter coefficients have been pre-calculated and stored in Look up Table (LUT) which in turn will increase the logic elements and power. To overcome this problem DA based Least Mean Square (LMS) adaptive filter using offset binary coding (OBC) without LUT is proposed. The proposed method will reduce the logic elements by half when compared to the conventional DA based OBC filter. The Carry Save Accumulator (CSA) is used to carry out the operation of shift and accumulation. The proposed architecture is implemented in Quartus II 9.1 with the device as Stratix-EP2S15F484C3 which offers 13.72% high throughput, 56.92% reduction in logic elements, 42.84% reduction in power, 57.74% reduction in logical registers for N = 16 and for N = 32 the number of logical element is reduced to 80.87%, 66.66% reduction in power and 24.12% high throughput.

An Efficient FIR Filter Architecture Implementation using Distributed Arithmetic (DA) for DSP Applications

In this paper the proposed efficient FIR filter architecture using a distributed arithmetic (DA) algorithm in which two issues are discussed in the conventional FIR filter. The FIR filter is well known to include delay elements, multipliers and adders. Due to the need for multipliers, this results in 2 demerits which are (i) increased in area and (ii) delayed increases that eventually lead to low efficiency (low speed). A notable feature of the proposed technique is to substitute a trivial amount of indexed LUT pages instead of conventional LUT based DA that it helps to maintain the access time lower. Also, significant idea connected with the proposed technique is required page can be thoroughly selected with the selection module without needing adders that result in reduced computation time. Furthermore, the proposed fast FIR filter is used for the powerful ECG noise elimination technique, which is prevalently used in biomedical and healthcare applications. The designs are simulated and synthesized by using Xilinx ISE. It can be seen from reports that our proposed DA consumes 30% less power for 11-tap FIR filters with a 40% shorter area, while the saving in power consumption for 8-tap FIR filters is 30% to 80% and 35% to 80% in the area. Especially in contrast with all the above-mentioned DA techniques, our enhanced quick FIR filters require less area and less power intake due to their lower memory requirements. All architectures are designed for FIR filters with 4 and 8 taps.

A memory and area-efficient distributed arithmetic based modular VLSI architecture of 1D/2D reconfigurable 9/7 and 5/3 DWT filters for real-time image decomposition

In this article, we have proposed the internal architecture of a dedicated hardware for 1D/2D convolution-based 9/7 and 5/3 DWT filters, exploiting bit-parallel ‘distributed arithmetic’ (DA) to reduce the computation time of our proposed DWT design while retaining the area at a comparable level to other recent existing designs. Despite using memory extensive bit-parallel DA, we have successfully achieved 90% reduction in the memory size than that of the other notable architectures. Through our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, mode. With the introduction of DA, we have incorporated pipelining and parallelism into our proposed convolution-based 1D/2D DWT architectures. We have reduced the area by 38.3% and memory requirement by 90% than that of the latest remarkable designs. The critical-path delay of our design is almost 50% than that of the other latest designs. We have successfully applied our prototype 2D design for real-time image decomposition. The quality of the architecture in case of real-time image decomposition is measured by ‘peak signal-to-noise ratio’ and ‘computation time’, where our proposed design outperforms other similar kind of software- and hardware-based implementations.

Design of parallel and pipelined DA based OBC fir filter for software defined radio

Software Defined Radio (SDR) is a new technology used to implement different wireless communication standard for mobile communication. The Intermediate Frequency (IF) block is the most demanding block in software defined radio. The most important task in intermediate processing block is digital filtering which is carried out by Finite Impulse Response (FIR) filter. One of the major techniques for the calculation of inner product is Distributed Arithmetic (DA) based FIR filter which uses Look Up Table (LUT) to eliminate the need of multiplier. The efficiency of the DA filter is affected with the increasing number of address line and also due to its serial operation. To overcome this problem parallel and pipeline based DA filter using Offset Binary Coding (OBC) for Two Bit At A Time (2-BAAT) is proposed. Our proposed method achieves less area, low power consumption and nominal delay for SDR application.

Fast hardware architecture for fixed-point 2D Gaussian filter

This study presents the hardware architecture for 16-bit, 5 × 5 fixed-point 2D Gaussian kernel. Two filters are proposed, one using generalized kernel and other using separable kernel. The quality analysis of both the filters are obtained for different metrics and it is observed that the generalized filter achieves the best performance compared to all the existing methods. The proposed filters are evaluated on different images and its performance is similar to that of the original filter, evident from the difference in values of Peak Signal to Noise Ratio (PSNR) and Structural Similarity Index Metric (SSIM) of proposed filters to that of the original filter. Based on the principle of Distributed Arithmetic (DA), two hardware architectures, Generalized Filter Architecture (GFA) and Separable Filter Architecture (SFA) are proposed. SFA achieves an improvement in area, delay, power, Area Delay Product (ADP) and Area Power Product (APP) compared to GFA. GFA, on the other hand, achieves high performance compared to the SFA model. The performance of both the architectures are analyzed in terms of max speed and frames per second metric and it is shown that the proposed architectures achieve significantly better performance compared to all the existing techniques.

Optimal Complexity Architectures for Pipelined Distributed Arithmetic-Based LMS Adaptive Filter

This paper presents three optimal-complexity structures (I, II, III) for pipelined distributed arithmetic (DA) based least-mean-square (LMS) adaptive filter. The complexity of proposed structures is reduced by implementing offset-binary-coding (OBC) combinations of input samples on hardware. However, some non-OBC outputs are produced, and subsequently eliminated in the error computation during the initial clock cycles. For achieving more performance benefits, radix-4 OBC combinations of input samples are implemented with the proposed partial product generators. In addition, novel low-complexity implementations for the offset term, weight update block and shift-accumulate unit are also proposed. Analysis shows that byte-complexity of proposed structures vary linearly with the order of DA base unit, while their bit-complexity depends on the topology. All the structures show significant hardware savings, Structure-I has least critical-path and Structure-II, III offer superior convergence performance. Experimental results show that the Structure-I, II and III with 32 nd order filter provide savings 71.13%, 71.83% and 73.08% in area, 68.47%, 70.01% and 72.17% in power, 51.74%, 37.83% and 45.38% in area-per-throughput (APT), 47.33%, 33.72% and 43.19% in power-per-throughput (PPT), 55.11%, 59.66% and 64.20% in slice LUTs, 35.33%, 40.28% and 44.87% in flip-flops over the best existing scheme.

A Variation-Aware Design Methodology for Distributed Arithmetic

Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, new error resilient techniques for DA computation are urgently required to improve robustness against the process, voltage, and temperature (PVT) variations. This paper proposes a new in-situ timing error prevention technique to mitigate the impact of variations in DA circuits by providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the sign extension block and carefully gate-sizing. Therefore, least significant bit (LSB) computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Our approach is demonstrated on a 16-tap finite impulse respons (FIR) filter using the 65 nm CMOS process and the simulation results show that this design can still maintain high-accuracy performance without worst case timing margin, and achieve up to 
 
 
 
 32
 %
 
 
 
 power savings by voltage scaling when the worst case margin is considered with only 
 
 
 
 9
 %
 
 
 
 area overhead.

High speed and low area decision feed-back equalizer with novel memory less distributed arithmetic filter

In this paper an efficient implementation of decision feed back equalizer (DFE) is carried out using novel memory less distributed arithmetic (NMLDA) filter. In wireless transmission systems, DFEs are used to mitigate the inter-symbol interference (ISI). The ISI is occurred due to multi-path propagation of the transmitted signal. High data rate systems demand higher order filters in DFE architectures which increase complexity in hardware design. In our proposed NMLDA design, we have used multiplexers and enhanced compressor adders in place of memory unit and conventional adders. The proposed design occupies lower area and gives higher throughput, when compared to MAC based filter and all other memory based DA filter architectures. By using proposed NMLDA based DFE, the ISI errors in transmission signal, will be minimized and the performance of the transmission system will be enhanced. We have synthesized the NMLDA of 32-tap, 16-tap, 8-tap and 4-tap filters and implemented them on FPGA device. The proposed design has nearly 70% less number of logical elements than OBC DA and 50% less than MDA and offers better throughput than the existing designs when implemented on Altera Cyclone III EP3C55F484C6.

A High-Performance and Energy-Efficient FIR Adaptive Filter Using Approximate Distributed Arithmetic Circuits

In this paper, a fixed-point finite impulse response adaptive filter is proposed using approximate distributed arithmetic (DA) circuits. In this design, the radix-8 Booth algorithm is used to reduce the number of partial products in the DA architecture, although no multiplication is explicitly performed. In addition, the partial products are approximately generated by truncating the input data with an error compensation. To further reduce hardware costs, an approximate Wallace tree is considered for the accumulation of partial products. As a result, the delay, area, and power consumption of the proposed design are significantly reduced. The application of system identification using a 48-tap bandpass filter and a 103-tap high-pass filter shows that the approximate design achieves a similar accuracy as its accurate counterpart. Compared with the state-of-the-art adaptive filter using bit-level pruning in the adder tree (referred to as the delayed least mean square (DLMS) design), it has a lower steady-state mean squared error and a smaller normalized misalignment. Synthesis results show that the proposed design attains on average a 55% reduction in energy per operation (EPO) and a 3.2× throughput per area compared with an accurate design. Moreover, the proposed design achieves 45%-61% lower EPO compared with the DLMS design. A saccadic system using the proposed approximate adaptive filterbased cerebellar model achieves a similar retinal slip as using an accurate filter. These results are promising for the large-scale integration of approximate circuits into high-performance and energy-efficient systems for error-resilient applications.

A cost-efficient error-resilient approach to distributed arithmetic for signal processing

Distributed arithmetic (DA) brings area and power benefits to digital designs relevant to the Internet-of-Things. Therefore, a new error resilient technique for DA computation is proposed to improve robustness against process, voltage, and temperature variations. The proposed approach mitigates the effect of timing violations by first providing a guardband for significant (most significant bit) computations. This guardband is initially achieved by modifying the order of DA serial operations and borrowing time from the least significant bit (LSB) group. Therefore, LSB computation can correspond to the critical path, and timing error can be tolerated at the cost of acceptable accuracy loss. Moreover, the shifted-phase clock signals are applied on the end-point registers, thereby increasing the global guardband without any effect on system sampling rate. Our approach is demonstrated on a 16-tap FIR filter using the 65 nm CMOS process. The simulation results demonstrate that this design can maintain error-free operation without worst case timing margin, and achieve up to 42% power savings by voltage scaling when the worst case margin is considered. This is at the cost of a 6.3% delay and 7.3% overhead.