Parallel Processing Area Research Articles

Study of parallel processing area extraction and data transfer number reduction for automatic GPU offloading of IoT applications

To overcome of the high cost of developing IoT (Internet of Things) services by vertically integrating devices and services, Open IoT has been developed to enable various IoT services to be developed by integrating horizontally separated devices and services. For Open IoT, we have proposed Tacit Computing technology to discover the devices that can provide the data users need on demand and use them dynamically. We have also proposed an automatic GPU (graphics processing unit) offloading method as an elementary technology of Tacit Computing. However, our GPU offloading method can improve only a limited number of applications because it only optimizes the extraction of parallelizable loop statements. Therefore, in this paper, to improve performances of more applications automatically, we propose an improved GPU offloading method with fewer data transfers between the CPU and GPU that can improve performance of many IoT applications. We evaluate our proposed GPU offloading method by applying it to Darknet and Fourier Transform, which are general large applications for CPU, and find that it can process them 3 times and 5 times as quickly as only using CPUs within 10-hour tuning time.

Electronic Voting System with Cloud Based High Performance Computing

Traditional voting system has been replaced by electronic voting systems in most places increasingly. It is efficient, but not efficient enough in terms of cost and capacity. High Performance Computing (HPC) in Cloud computing is a relatively new concept which has been replacing the traditional systems. The HPC has been widely used over the recent years because of its efficiency, reliability, speed and cost. Whereas in the traditional super computing system a lot of cost is involved. The ability of integration of HPC with cloud provided enormous growth in the area of parallel processing and computing. This system may advocate to push the case of promoting electronic voting system for higher traffic scenarios with lower cost requirements. This paper proposes an idea of implementing a fully formed e-voting system integrated with both HPC and Cloud Computing.

Towards concurrent product and supply chain designing: a review of concepts and practices

The modern business, in order to attract and satisfy customers, is compelled to provide low priced, well differentiated products which require faster time to market and have shorter life cycle. These developments have a strong impact on not only procurement logistics but beyond. New challenges are being created for intra firm logistics as well as distribution logistics. The supply chain needs to be agile and resilient in the turbulent global market. It is essential that the design of the product and the supply chain which supports it must be carried out in an integrated manner and concurrently. A comprehensive ‘design for life-cycle’ approach which addresses the integration of product and supply chain design from ‘cradle to cradle’ is desirable. The interfaces of product designing and supply chain may be in the areas of parallel processing, modular design, packaging, storage, transportation, mass customisation and reverse logistics.

Diagnosability of optical multi-mesh hypercube networks under the comparison diagnosis model

Diagnosability of a multiprocessor system is one important study topic in the parallel processing area. As a family of promising optical interconnection topologies for massively parallel computers, the optical multi-mesh hypercube (OMMH) networks integrate positive features of both hypercube and mesh topologies and circumvent the lack of scalability of hypercubes and the large diameter of meshes. This paper studies an (l, m, n)-OMMH network and, proves that its diagnosability under the comparison diagnosis model is n+4 for l≥5, m≥5, n≥3.

Editorial: A Message from the New Editor-in-Chief

1045-9219/06/$20.00 © 2006 IEEE Published by the IEEE Computer Society For information on obtaining reprints of this article, please send e-mail to: tpds@computer.org. I T is a great privilege and honor to serve as the Editor-in-Chief (EIC) of the IEEE Transactions on Parallel and Distributed Systems (TPDS). TPDS is a relatively young journal that started in 1990, yet it has become the premier outlet for research publications in the parallel and distributed processing area. The credit for this accomplishment goes to all the four previous EICs, associate editors, reviewers, and the authors who submitted their papers to TPDS for publication. Currently, the first review turn around time for a submission is below six months, meaning that a paper can get accepted for TPDS as fast as a conference. At the same time, a paper submitted to TPDS can go through minor or major revision and, finally, get accepted, which is not possible in conferences. The timely review and publication of papers in TPDS is now possible because of the combined effort of the last EIC, Pen-Chung Yew, and his staff. While I am assuming the EIC job in a very comfortable position with regard to visibility and publication timing, there are a few challenges that need our urgent attention. TPDS was born while research in the area of parallel processing was at its peak. Also, the competition with other journals and conferences was not that fierce. Now, we need to take a closer look at the scope of TPDS and revise it to include emerging areas, technological advancements, and experimental results in the systems area to boost the number of submissions. I shall invite well-recognized researchers to organize special issues and appoint some of them to the editorial board. I also plan to appoint an associate Editor-in-Chief to help me in various areas. In order to reduce the delay in publication further, I would urge the associate editors to administratively reject submissions if the research is outdated, and cut down on major revisions, recommending some of them for new submission after revision. I would urge understanding on the part of authors if they are advised to do so. I would also request the associate editors to review some papers themselves instead of waiting for the reviewer’s response indefinitely. The TPDS staff will closely monitor the review time of a paper and bring it to our attention if such an action is needed. An IEEE Transactions cannot gain a good reputation without the active support and participation of the research community in the area. I invite you to send me your suggestions to further enhance the quality and visibility of the TPDS. I look forward to working with you during the next two years to take TPDS to the next level of excellence.

Fault-Tolerant Pancyclicity of the Mobius Cubes

The Mobius cube MQ n proposed by Cull et al. is an alternative to the popular hypercube network. Recently, MQ n was shown to be pancyclic, i.e., cycles of any lengths at least four can be embedded into it. Due to the importance of the fault tolerance in the parallel processing area, in this paper, we study an injured MQ n with mixed node and link faults. We show that it is (n - 2)-fault-tolerant pancyclic for n ≥ 3, that is, an injured n-dimensional MQ n is still pancyclic with up to (n-2) faults. Furthermore, our result is optimal.

Diagnosability of crossed cubes under the comparison diagnosis model

Diagnosability of a multiprocessor system is one important study topic in the parallel processing area. As a hypercube variant, the crossed cube has many attractive properties. The diameter, wide diameter and fault diameter of it are all approximately half of those of the hypercube. The power that the crossed cube simulates trees and cycles is stronger than the hypercube. Because of these advantages of the crossed cube, it has attracted much attention from researchers. We show that the n-dimensional crossed cube is n-diagnosable under a major diagnosis model-the comparison diagnosis model proposed by Malek (1980) and Maeng and Malek (1981) if n/spl ges/4. According to this, the polynomial algorithm presented by Sengupta and Dahbura (1992) may be used to diagnose the n-dimensional crossed cube, provided that the number of the faulty nodes in the n-dimensional crossed cube does not exceed n. The conclusion of this paper also indicates that the diagnosability of the n-dimensional crossed cube is the same as that of the n-dimensional hypercube when n>5 and better than that of the n-dimensional hypercube when n=4.

Lower bounds on precedence-constrained scheduling for parallel processors

We consider two general precedence-constrained scheduling problems that have wide applicability in the areas of parallel processing, high performance compiling, and digital system synthesis. These problems are intractable so it is important to be able to compute tight bounds on their solutions. A tight lower bound on makespan scheduling can be obtained by replacing precedence constraints with release and due dates, giving a problem that can be efficiently solved. We demonstrate that recursively applying this approach yields a bound that is provably tighter than other known bounds, and experimentally shown to achieve the optimal value at least 90.3% of the time over a synthetic benchmark. We compute the best known lower bound on weighted completion time scheduling by applying the recent discovery of a new algorithm for solving a related scheduling problem. Experiments show that this bound significantly outperforms the linear programming-based bound. We have therefore demonstrated that combinatorial algorithms can be a valuable alternative to linear programming for computing tight bounds on large scheduling problems.

Mapping pyramids into 3-D meshes

Embedding one parallel architecture into another is very important in the area of parallel processing because parallel architectures can vary widely. Given a pyramid architecture of (4N - 1)/3 node...

DPL

T HE NEED FOR a powerful, easy to use, parallel language continues despite very significant advances in the area of parallel processing. Many parallel languages are simply old sequential languages with parallel constructs added. This research describes the Data Parallel Language (DPL), a parallel language built from its foundations on parallel concepts. DPL bases much of its expression on data parallelism found in APL2 and Fortran90. DPL uses a method based on Petri nets for controlling the execution of groups of statements. Therefore, it allows the user to express parallel algorithms in a natural, array-based method that is independent of the underlying parallel architecture.APL has been recognized as a naturally parallel language because of its ability to express algorithms on array arguments directly. This eliminates the need for a programmer to convert them into sequential loops. Fortran90 has recently adopted similar data parallel concepts into the Fortran language. DPL borrows from APL2 and Fortran90 to define an extensive data parallel function set. Functions in DPL are designed to take arrays as arguments and map the execution onto the underlying parallel machine.Petri nets provide a very elegant model for expressing concurrent and asynchronous operations. DPL uses the semantics of Petri nets to provide a general purpose control structure. DPL frees the programmer from having a fixed set of parallel control constructs, such as are provided in most parallel languages. Rather, it provides a method to express parallel execution based only on the input and output conditions of parts of the program.This work provides the complete syntax and semantics of DPL and then explores its use. The expressiveness of the language is demonstrated by showing how common parallel structures can be implemented. The ease of use is analyzed using a study of existing APL2 code to determine the amount of implicit parallelism in an array language. Some of the issues of compiling DPL are discussed and theoretical speedups are given. The advantages of DPL over other languages, especially APL2 and Fortran90, are outlined.

Embedding binary trees into crossed cubes

The recently introduced interconnection network, crossed cube, has attracted much attention in the parallel processing area due to its many attractive features. Like the ordinary hypercube, the n-dimensional crossed cube is a regular graph with 2/sup n/ vertices and n2/sup n-1/ edges. The diameter of the crossed cube is approximately half that of the ordinary hypercube. These advantages of the crossed cube motivated the study of how well it can simulate other networks such as the complete binary tree. We show that the (2/sup n/-1) node complete binary tree can be embedded into the n-dimensional crossed cube with dilation 1. >

A high speed systolic architecture for labeling connected components in an image

Connected components detection and labeling is an essential step in many image analysis techniques. The efficiency of the connected components labeling algorithm is critical for many image processing and machine vision applications that require real time response. The advances in the areas of parallel processing and VLSI technology can be exploited in designing hardware algorithms of high speed and throughput. In this paper, the authors propose a systolic algorithm and architecture for finding connected components in an image. The architecture is simple and can be implemented as a special purpose VLSI chip. Although, the algorithm has a time complexity of O(N/sup 2/), this is in terms of the actual clock cycle which is estimated as 25 nano seconds. The proposed hardware can process a 128/spl times/128 image in 0.85 msec and uses 128 processors whereas the MPP requires 94.6 msec with 16384 processors. The only special purpose hardware that exists requires 300 msec to label a 512/spl times/512 image which can be accomplished in 13.5 msec using the authors' proposed hardware. >

A reusable load balancer for parallel search problems

In this paper, we describe the design and implementation of a reusable load balancer for parallelsearch problems. Parallel search problems are a significant research topic in the parallel processing area: these applications expose irregularities that require dynamic load balancing techniques. Software for dynamic load balancing should be reusable. Our load balancer can be developed independently from the application -and thus be replaced and reused- as it does not directly interact with the application itself. Our prototype implementation runs on a transputer system; we used different load balancing strategies: sender-initiated, receiver-initiated and symmetrically-initiated. The modularity of our load balancer is illustrated by the fact that we could easily replace the load balancer by different alternatives and compare the performance results.

An Approach To Program Representation OfThe R&F Systolic LU-factorizationAlgorithm

In this work, we view systolic algorithms as programs, each consisting of a multiple assignment statement that describes the algorithmic operation and the synchronous data movement between the nodes of the systolic architecture. We carry out the development of the LU-factorization algorithm for band matrices using the R&F technique (Bekakos and Evans [9], [2]) and applying for its design a traditional program development technique based on an invariant. INTRODUCTION One of the most significant fields in the area of parallel processing is that of systolic algorithms, which are usually illustrated by snapshots of nodes and lines, descriptions of processing at each node in the snapshot and data movement between nodes. A pictorial representation of an algorithm does not lead itself readily to a proof of correctness, although it suggests that it can be implemented on a VLSI chip. From all the above it becomes apparent that we do not attempt to propose a VLSI design methodology for systolic algorithms, because we do not consider many of the limitations that would be imposed by any real system. Although such a sort of proposal concerns a later stage in the design, through the use of a traditional program development technique, for the R&F method, a design methodology seems that could be derived mechanically. The primary contribution of this work is the representation of the R&F systolic LU-factorization algorithm by a program derived from an invariant. Transactions on Information and Communications Technologies vol 3, © 1993 WIT Press, www.witpress.com, ISSN 1743-3517 368 Applications of Supercomputers in Engineering SYSTOLIC ALGORITHM REPRESENTATION Multiple Assignment Statements Our program will make use of multiple assignment statements. A multiple assignment statement of the form, x,y:=f(x',y),g(x,y'), assigns f(x, y) and g(x ,y) to x, y, respectively, where x ,y are the values of x, y prior to the execution of the statement. We shall allow the right sides of assignments to be conditional expressions, e.g. 0, if a > 0 <:= i 1, if a < 0