Layout Area Research Articles

Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications

Data converters such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital-to-time converters (DTCs), time-to-digital converters (TDCs), among others, are considered some of the most essential blocks in the field of integrated circuit design. In this work, we introduce a novel type of data converter known as the Digital-to-Pulse converter (DPC) and present its novel analog flow circuit implementation. The DPC system is a critical component in emerging artificial neural network accelerators and in-memory computing systems. The DPC system presented in this study offers two distinct operating modes. The first mode is the generation of a single pulse with a width that is modulated by the digital input. The second mode is an n-bit digital to discrete pulse converter, where the number of generated pulses is directly related to the value of the digital input. The proposed DPC system offers designers a high level of flexibility in shaping the characteristics of the output pulses, including the number of pulses, pulse width, and pulse amplitude. This empowers designers to accommodate different application requirements and scenarios effectively. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulation and analysis. The results indicate a significant enhancement in average power consumption (∼12×), layout area (∼5×), and Latency (∼1.4×) with the proposed system compared to the digital Register Transfer Level (RTL) implementation under a power supply of 1.8V and a clock frequency of 1 GHz in the Application Specific Integrated Circuits (ASIC) flow. This demonstrates the suitability of the proposed system for low-power and high-speed applications.

Volumetric Drag Coefficients for Generic Urban Configurations: Insights from Canopy Flow Analysis

Alternative drag approaches for representing unresolved buildings were proposed in literature for computational fluid dynamics (CFD) simulation of macroscopic urban airflow. As a contribution, the present work derives the volumetric drag coefficient (Cd*) through canopy drag and velocity analysis and provides appropriate correlations for Cd*against urban morphological parameters. A total of 72 cases across various urban configurations are investigated, categorized by building typology, horizontal layout, height variability, and plan area density (λp, from 0.0625 to 0.57). Reynolds-Averaged Navier-Stokes (RANS) simulations with periodic boundary conditions are performed to model fully developed flows. Results for the normalized drag force and superficial velocity and their relations with λp are evaluated. Subsequent evaluation of the profiles for the sectional coefficients (Cd*(Z)) reveals four distinct types with variations in uniform-height cases and combinations in varying-height cases. A throughout correlations analysis, facilitated by data transformation, identifies the straightforward relations between Cd* and frontal area density (λf) and tortuosity (τ). The followed stepwise regression provides a recommended formula for Cd*, demonstrating a proper fit with the simulated values. These findings facilitate the understanding and appropriate estimation of Cd* and Cd*(Z), promoting the application of macroscopic turbulence models, for neighborhood-scale wind and air quality studies.

LIC-CGAN: fast lithography latent images calculation method for large-area masks using deep learning

Latent image calculation for large-area masks is an indispensable but time-consuming step in lithography simulation. This paper presents LIC-CGAN, a fast method for three-dimensional (3D) latent image calculation of large-area masks using deep learning. Initially, the library of mask clips and their corresponding latent images is established, which is then used to train conditional generative adversarial networks (CGANs). The large area layout is divided into mask clips based on local pattern features. If a mask clip matches one from the training library, its latent image can be obtained directly. Otherwise, the CGANs are employed to calculate its local latent image. Finally, all local latent images are synthesized to simulate the entire latent image. The proposed method is applied to lithography simulations for display panels, demonstrating high accuracy and a speed-up of 2.5 to 4.7 times compared to the rigorous process.

Addressing output ripples in low-power CMOS-based multistage DC-DC boost converters for self-powered electrochemical sensors applications

In modern electronic systems, the DC-DC converter plays a pivotal role by facilitating the conversion of direct current (DC) from one voltage level to another. Given the diverse voltage requirements of contemporary chips, a single chip may encompass multiple circuitry groupings, each necessitating specific voltage levels for optimal functionality. To address this need, voltage converters are essential, whether it involves increasing the voltage (Boost converter), decreasing the voltage level (Buck converter), or performing both functions (Buck-boost converter). This paper presents a novel multistage DC-DC converter designed to minimize voltage ripples. The proposed three-stage DC-DC converter is supplied with a 1.5-V input and achieves a four-boost ratio. The cascaded architecture integrates switching capacitors and a gyrator, complemented by a terminating low-pass filter, resulting in a minimal voltage ripple of 0.0003 % relative to the maximum output voltage. Notably, integrating the gyrator enables an inductorless CMOS-based architecture, significantly reducing layout area to 30 × 140 μm2. Furthermore, the converter's transient response was simulated, yielding a response time of 90 ms.

Assessing the Cascading Post-Earthquake Fire-Risk Scenario in Urban Centres

The frequency of urban fires has grown in recent years everywhere, especially in historic districts, including in Portugal, due to the existence of sensitive igniting materials, the proximity of buildings, the complex urban layout, and the presence of many people. The current study proposes a technique, applied in the Baixa Pombalina (downtown) area in Lisbon, to undertake an appropriate evaluation of the post-earthquake fire cascading effect, which may cause major damage. The earthquake vulnerability and damage scenario were carried out using the Risk-UE method. An empirical fire ignition model was then applied to determine the quantity and location of fire ignitions for different return periods. Furthermore, the simple fire spread Hamada’s model was applied to both the equally spaced grid buildings, as in the original Hamada procedure, and the current study area layout for different time thresholds. Finally, the risk assessment for both models was carried out, allowing for the estimation of earthquake and fire losses, respectively. The results demonstrated that the models are comparable, showing that the Hamada model might be a useful tool for large-scale evaluations aimed at disaster-risk reduction and management since it gives useful information for managing and reducing natural and anthropogenic hazards.

Design of SRAM cell using an optimized D-latch in quantum-dot cellular automata (QCA) technology

A newer nanoscale technology called quantum-dot cellular automata (QCA) has been used by researchers to design digital circuits in place of the more traditional complementary metal–oxide semiconductor (CMOS) technology. This recent development in the technology change is due to the problems faced by CMOS technology in terms of power consumption and physical limitations. The advantages of QCA technology over CMOS technology are high density, low power consumption, high-speed operation, and less footprint area. This research provides a novel circuit for D-latch and static random access memory (SRAM) cells based on QCA technology. Initially, a D-latch circuit is proposed with a layout area of 0.01 μm2, a 0.5 clock cycle delay (latency), and a cell count of 18 QCA cells. Furthermore, an SRAM cell is proposed using the same D-latch circuit, which uses cell counts of 26 QCA cells and contributes to a layout area of 0.02 μm2 with a 0.75 clock cycle delay (latency). It is observed that our proposed circuits have a smaller layout area, fewer QCA cell counts, and a lower clock cycle delay (latency) than existing circuits.

Urban expansion in highly populous East Asian megacities during 1990–2020: Tokyo, Seoul, Beijing, and Shanghai

The world is experiencing unprecedented urbanization, particularly through the continuous growth of megacities, leading to significant urban land expansion. The spatial layout and growth patterns of urban areas play a critical role in determining cities' sustainable development. However, the optimal path for cities undergoing rapid urbanization remains uncertain. This study examines four megacities—Tokyo, Seoul, Beijing, and Shanghai—and, from the perspective of urban land density, compares their patterns and processes of land expansion in 1990, 2000, 2010, and 2020. Findings reveal that the urban land area of China's megacities has expanded nearly fourfold over the past three decades. Meanwhile, Tokyo and Seoul have adopted a polycentric urban structure, becoming increasingly compact. In contrast, Beijing and Shanghai are only beginning to show signs of polycentric development. The study concludes that cities experiencing rapid growth should not impose excessive limitations on urban expansion. Polycentric and compact development has become a critical strategy for megacities. These insights offer valuable guidance for urban planning and sustainable development in both established and emerging megacities across East Asia.

Low-Temperature Drift Bandgap Reference Based on Exponential Compensation Design

Abstract In analogue and mixed-signal systems, a stable and accurate reference voltage source is essential to ensure system performance. In this paper, a high-precision bandgap reference (BGR) with a high power supply ripple rejection ratio (PSRR) and lowtemperature drift is proposed, which mainly consists of a core circuit, an exponential temperature compensation circuit, a PSRR enhancement circuit and a start-up circuit. The PSRR is improved by using a PSRR enhancement circuit and a low-pass filter. An exponential compensation circuit is used to reduce the temperature drift coefficient of the bandgap reference. Based on a 0.18 μm BCD process for design and simulation, the output reference voltage is 1.203 V with a temperature drift coefficient of 2.635 ppm/°C over the temperature range of −40°C to 125°C. The PSRR is −144.4 dB at a frequency of 10 Hz, and −43.8 dB at a frequency of 1 MHz, and the layout area is 316 μm × 156 μm.

Producer services agglomeration and low-carbon economic transition: the role of economic growth target constraint

Abstract Objective. Producer services are an intermediate input factor that permeates every link in the industrial production chain and is essential to the growth of a low-carbon economy. This study aims to elucidate the connection between producer services agglomeration (PSA) and low-carbon economic transition. Methods. Based on China’s provincial panel data from 2004 to 2021, we empirically test the influence of PSA on low-carbon economic transition using a two-way fixed effects model, and utilize government work reports to construct an indicator of economic growth target constraints and its characteristics to further explore its moderating effect. Results. PSA contributes to enhancing low-carbon economic transition. The heterogeneity test finds that PSA significantly helps low-carbon economic transition in the east and west regions, but not in the central region. The quantile regression findings demonstrate that PSA is more effective at raising the level of low-carbon economic transition at the 10th and 90th quantiles, which indicates that the carbon reduction and efficiency enhancement effects of PSA play a greater role in regions with lower and higher low-carbon economic transition levels. Further research presents that the economic growth target constraint negatively moderates PSA’s impact on low-carbon economic transition, but this constraint characterized by soft constraints strengthens the positive effect of PSA on low-carbon economic transition. Implications. In view of this, the government can foster PSA in accordance with local conditions, optimize agglomeration area layout, and establish a scientific and reasonable government target management system to strengthen low-carbon and high-quality economic development.

Threats and Membership of Kandovan in UNESCO

This research aims to explore the heritage and tourist zone of Kandovan in Iran, currently undergoing the UNESCO registration process, but facing rejection due to threats in the area. The primary goal is to offer valuable insights to the Kandovan municipality and officials, assisting them in recognizing and mitigating the prevailing threats to secure the designation of Kandovan as a UNESCO heritage site. The examination of the heritage zone in Kandovan, Iran, involved a comprehensive approach incorporating a literature review, interviews, and on-site observations. Interviews were conducted with Kandovan officials to inquire about the heritage criteria, existing challenges and threats, future initiatives, and notable transformations. Field observations were employed to assess the physical characteristics and layout of the heritage area, residents' interactions with the heritage sites, and issues affecting tourists, including accommodation shortages and architectural concerns. The findings of this study have identified the threats present in Kandovan, as acknowledged by UNESCO. The majority of these threats have emerged as a consequence of the expanding urbanization and tourism activities in Kandovan, emphasizing the need for effective management and controlled development in the area.

Research on the Identification, Network Construction, and Optimization of Ecological Spaces in Metropolitan Areas Based on the Concept of Production-Living-Ecological Space

In the strategic orientation of promoting high-quality development of metropolitan areas, ecological space is not only the core carrier for maintaining regional ecological balance and harmony but also a key element in shaping the scientific layout of metropolitan areas and promoting harmonious coexistence between cities and nature. This paper takes the Chang-Zhu-Tan metropolitan area as the research object and identifies and classifies ecological space based on the “Production-Life-Ecology” concept, extracts core ecological source areas through the minimum resistance model, and generates ecological resistance surfaces. Then, three types of ecological space corridors are constructed by using the MCR gravity model. This study finds that the ecological space in the Chang-Zhu-Tan metropolitan area is seriously fragmented, the number of corridors is insufficient, and the spatial configuration of the “Production-Life-Ecology” is imbalanced in the region and proposes optimization models and strategies in combination with the spatial network approach to identify and classify ecological space patterns for the metropolitan area. Accordingly, the study proposes optimization models and strategies based on the spatial network approach to provide theoretical support and practical guidance for the ecological spatial pattern and sustainable development of the metropolitan area.

Novel Power-Efficient Fast-Locking Phase-Locked Loop Based on Adaptive Time-to-Digital Converter-Aided Acceleration Compensation Technology

This paper proposes an adaptive acceleration lock compensation technology for phase-locked loops (PLLs) based on a novel dual-mode programmable ring voltage-controlled oscillator (ring-VCO). In addition, a time-to-digital converter (TDC) is designed to accurately quantify the phase difference from the phase frequency detector (PFD) in order to optimize the dead-zone effect while dynamically switching an auxiliary charge pump (CP) module to realize fast phase locking. Furthermore, a TDC-controlled three/five-stage dual-mode adaptively continuously switched VCO is proposed to optimize the phase noise (PN) and power efficiency, leading to an optimal performance tradeoff of the PLL. Based on the 180 nm/1.8 V standard CMOS technology, the complete PLL design and a corresponding simulation analysis are implemented. The results show that, with a 1 GHz reference signal as the input, the output frequency is 50–324 MHz, with a wide tuning range of 260 MHz and a low phase noise of −98.07 dBc/Hz@1 MHz. The key phase-locking time is reduced to 1.11 μs, and the power dissipation is lowered to 1.86 mW with a layout area of 66 μm × 128 μm. A significantly remarkable multiobjective performance tradeoff with topology optimization is realized, which is in contrast to several similar design cases of PLLs.

Complementary Polarizer SOT-MRAM for Low-Power and Robust On-Chip Memory Applications

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM) has been proposed to address the sensing reliability issues caused by the single-ended sensing of STT-MRAM. However, it results in a three-fold increase in the free layer (FL) area compared to STT-MRAM, leading to a higher write current. Moreover, the read and write current paths in this memory are the same, thus preventing the optimization of each operation. To address these, in this study, we proposed a complementary polarized spin-orbit torque MRAM (CPSOT-MRAM), which tackles these issues through the SOT mechanism. This CPSOT-MRAM retains the advantages of CPSTT-MRAM while significantly alleviating the high write current requirement issue. Furthermore, the separation of the read and write current paths enables the optimization of each operation. Compared to CPSTT-MRAM, the proposed CPSOT-MRAM achieves a 4.0× and 2.8× improvement in write and read power, respectively, and a 20% reduction in layout area.

Chemical plant optimization layout based on the domino hazard index considering the fixed hazard unit outside the available area

The layout of chemical plants is a significant step to promote the safe and efficient operation of a chemical factory. In the actual production process, the chemical process plant layout may be affected by immovable hazards outside the available layout area. In this paper, the external hazard unit is arranged as one of the chemical process plants. The domino effect potential of all chemical process plants is quantified by using the classical domino hazard index (DHI). A layout optimization model considering the effects of external hazard units has been proposed to obtain the optimal plant layout from economic and safety aspects. The feasible layout solutions are obtained under the orientation, boundary and non-overlapping constraints by the non-dominated sorting genetic algorithm II (NSGA-Ⅱ). The proposed model is further analyzed through a hypothetical case of three storage tanks outside the acrylic acid (AA) production plant layout area. The results show that the total cost range for the optimal solution is 650348–1365443 $, with corresponding DHI values ranging from 29 to 129. The plant with larger DHI value will be arranged to far away from the external hazard units to obtain a safer layout. This work can provide rational layout solutions for the layout designers to make different decisions according to the actual situation.

Spatial evolution and influencing factors of water-town settlements in Southern China: evidence from 942 villages in Zhongshan City

ABSTRACT Zhongshan, a city characterized by its profound historical heritage and distinctive rural civilization, has been consistently influenced by traditional agricultural practices throughout its history. This research conducts an in-depth exploration of Zhongshan’s unique rural spaces, systematically examining the evolutionary trends and determinants of Zhongshan’s water-town settlements across different historical epochs through the application of multidimensional spatial analysis techniques. The results indicate that these settlements exhibited cohesive spatial distribution characteristics across five historical periods. Notably, there was a significant clustering effect during the Ming and Qing dynasties, while Before the Qing dynasty, the spatial distribution of the settlements presented a pattern with multiple core areas coexisting. After the Qing dynasty, the spatial layout of these principal core areas stabilized and gradually diffused to surrounding areas, forming a balanced and continuous distribution pattern. Throughout the study period, the spatial pattern of the water-town settlements exhibited characteristics of five primary core areas and several secondary core areas. Concurrently, the centroid of the water-town settlements consistently shifted southeastward. When examining the intensity of influence on spatial evolution, the study found that socio-economic (q = 0.345) and accessibility factors (q = 0.356) exert a greater impact on the spatial distribution of rural settlements than do natural environmental factors (q = 0.136). However, the interaction between natural environmental factors and socio-economic and accessibility factors provides greater explanatory power than the interactions within natural factors alone. This suggests that in a specific socio-economic context, the impact of the natural environment on water-town settlements is enhanced. Furthermore, multivariate linear regression analysis demonstrates that the rural population, regional economic status, proximity to urban centers, and the distribution of water bodies positively influence the spatial evolution of water-town settlements.

A Low-Power Continuous-Time Delta-Sigma Analogue-to-Digital Converter for the Neural Network Architecture of Battery State Estimation

Electric vehicle systems and smart grid systems are setting stringent development targets to respond to global trends in energy saving, carbon reduction, and sustainable environmental development. In the field of batteries, there has been extensive discussion on the estimation of battery charge. In battery management systems (BMSs) and charging/discharging systems, the accuracy of the measurement of battery physical parameters is critical, as it directly affects the system, alongside the algorithm’s estimation and error correction. Therefore, this paper proposes incorporating a low-power continuous-time delta-sigma analogue-to-digital converter into a battery measurement system to support deep learning algorithms for battery state estimation. This approach aims to maintain the accuracy of battery state estimation while reducing latency and overall system power consumption. Implemented using the UMC 0.18 μm CMOS 1P6M process, the proposed design achieves a measured signal-to-noise distortion ratio (SNDR) of 78.42 dB, an effective number of bits (ENOB) of 12.73 bits, and a power consumption of approximately 15.97 μW. The chip layout area is 0.67 mm × 0.56 mm. By applying delta-sigma modulators to energy management systems, this solution aims to increase the total number of battery monitoring units while reducing overall power consumption and construction costs.

An efficient new design of nano-scale comparator circuits using quantum-dot technology

Traditional semiconductor-based technology has recently faced many issues, such as physical scalability constraints and short-channel properties. Much research on nano-scale designs has resulted in these flaws. Quantum-dot Cellular Automata (QCA) is a promising nanotechnology solution for solving CMOS-related issues. The 4-dot squared cell is identified as the main feature of this technology. Also, a comparator is an essential electronic device that compares 2 voltages or currents. It is frequently employed to confirm whether an input has achieved a predefined value or not. So, the design of the QCA-based comparator is one of the interesting lines in recent studies. However, cell and area consumption limits the circuit design in the most relevant research. As a result, two efficient comparator circuits based on the inherent rules of quantum dots have been presented in this work. The proposed 1-bit design employs 35 quantum cells in a 0.04 μm2 compact layout space. Also, the proposed 2-bit design uses 173 cells in a 0.19 μm2 compact layout area. These circuits, which are built across three layers of 90-degree cells, remove the need for coplanar crossovers, ensuring accessible inputs and outputs. The presented 1-bit comparator circuit uses 3 majority gates with three inputs. The first output signal in 1-bit comparator is generated after 0.75 clock phases and in 2-bit design after 1.25 clock phases. QCADesigner-E evaluated the suggested circuits' practical accuracy, cost, and power. The results showed that the proposed designs are extremely efficient in cell and area consumption compared to the state-of-the-art designs.

Design of dual port 9T SRAM cell with parallel processing and high performance computing

Abstract To meet industry requirements of higher transistor count SRAM cells this paper is proposing, a nine-transistor configuration static random access memory (SRAM) cell which is accessible by dual bit line and performing simultaneous read and write operations. The suggested 9T (P9T PS) cell is constructed at 32 nm CMOS and is operating at an operating voltage 0.9 V. To justify the refined performance of proposed design various analysis are carried out that shows the static noise margins (SNM) that occurs while executing the read operation is 0.368 V and hold operation by the cell is 0.364 V, while the write operation has an SNM of 0.422 V. The access time for write and read functions of the cell is found to be 1.2 nS and 4.5 nS respectively. The P9T PS SRAM is compared with other dual-port and single-port 9T SRAM cells is stand out to be pre-eminence in performance in terms of noise immunity, temperature variations, power consumption (static and dynamic both), power delay product (PDP), SNM to PDP and area ratio (SAPR) and electric quality matric. Total leakage power for P9T PS cell is found to be 22.1 nW. The P9T PS bit cell is also found to be power efficient as it is consuming minimal power for all of the operations. Area layout of the P9T (PS) is found to be 22.372 μm2. The results are also supported by the process corner variation analysis for four different corners. LT-spice software is used to carry out all the simulations and analysis.

Power-efficient wideband programmable pseudo differential ring oscillator CP-PLL

A power-efficient, wide-band, programmable pseudo-differential ring-oscillator charge-pump phase-locked loop (CP-PLL) is proposed. The ring-VCO, characterized by its low power consumption and broadband, is achieved based on a feedforward pseudo-differential configuration. The linearity of ring-VCO is improved by using the source negative feedback topology. Through the rail-to-rail operatingamplifier clamping current source, the current matching accuracy is improved to realize a high-performance CP circuit. The results show that the output frequency range of the phase-locked loop is 0.6–6 GHz at a 1.2 V supply voltage, and the power consumption is 1.372 mW at 5 GHz with a lock-up time of 1.72 μs and RMS jitter of 9.3 ps. The power consumption is as low as 0.643 mW at 2.5 GHz and 1.067 mW at 4 GHz, and the final layout area is 0.00716 mm2. The implemented CP-PLL can be used effectively in wireless RF communication system of NB-IoT and intelligent edge computing scenario.

DecorPGNet: Functional Area Division and Layout Algorithm Model in Living Rooms of Chinese Apartment-Style Family Homes

DecorPGNet: Functional Area Division and Layout Algorithm Model in Living Rooms of Chinese Apartment-Style Family Homes