Area Efficient Finite Impulse Response Research Articles

Performance Analysis of High Speed and Area Efficient Finite Impulse Response Filters

This study represents the designing and implementation of a bandpass finite impulse response (FIR) filter of order 31 using windowing techniques. The frequency parameters used are of a typical GSM receiver,19 which is one of the applications of software-defined radio (SDR). To minimize filter area, various multiplication techniques like a canonical signed digit, Vedic multiplier, booth multiplier, and modified booth multiplier are used. Adders like ripple carry adder, carry save adder, carry look ahead adder, and Kogge-Stone adder are used to add the product from the multiplier unit. A comparison between three different windows has been made. The FIR is designed in MATLAB using a windowing technique. Then it is synthesized on Xilinx 14.7, Virtex 6 XC6VLX760, whose results are included in this paper.

Resource minimization and power reduction of ESPFFIR filter using unified adder/subtractor

Digital filters are the important processing elements in most of the digital signal processing system designs, ranging from medical signal processing to wireless communication. Low power and area efficient Finite Impulse Response filter is designed with the aid of parallel processing which increases the throughput. Symmetric property reduces the multipliers into half in Even Symmetric Parallel Fast Finite Impulse Response (ESPFFIR) filters. The adder and the subtractor present in the pre/post-processing blocks increase in accordance with the block size L of ESPFFIR filter which in turn increases the numbers of unified operators. The canonical signed digit representation of the coefficient in the design Multiple Constant Multiplications (MCM) based multipliers has the advantages of utilizing unified operators in sub-filter block of ESPFFIR. To reduce the power consumption and resource utilization of the ESPFFIR filter, the unified operator used in the pre/post processing and MCM blocks are replaced by unified adder subtractor (UAS). The UAS utilizes fewer resources for simultaneous calculation of sum and difference of two operands with less area and low power consumption. This paper shows the design of 16-bit Square Root (SQRT) UAS CSLA adder using UAS logical element to reduce the area utilization, power consumption and delay. Then the Heuristic of cumulative benefit (Hcub) based MCM multiplier is designed using UAS. The existing SQRT BEC CSLA adder and subtractor with same input present in the pre/post processing block of the ESPFFIR filters are replaced by a single SQRT UAS CSLA in suitable places. The Hcub MCM used in the sub-filter blocks of the ESPFFIR are replaced using SQRT UAS CSLA based MCM multiplier. The SQRT UAS CSLA consumes 78% less area, 29.51% less power and 24% less delay when compared to the BEC CSLA 2 (one BEC based CSLA Adder plus one BEC based CSLA Subtractor). Finally, the SQRT UAS CSLA adder and Hcub based UAS MCM multipliers are used to design the filter, the overall area and power consumption of UAS based ESPFFIR is reduced compared with the existing BEC based ESPFFIR filter. Cadence RC tool is used for analysis.

VLSI Realization of Area efficient FIR Filters

Arithmetic circuit Multiplication happens oftentimes in finite impulse response (FIR) filters, quick Fourier transforms, distinct trigonometric function transforms, convolution, and to avoid wasting vital temporal order consumption of a VLSI style. Here, we have a tendency to propose planning of FIR filter exploitation high speed & space economical multiplier factor adopting the new implementing approach exploitation changed radix-4 booth multiplier factor. The multiplier factor is intended by a changed Booth formula that is controlled by a detection unit exploitation associate degree logic gate. The changed booth formula can scale back the amount of partial merchandise generated by an element of two.

Low-power and area-efficient FIR filter implementation suitable for multiple taps

This paper describes a 32-tap finite impulse response (FIR) filter with two 16-tap macros suitable for multiple taps. The derived condition for a coded coefficient and data block shows 35% savings in power consumption and 44% improvement in occupied area compared to a typical radix-4 modified Booth algorithm. According to the condition and separated shifting-accessing clock scheme, we have implemented a 32-tap FIR filter in 0.6-/spl mu/m CMOS technology with three levels of metal. The chip that occupies 2.3/spl times/2.5 mm/sup 2/ of silicon area has an operating frequency of 20 MHz and consumes 75 mW at V/sub dd/=3.3 V.

Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS

A two-sample per cycle, programmable five-tap, area-efficient finite-impulse response (FIR) filter for hard-disk drive PRML read channels is presented. The design is optimized for low power, achieving a figure of 6.25 /spl mu/W/MHz with a gate density of 2.3 K, by a combination of algorithmic, architectural, circuit-level, and layout techniques.