Sigma-delta Modulator Architecture Research Articles

A Systematic Method for Scaling Coefficients of the Continuous-Time Low-Pass ΣΔ Modulator Using a Simulink-Based Toolbox

The sigma-delta modulator (SDM) is one of the well-established data converter architectures. It is well-known for achieving a high signal-to-noise ratio (SNR). In the SDM, the integrators in the loop filter could suffer from overloading if the signal swing exceeds its maximum level, which leads to performance and SNR degradation. Thus, scaling the system coefficients is needed, such that there is no overloading for the integrators. In this work, we present a systematic general method that could be used for scaling the signal swings in the continuous-time low-pass sigma-delta modulator (SDM). The proposed method can be applied to any continuous-time low-pass SDM architecture, and it includes the scaling of all the possible combinations of the system coefficients. Moreover, an open-source Simulink-based toolbox that includes the systematic method is presented. This toolbox could help the designer to execute the scaling process and the simulations in an efficient way. In addition to that, a design example is discussed to illustrate the proposed method, wherein the presented toolbox is used for simulations, and the simulation results are shown.

Frequency-Agile Real-Time All-Digital Transmitter With 1 GHz of Bandwidth

This paper presents an all-digital transmitter implemented in a field programmable gate array (FPGA) that surpasses the state of art in terms of carrier frequency agility as well as in bandwidth using a single multi-gigabit transmitter. These figures of merit were achieved through the optimization of the delta-sigma modulator architecture as well as by the utilization of higher-order filters in such modulator. Results show an error vector magnitude (EVM) of around 4% for carrier frequencies in the 2 to 9 GHz range and under 8% in the 1 to 2 GHz and 9 to 12 GHz range using a 1 GHz bandwidth, 16-QAM signal, which would comply with EVM standards under the 5G protocol.

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

Multi-Band Transmission Using Reconfigurable Complex Multi-Band Delta Sigma Polar Modulator

This brief presents a new reconfigurable complex multi-band delta sigma polar modulator (CMB-DSPM) architecture for multi-band transmission. In this brief, a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6^{\mathrm{ th}}$ </tex-math></inline-formula> order band-pass delta sigma modulator (DSM) is designed and implemented for reconfigurable triple-band transmission. The proposed DSM architecture utilizes the advantage of a complex DSM structure to reduce the required processing block and polar quantizer to reduce the quantization noise. The proposed CMB-DSPM architecture improves the in-band and out-of-band performance in terms of signal-to-noise distortion ratio (SNDR) and coding efficiency (CE), respectively. The proposed scheme is validated in MATLAB/SIMULINK-based digital signal processing platform using three 5 MHz long-term evolution (LTE) signals. The results show up to 12.4 dB improvement in SNDR and 12.3% improvement in CE compared to the standard cartesian DSM architecture. The measured EVM is below 3%, which shows the good in-band performance of the proposed scheme.

New 2 2 Sigma Delta Modulators for Different Applications

This work presents the design of a new 2-2 programmable sigma delta modulator architecture, for different applications, this transformation design of the ΣΔ modulator low-pass, band-pass and high-pass or vice versa with loopbacks addition, which improved the linearity of the converter and reduced the quantization noise. In this work, the MASH structure enables the implementation of stable and high-order modulator. This makes low voltage and low power applications ideal. The simulation result for sigma delta modulator for biomedical applications exhibit a signal to noise ratio is 95 dB @ 250Hz bandwidth and a 75dB @ 200KHz ,85dB @1MHz for pass band modulator. The SNR is about 70dB for 5MHz bandwidth and for high pass application. This tool will allow a development contribution and characterize a system optimization set from the start while remaining at a high level of design that is suitable for electronic systems and models VHDL-AMS, RF, Biomedical.

Single-loop sigma delta modulator design and verification for cognitive IoT applications

PurposeA third-order discrete time sigma delta modulator (SDM) is proposed with optimum performance by addressing instability and power dissipations issues, and a novel SDM architecture is designed and verified in behavioural modelling in MATLAB/SIMULINK environment. Simulation results show that performance parameters of proposed modulator achieved SNR of 105.41 dB, SNDR of 101.96 dB and DR of 17 bits for the signal bandwidth of 20 kHz.Design/methodology/approachThis paper describes single-loop SDM design with optimum selection of integrator weights for physiological signal processing in IoT applications.FindingsThe proposed discrete time modulator designed with 1-bit quantizer and optimum oversampling ratio proved as power efficient. Integrator scaling coefficients are generated in LabVIEW environment for pure third-order noise shaping.Originality/valueThis paper contains the novelty in the work, and it is suitable for cognitive Internet of Things applications.

Based Second Order ∑Δ Modulator for Digital Hearing Aid Applications

Abstract This paper describes the design and simulation of a sigma delta modulator (∑ΔM) architecture that can be used in digital hearing aid applications. A model of a non-ideal second order feed-forward ∑Δ Modulator, adopted for this purpose, is also presented. The loop coefficients of this architecture are optimized using Genetic Algorithm. The architecture together with optimized coefficients achieves 99 dB SNDR and a dynamic range of 101 dB. A sampling frequency (fs) of 1.28 MHz and a second order modulator makes this architecture less complex and power efficient.

입력 범위를 개선한 FDPA 방식의 3차 시그마-델타 변조기

본 논문은 개선된 입력 범위를 갖는 FDPA(Feedback Delay Pass Addition) 방식의 3차 SDM(Sigma-Delta Modulator) 구조를 제안한다. 기존의 구조는 2차 SDM 구조에서 디지털 딜레이 패스만을 추가하여 3차 전달함수를 구현하였지만, 첫 번째 적분기로 피드백 하는 패스가 많아짐에 따라 입력 범위가 매우 작은 단점이 있다. 그러나 제안된 구조는 첫 번째 적분기로 피드백 하는 디지털 패스를 2차 적분기로 피드백 하여 입력 범위를 9dB 개선할 수 있었다 이를 이중 샘플링 기법을 통해 연산 증폭기 한 개 만으로 3차 SC SDM을 구현하였다. 공급전압 1.8V, 신호대역폭 20KHz, 오디오 대역 샘플링 주파수 2.8224MHz 조건에서 <TEX>$0.18{\mu}m$</TEX> CMOS 공정을 이용하여 제안한 SDM을 시뮬레이션한 결과, SNR(Signal to Noise Ratio)은 83.8dB, 전력소비는 <TEX>$700{\mu}W$</TEX>, Dynamic Range는 82.8dB이다. In this paper, <TEX>$3^{rd}$</TEX> SDM with FDPA(Feedback Delay Pass Addition) technique to improve the input range is proposed. Conventional architecture with <TEX>$3^{rd}$</TEX> transfer function is just made as adding a digital delay path in <TEX>$2^{nd}$</TEX> SDM architecture. But the input range is very small because feedback path into the first integrator is increased. But, proposed architecture change feedback path into the first integrator to the second integrator, so input range could be improved about 9dB. The <TEX>$3^{rd}$</TEX> SC SDM with only one operational amplifier was implemented using double-sampling technique. Simulation results for the proposed SDM designed in <TEX>$0.18{\mu}m$</TEX> CMOS technology with power supply voltage 1.8V, signal bandwidth 20KHz and audible sampling frequency 2.8224MHz show SNR(Signal to Noise Ratio) of 83.8dB, the power consumption of <TEX>$700{\mu}W$</TEX> and Dynamic Range of 82.8dB.

Single-Bit Pseudoparallel Processing Low-Oversampling Delta–Sigma Modulator Suitable for SDR Wireless Transmitters

The oversampling requirement in a delta-sigma modulator (DSM) is considered one of the limiting factors toward its employment in current high-frequency applications, such as wireless software defined radio (SDR) systems. This paper advances that the critical requirement for DSMs is high-frequency processing and not a high-oversampling ratio. A single-bit semiparallel processing structure to accomplish the high-frequency processing is proposed in this paper. Using the suggested low-oversampling digital DSM architecture, high-speed, high-complexity computations, which are normally required for wireless applications, are executed simultaneously. This facilitates the design of embedded SDR multistandard transmitters using commercially available digital processors. The most favorable application of the proposed single-bit DSM is to build an radio frequency transmitter that includes a one-bit quantifier with two-level switching power amplifier for both high linearity and high efficiency. Performance analysis is carried out by using MATLAB simulations, which shows a reduction of the oversampling ratio by a factor of 16 (for a baseline oversampling ratio of 256) with the same signal-to-noise ratio (SNR). The proposed DSM is also implemented on a field-programmable gate array (FPGA) board and its performance is validated by using a code division multiple access signal. The bandwidth of the output signal is increased four times without increasing the processing frequency. Simultaneously, quality of the output signal remains the same but FPGA resource usage is increased by a factor of three.

A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

A dynamic comparator-based OTA is introduced as a replacement for a conventional OTA. It performs charge transfer in a switched-capacitor circuit by repeatedly evaluating the polarity of the differential input using a dynamic clocked comparator and injecting current pulses at the output to move the input voltage toward zero. The amplitude of the current pulse is reduced each time the input voltage crosses zero to provide fast but accurate settling of the output voltage. Dynamic comparator-based OTAs are applied to the design of a 1-1-1-1 MASH delta-sigma modulator. The 65-nm CMOS prototype achieves a 70.4 dB peak SNDR over a 2.5-MHz bandwidth while consuming 3.73 mW from a 1.2-V supply. The 276-fJ/conv-step FoM represents a four times improvement over previously-reported delta-sigma modulators using zero-crossing-based circuits or comparator-based switched capacitors. Because of the dynamic operation of the OTAs and discrete-time delta-sigma modulator architecture, both bandwidth and power consumption linearly scale with the sampling frequency without any reconfiguration of the modulator.

Multi-stage noise band cancellation ΣΔ modulator for digitisation of distorted signals

A new sigma-delta modulator (ΣΔM) architecture is proposed to digitise wideband distorted signals. It combines frequency band decomposition with bandpass (BP) ΣΔ converters and cascaded architectures. The novelties are the use of the residual signal transfer function at the output of the first summing node in a classical BP ΣΔ that is an almost free signal shaping in the ΣΔM and the digitisation of the shaped noise in order to cancel it out in a particular band.

Continuous time sigma-delta modulator based on binary weighted charge balance

A novel multibit continuous time sigma-delta modulator architecture that does not require a flash converter is presented. The quantiser of this modulator is similar to an integrating ADC that is operated with a binary weighted charge balancing algorithm. The charge residue in the integrating ADC at the end of each conversion cycle is accumulated for the next conversion, providing first-order noise shaping. The modulator order can be increased by the addition of more integrating stages.

A 1.2-MHz 10-bit Continuous-Time Sigma–Delta ADC Using a Time Encoding Quantizer

This paper shows the operating principle and experimental results of a new continuous-time sigma-delta modulator architecture. The proposed modulator does not require a multibit quantizer nor a mismatch-shaping digital-to-analog converter to produce a multibit noise-shaped output. Instead, its quantizer encodes the loop filter output in a binary signal using a time encoding technique similar to pulsewidth modulation. This binary signal is used to generate both the analog feedback loop signal and the digital output. A proof-of-concept chip in 0.35-mum CMOS achieves 10 bits of resolution within a signal bandwidth of 1.2 MHz using a first-order modulator.

Multi-bit Sigma-Delta Modulator for Low Distortion and High-Speed Operation

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to- digital converter and the scrambler logic. Implemented by a 0.13 µm CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

Putting the "FLEX" in flexible mobile wireless radios - A wideband continuous-time baudpass sigma-delta ADC software radios

This article has provided a brief overview of the SigmaDelta ADC conversion technologies for SDRs. The wireless receiver challenges were identified, the ADC design considerations and SigmaDelta solutions were discussed, and a low-distortion CT BP SigmaDelta modulator architecture was presented. The article has shown that the proposed CT BP SigmaDelta modulator is suitable for implementing high-IF ADC, making possible the software radio in handhelds. The major challenges in implementing such a high-IF ADC are the power dissipation and the degree of configurability, programmability, and adaptability that can be achieved by applying digital tuning and adaptive calibration

A Triple-Mode Sigma-Delta Modulator for Multi-Standard Wireless Radio Receivers

A 1.8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted-Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2 MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN.

Dynamic Range Improvement of Multistage Multibit Modulator for Low Oversampling Ratios

This paper presents an improved architecture of the multistage multibit sigma-delta modulators (ΣΔMs) for wide-band applications. Our approach is based on two resonator topologies, high-Q cascade-of-resonator-with-feedforward (HQCRFF) and low-Q cascade-of-integrator-with-feedforward (LQCIFF). Because of in-band zeros introduced by internal loop filters, the proposed architecture enhances the suppression of the in-band quantization noise at a low OSR. The HQCRFF-based modulator with single-bit quantizer has two modes of operation, modulation and oscillation. When the HQCRFF-based modulator is operating in oscillation mode, the feedback path from the quantizer output to the input summing node is disabled and hence the modulator output is free of the quantization noise terms. Although operating in oscillation mode is not allowed for single-stage ΣΔM, the oscillation of HQCRFF-based modulator can improve dynamic range (DR) of the multistage (MASH) ΣΔM. The key to improving DR is to use HQCRFF-based modulator in the first stage and have the first stage oscillated. When the first stage oscillates, the coarse quantization noise vanishes and hence circuit nonidealities, such as finite op-amp gain and capacitor mismatching, do not cause leakage quantization noise problem. According to theoretical and numerical analysis, the proposed MASH architecture can inherently have wide DR without using additional calibration techniques.

Continuous-time sigma-delta modulators with reduced timing jitter sensitivity based on time delays

A novel continuous time sigma-delta modulator architecture is presented. This architecture employs a noise shaping filter based on time delays, which allows a high speed hardware implementation with transmission lines. This architecture is less sensitive to clock jitter and excess loop delay than the equivalent continuous time modulators based on integrators.

Third-order cascaded sigma-delta modulators

A sigma-delta modulator architecture wherein third-order noise shaping is achieved with relatively modest constraints on device matching is explored. The architecture is based on a cascade of a second-order modulator stage followed by a first-order stage, both using 1-b quantization. To improve the dynamic range, the input to the second stage is generated as an asymmetrically weighted error signal from the first stage. An analytical model for assessing the performance and device matching requirements of cascaded architectures is introduced, and computer simulations are used to verify the approximations made in this model. The analytical model is used to show that the proposed architecture offers performance comparable to other third-order cascaded sigma-delta modulator topologies, while being less sensitive to device matching errors. >