Digital Receiver Architecture Research Articles

A LUT-based scheme for LNA linearization in direct RF sampling receivers

Direct RF sampling receiver – a fully digital receiver architecture – undoubtedly becomes a favored choice for HF/VHF as this approach inherently bypasses the legacy nonlinearities caused by analog components. In DRF-RF and wideband multichannel in general, LNA is still an indispensable component to ensure the receiver’s sensitivity. However, with the presence of multiple channels, the total RF power often surpasses the linear threshold that LNA and the amplified signal become severely distorted. This paper proposed a method for mitigating the LNA distortion using the look-up table (LUT) approach. Specifically, our receiver is designed with two modes of operation. In training mode, a built-in signal circuit generates a training signal for extracting the LNA characteristic and eventually reconstructs the inverse LNA nonlinear model in the form of a LUT memory. During the receiving mode, a linearization circuit reverses the distortion impact by matching the RF power level with the inverse nonlinear model pre-stored in the LUT. The effectiveness of the proposed distortion compensation method first is evaluated by a MATLAB simulation with a multi-channel DRF-RF model. The simulation results show that the proposed approach significantly improved the SNDR for the channel of interest. Furthermore, the model has been practically verified, where the actual distorted signals are sampled from a commercial LNA (ZFL-500LN+) by a customized FPGA board. Results from measurements show an improvement of ∼7 dB for SNDR and 27% for EVM in a strong distortion scenario of QPSK modulation signal.

Scalable Digital Receiver for Multi-Element Radio Telescopes

Modern and upcoming radio telescopes at low frequencies are often characterized by hundreds or thousands of antenna elements operating at wide bandwidths up to about 0.5[Formula: see text]GHz. A spectral correlator for such an array is required to estimate the cross-power spectrum of the response of each element with that of every other element with a high spectral resolution. The resulting all-to-all connectivity between signals from the entire array poses a serious bottleneck. In this paper, we propose a simple digital receiver architecture that interfaces the digitized time series from a large number of antenna elements to a High-Performance Computing (HPC) cluster through a communication switch to overcome the data ingest bottleneck. Each HPC node can then perform wideband processing in steps of finite but significant time-slices for the entire array. We explain in detail the implementation of our architecture for the proposed expansion of the Ooty Wide Field Array (OWFA) into a 1056 element array. Since the proposed digital receiver is based on Field Programmable Gate Array (FPGA), it can be reconfigured for different applications. This is illustrated by considering the case of Phased Array Feeds (PAF) for the proposed expanded Giant Metrewave Radio Telescope (eGMRT).

RF Chain Reduction for MIMO Systems: A Hardware Prototype

Radio frequency (RF) chain circuits play a major role in digital receiver architectures, allowing passband communication signals to be processed in baseband. When operating at high frequencies, these circuits tend to be costly. This increased cost imposes a major limitation on future multiple-input multiple-output (MIMO) communication technologies. A common approach to mitigate the increased cost is to utilize hybrid architectures, in which the received signal is combined in analog into a lower dimension, thus reducing the number of RF chains. In this work we study the design and hardware implementation of hybrid architectures via minimizing channel estimation error. We first derive the optimal solution for complex-gain combiners and propose an alternating optimization algorithm for phase-shifter combiners. We then present a hardware prototype implementing analog combining for RF chain reduction. The prototype consists of a specially designed configurable combining board as well as a dedicated experimental setup. Our hardware prototype allows evaluating the effect of analog combining in MIMO systems using actual communication signals. The experimental study, which focuses on channel estimation accuracy in MIMO channels, demonstrates that using the proposed prototype, the achievable channel estimation performance is within a small gap in a statistical sense from that obtained using a costly receiver in which each antenna is connected to a dedicated RF chain.

Bandpass sampling in heterodyne receivers for coherent optical access networks

A novel digital receiver architecture for coherent heterodyne-detected optical signals is presented. It demonstrates the application of bandpass sampling in an optical communications context, to overcome the high sampling rate requirement of conventional receivers (more than twice the signal bandwidth). The concept is targeted for WDM coherent optical access networks, where applying heterodyne detection constitutes a promising approach to reducing optical hardware complexity. The validity of the concept is experimentally assessed in a 76 km WDM-PON scenario, where the developed DSP achieves a 50% ADC rate reduction with penalty-free operation.

Synchronization and cell search algorithms in 3GPP long term evolution systems (FDD mode)

In this paper initial downlink synchronization (sync) and cell identification algorithms for the 3rd generation partnership project (3GPP) long term evolution (LTE) systems are presented. The frequency division duplex (FDD) mode is used in the downlink radio frame structure. A user equipment digital receiver architecture is proposed. The orthogonality of signals in orthogonal frequency division multiplexing (OFDM) may be lost due to some impairments such as frequency, time, and phase offsets. Therefore, major parts of this research are involved in restoring the orthogonality at the user equipment (UE) by using some techniques to estimate the sync parameters, and to detect cell identity among candidate cells based on sync signals. A Farrow structure interpolator is used to compensate the fractional timing offset. Both inter site synchronous and inter site asynchronous networks are presented. Computer simulations are used to demonstrate the performance of the proposed schemes with multipath Rayleigh fading channel, frequency offsets, timing offsets, and additive white Gaussian noise (AWGN). Results show high probability of cell identification in a very short time 20 ms in both multi cell model scenarios, especially when multiple input multiple output (MIMO) technique, oversampling at the UE, and high order Farrow structure interpolator are used.

Design and Implementation of Software-Defined Radio Receiver Based on Blind Nonlinear System Identification and Compensation

As the commonly used wideband software radio receiver does not possess the performance of a high linear dynamic range under multiple signal excitation, a new type of adaptive wideband digital receiver architecture is proposed and designed based on blind nonlinear system identification. The traditional narrowband linear receiving and channelizing technologies should not be applied to deal with the complicated multiple-signal excitation with unknown or time-varying characteristics of time domain or frequency domain. Here, the harmonic and the intermodulation components brought about by the wideband digital receiver are firstly identified and extracted in the frequency domain, then a blind identification criterion for minimizing the short-time energy of the nonlinear components is designed, and the steepest descent method (SDM) or the recursive least square (RLS) algorithm is applied to extract and update iteratively the parameters of the nonlinear behavior model of the wideband digital receiver. Finally, the updated model is utilized to compensate the nonlinear distortion of the receiver in real time. The experimental results show that the spur-free dynamic range (SFDR) of the blind identification digital receiver achieves about 20-dB higher than that of the traditional receiver under multitone or 16-QAM bandpass signal excitation. As regards the large bandwidth and the high power efficiency of the RF front end and ADC circuits, the blind identification receiver architecture is helpful for detecting weak signal in concomitance with in-band or out-of-band strong jammers.

Architecture of wideband digital receiver based on two-level channelization

Architecture of wideband digital receiver based on two-level channelization

A Digital Receiver Architecture for Bluetooth in 0.25-<formula formulatype="inline"> <tex>$\mu$</tex></formula>m CMOS Technology and Beyond

A digital receiver architecture for short-range communications systems like Bluetooth is presented. The architecture is tailored to a highly integrated Bluetooth single-chip integrated circuit (IC) and can easily be adapted to other communications systems using a Gaussian frequency-shift keying (GFSK ) modulation scheme. The single-chip IC integrates the complete digital baseband and radio frequency (RF) functionality on a single die and is realized in a 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology targeted for cost efficiency. The superior performance of this digital receiver architecture compared to the state-of-the-art short-range communications receivers is shown. Simulation and measurement results are presented showing a receiver sensitivity of 87 dBm and excellent co-channel and adjacent channel interference performance.

Digital satellite receiver for wideband multi-rate Ka-band communications

This correspondence presents the architecture of a high-speed low-complexity digital receiver for wideband satellite communications supporting multiple baud rates, ranging from 10 to 200 MBaud. The design of the modem is based on the cascaded integrator-comb (CIC) scheme which exploits a parallel processing so as to provide an outstanding decimation agility. Eventually, bit error rate (BER) performance of the multi-rate receiver are assessed by floating-point simulations.

Frequency-domain implementation of the transmitted-reference ultra-wideband receiver

This paper presents a mixed-signal frequency-domain implementation of the autocorrelation receiver used in the detection of ultra-wideband communication signals that are modulated with transmitted-reference signaling. The digital receiver architecture is based on samples provided by an analog-to-digital converter (ADC) in the frequency domain. Among the advantages of the new receiver are the relaxation of the conversion speed achieved by the inherent parallel architecture of the frequency-domain ADC and the flexibility and simplicity of an all-digital receiver architecture that follows the mixed-signal ADC radio front-end. The paper provides the symbol detection formulas and the corresponding system implementation and makes comparisons with the conventional time-domain implementations. Additionally, a time synchronization technique for the new receiver structure is proposed, which makes the receiver insensitive to any time offset at the pulse level. Furthermore, as a particular case of great practical interest, we consider a single bit for the ADC implementation, and we show with experimental results that the resultant frequency-domain mono-bit digital receiver provides a performance gain that increases with the number of frequency samples, when compared with its time-domain counterpart.

Ultra wideband direction finding using digital channelization receiver architecture

In this paper, UWB direction finding technique using digital channelization receiver architecture Is proposed. The basic idea of this technique is to split the UWB array output into multiple frequency channels and then down-convert each channel into much lower frequency, hence allowing the low sampling rate ADC to be used. Estimation of the DoA of UWB source is achieved by forming a direction finding function using the spectral information from channelizer's output. A thorough performance analysis from simulation results is presented to verify the proposed technique and to investigate the effect of the system's parameters on the performance

Low cost architecture of direct conversion digital receiver

The paper presents a low-cost architecture for a direct conversion digital receiver that uses six-port technology. An experimental prototype has been constructed and tested. Analogue carrier recovery and decision circuits are investigated as a means to provide future system integration and high data rate capacity. The designed receiver is operated at an ISM frequency of 2.45 GHz and uses a QPSK modulation format. Results on data rate limitations are given for QPSK signals up to 52 Mb/s. Test results related to adjacent channel, co-channel and CW interferences are presented for a data rate of 40 Mb/s. Phase offset between carrier and reference signals, along with carrier frequency deviation performances, are also presented for a rate of 40 Mb/s. A frequency hopping spread spectrum technique is discussed on the basis of the proposed architecture.

Flexible Digital Receiver Architecture with Optimized Components

Future wireless communication systems require increased flexibility, lower power consumption, smaller size and decreasing costs for the terminals and therewith for the components. By replacing analogue by digital signal processing the degree of integration and the flexibility of a terminal with respect to multi-mode capability can be improved.In a highly integrated implementation the most critical components are the A/D-converter and the digital filter stages due to high speed and low power requirements. In this contribution a novel concept for a flexible, digital receiver with highly optimized components will be presented. The concept is based on down-conversion of the broadband receive signal to a low intermediate frequency. The main modules of the receiver are a properly designed ΔΣ-modulator for A/D-conversion, and novel digital filtering stages. It will be demonstrated, that the use of cascaded low-order wave digital lattice filters results in a number of advantages and makes a very efficient realization in VLSI-technology feasible.

An all digital receiver architecture for bandwidth efficient transmission at high data rates

Using the maximum-likelihood approach, algorithms for detection and synchronization are derived that are well suited for VLSI implementation. Special emphasis is placed on an all-digital implementation where carrier and clock synchronization do not require a feedback of signals to the analog part, which simplifies the analog front-end design (mixing oscillator and A/D converter sampling clock run at fixed frequency). An important advantage of the proposed algorithms is that a high clock rate is not required; only two-four times the symbol rate is needed, depending on amplitude quantization. Implementation aspects, e.g. architecture, and quantization, are considered. A prototype is described which was implemented to prove the feasibility of the concept and to evaluate the performance under practical conditions.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>