Architectural Modeling Methodologies Research Articles

Urban Air Mobility Situation Awareness From Enterprise Architecture Perspectives

Urban Air Mobility operation is currently under discussion by the industry, authorities, and society, dealing with new concepts, new technologies, and complex challenges. For UAM safety, it is fundamental to strive for high levels of correct decision-making among agents and services. In safety-critical systems like UAM transportation, it is crucial to secure Situation Awareness (SA). Systems engineers, architects, and organizations must plan for SA acquisition and maintenance from early concept studies to ensure the relevant information is shared, allowing good decision-making. The article proposes a new approach to represent Situation Awareness in the UAM ecosystem using Enterprise Architecture (EA) modeling through the Unified Architecture Framework (UAF). To understand the interactions and behaviors committed to SA, decision-making, and safe performance, SA is explored using a process driven by a comprehensive picture of an entire enterprise from the perspectives of designers, providers, and operators. The UAF modeling language and domain metamodel were used as the Enterprise Architecture modeling methodology. The model proposed in this work presents a novel and comprehensive representation of SA in the UAM ecosystem. The different views from the model are explored to discuss how the SA can improve the safe accomplishment of UAM missions. The results include views combining people, data, operators, and operational processes showing how an enterprise support Situation Awareness as a competence.

SAMM: an architecture modeling methodology for ship command and control systems

Ship command and control systems (SCCSs) are composed of large-scale, complex, real-time and software-intensive systems that complete tasks collaboratively. Open architecture has been introduced to design the architecture of SCCSs and has been refined into functional architecture (FA) and technical architecture (TA) to meet architectural requirements such as adapting fast-speed functional and technical changes. Thereby, specifying the architecture of SCCSs, based on FA and TA, becomes a key issue for stakeholders of the domain. In this paper, we propose an architecture modeling methodology (named as SAMM) for describing the architecture of SCCSs. SAMM is derived by following a systematic and generic framework--modeling Goal, domain-specific Conceptual model, architecture Viewpoint, and architecture description Language (GCVL), which guides domain experts to devise domain-specific architecture modeling methodologies of large-scale software-intensive systems. SAMM contains three viewpoints and 22 models, and a UML/SysML-based architecture description language. An industrial application of SAMM, along with the subsequent application of the derived SAMM architecture model (i.e., a deployed SCCS prototype) was conducted to evaluate SAMM. A questionnaire-based survey was also conducted to subjectively evaluate whether SAMM meets the modeling goals and its applicability. Results show that SAMM meets all modeling goals and is easy to apply.

The Formal Design Models of Digraph Architectures and Behaviors

Graphs are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. Problems in sciences and engineering can be formulated and solved by the graph model. This paper develops a comprehensive design pattern of formal digraphs using the Doubly-Linked List (DLL) architecture. The most complicated form of graphs known as the weighted digraph is selected as a general graph model, based on it simple graphs such as nondirected and/or nonweighted ones can be easily derived and tailored. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of digraphs to be rigorously designed and implemented in a top-down approach. The architectural models of digraphs are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of digraphs is implemented using nodes of DLL dynamically created in the memory. The behavioral models of digraphs are specified and refined by a set of 18 Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node manipulation operations. This work has been applied in a number of real-time and nonreal-time system designs and specifications such as a Real-Time Operating System (RTOS+), graph-based and tree-based applications, and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Models of Tree Architectures and Behaviors

Trees are one of the most fundamental and widely used non-linear hierarchical structures of linked nodes. A binary tree (B-Tree) is a typical balanced tree where the fan-out of each node is at most two known as the left and right children. This paper develops a comprehensive design pattern of formal trees using the B-Tree architecture. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of B-Trees to be rigorously designed and implemented in a top-down approach. The architectural models of B-Trees are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of B-Trees is implemented using the left and right child nodes dynamically created in memory. The behavioral models of B-Trees are specified and refined by a set of Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node I/O operations. This work has been applied in a number of real-time and nonreal-time system designs such as a real-time operating system (RTOS+), a general system organization model, and the ADT library for an RTPA-based automatic code generator.

The Formal Design Models of a Universal Array (UA) and its Implementation

Arrays are one of the most fundamental and widely applied data structures, which are useful for modeling both logical designs and physical implementations of multi-dimensional data objects sharing the same type of homogeneous elements. However, there is a lack of a formal model of the universal array based on it any array instance can be derived. This paper studies the fundamental properties of Universal Array (UA) and presents a comprehensive design pattern. A denotational mathematics, Real-Time Process Algebra (RTPA), allows both architectural and behavioral models of UA to be rigorously designed and refined in a top-down approach. The conceptual model of UA is rigorously described by tuple- and matrix-based mathematical models. The architectural models of UA are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The physical model of UA is implemented using linear list that is indexed by an offset pointer of elements. The behavioral models of UA are specified and refined by a set of Unified Process Models (UPMs). As a case study, the formal UA models are implemented in Java. This work has been applied in a number of real-time and nonreal-time systems such as compilers, a file management system, the real-time operating system (RTOS+), and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Model of Doubly-Linked-Circular Lists (DLC-Lists)

Abstract Data Types (ADTs) are a set of highly generic and rigorously modeled data structures in type theory. Lists as a finite sequence of elements are one of the most fundamental and widely used ADTs in system modeling, which provide a standard encapsulation and access interface for manipulating large-volume information and persistent data. This paper develops a comprehensive design pattern of formal lists using a doubly-linked-circular (DLC) list architecture. A rigorous denotational mathematics, Real-Time Process Algebra (RTPA), is adopted, which allows both architectural and behavioral models of lists to be rigorously designed and implemented in a top-down approach. The architectural models of DLC-Lists are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The behavioral models of DLC-Lists are specified and refined by a set of Unified Process Models (UPMs) in three categories namely the management operations, traversal operations, and node I/O operations. This work has been applied in a number of real-time and nonreal-time system designs such as a real-time operating system (RTOS+), a file management system (FMS), and the ADT library for an RTPA-based automatic code generation tool.

The Formal Design Models of a Set of Abstract Data Types (ADTs)

Type theories are fundamental for underpinning data object modeling and system architectural design in computing and software engineering. Abstract Data Types (ADTs) are a set of highly generic and rigorously modeled data structures in type theory. ADTs also play a key role in Object-Oriented (OO) technologies for software system design and implementation. This paper presents a formal modeling methodology for ADTs using the Real-Time Process Algebra (RTPA), which allows both architectural and behavioral models of ADTs and complex data objects. Formal architectures, static behaviors, and dynamic behaviors of a set of ADTs are comparatively studied. The architectural models of the ADTs are created using RTPA architectural modeling methodologies known as the Unified Data Models (UDMs). The static behaviors of the ADTs are specified and refined by a set of Unified Process Models (UPMs) of RTPA. The dynamic behaviors of the ADTs are modeled by process dispatching technologies of RTPA. This work has been applied in a number of real-time and non-real-time system designs such as a Real-Time Operating System (RTOS+), a Cognitive Learning Engine (CLE), and the automatic code generator based on RTPA.

The Formal Design Model of a Real-Time Operating System (RTOS+)

A real-time operating system (RTOS) provides a platform for the design and implementation of a wide range of applications in real-time systems, embedded systems, and mission-critical systems. This paper presents a formal design model for a general RTOS known as RTOS+ that enables a specific target RTOS to be rigorously and efficiently derived in real-world applications. The methodology of a denotational mathematics, Real-Time Process Algebra (RTPA), is described for formally modeling and refining architectures, static behaviors, and dynamic behaviors of RTOS+. The conceptual model of the RTOS+ system is introduced as the initial requirements for the system. The architectural model of RTOS+ is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of RTOS+ are specified and refined by a set of Unified Process Models (UPMs). The dynamic behaviors of the RTOS+ system are specified and refined by the real-time process scheduler and system dispatcher. This work is presented in two papers in serial due to its excessive length. The static and dynamic behavioral models of RTOS+ is described in this paper; while the conceptual and architectural models of RTOS+ has been published in IJSSCI 2(2).

The Formal Design Model of a Real-Time Operating System (RTOS+)

A real-time operating system (RTOS) provides a platform for the design and implementation of a wide range of applications in real-time systems, embedded systems, and mission-critical systems. This paper presents a formal design model for a general RTOS known as RTOS+ that enables a specific target RTOS to be rigorously and efficiently derived in real-world applications. The methodology of a denotational mathematics, Real-Time Process Algebra (RTPA), is described for formally modeling and refining architectures, static behaviors, and dynamic behaviors of RTOS+. The conceptual model of the RTOS+ system is introduced as the initial requirements for the system. The architectural model of RTOS+ is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of RTOS+ are specified and refined by a set of Unified Process Models (UPMs). The dynamic behaviors of the RTOS+ system are specified and refined by the real-time process scheduler and system dispatcher. This work is presented in two papers; the conceptual and architectural models of RTOS+ is described in this paper, while the static and dynamic behavioral models of RTOS+ will be elaborated in a forthcoming paper.

The Formal Design Model of an Automatic Teller Machine (ATM)

An Automated Teller Machine (ATM) is a safety-critical and real-time system that is highly complicated in design and implementation. This article presents the formal design, specification, and modeling of the ATM system using a denotational mathematics known as Real-Time Process Algebra (RTPA). The conceptual model of the ATM system is introduced as the initial requirements for the system. The architectural model of the ATM system is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs), which share a generic mathematical model of tuples. The static behaviors of the ATM system are specified and refined by a set of Unified Process Models (UPMs) for the ATM transition processing and system supporting processes. The dynamic behaviors of the ATM system are specified and refined by process priority allocation, process deployment, and process dispatch models. Based on the formal design models of the ATM system, code can be automatically generated using the RTPA Code Generator (RTPA-CG), or be seamlessly transformed into programs by programmers. The formal models of ATM may not only serve as a formal design paradigm of real-time software systems, but also a test bench for the expressive power and modeling capability of exiting formal methods in software engineering.

The Formal Design Model of a Lift Dispatching System (LDS)

A Lift Dispatching System (LDS) is a typical real-time system that is highly complicated in design and implementation. This article presents the formal design, specification, and modeling of the LDS system using a denotational mathematics known as Real-Time Process Algebra (RTPA). The conceptual model of the LDS system is introduced as the initial requirements for the system. The architectural model of the LDS system is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of the LDS system are specified and refined by a set of Unified Process Models (UPMs) for the lift dispatching and serving processes. The dynamic behaviors of the LDS system are specified and refined by process priority allocation and process deployment models. Based on the formal design models of the LDS system, code can be automatically generated using the RTPA Code Generator (RTPA-CG), or be seamlessly transferred into programs by programmers. The formal models of LDS may not only serve as a formal design paradigm of real-time software systems, but also a test bench of the expressive power and modeling capability of exiting formal methods in software engineering.

Extracting Assembly Mating Graphs for Assembly Variant Design

Assembly variant design in agile manufacturing involves modifying components or mixing and matching existing components from valid assemblies to proliferate new variant products. Wanget al. (2001, “Assembly Modeling for Complex Assembly Variant Design,” Tenth Industrial Engineering Research Conference, Dallas TX; 2005, “Complex Assembly Variant Design in Agile Manufacturing. Part I: System Architecture and Assembly Modeling Methodology,” IIE Transactions on Design and Manufacturing, 37(1), pp. 1–15; 2005, “Complex Assembly Variant Design in Agile Manufacturing. Part II: Assembly Variant Design Methodology,” IIE Transactions on Design and Manufacturing, 37(1), pp. 17–33) developed an assembly variant design methodology based on a component relationship model that captures assembly mating relationships at the feature level referred as assembly mating graph. This paper is devoted to formulation of assembly mating graphs from legacy computer-aided design models. Mating relationships are classified as direct, indirect, and interference relationships. Direct mating relationships are identified using geometric methods while a ray-firing algorithm is used to identify indirect and interference type mating relationships. The effectiveness of the developed methodology is demonstrated using illustrative examples.

The Formal Design Model of a Telephone Switching System (TSS)

A typical real-time system, the Telephone Switching System (TSS), is a highly complicated system in design and implementation. This paper presents the formal design, specification, and modeling of the TSS system using a denotational mathematics known as Real-Time Process Algebra (RTPA). The conceptual model of the TSS system is introduced as the initial requirements for the system. Then, the architectural model of the TSS system is created using the RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of the TSS system are specified and refined by a set of Unified Process Models (UPMs) such as call processing and support processes. The dynamic behaviors of the TSS system are specified and refined by process priority allocation, process deployment, and process dispatching models. Based on the formal design models of the TSS system, code can be automatically generated using the RTPA Code Generator (RTPA-CG), or be seamlessly transformed into programs by programmers. The formal model of TSS may not only serve as a formal design paradigm of real-time software systems, but also a test bench of the expressive power and modeling capability of exiting formal methods in software engineering.

Complex assembly variant design in agile manufacturing. Part I: System architecture and assembly modeling methodology

In the distributed and horizontally integrated manufacturing environment found in agile manufacturing, there is a great demand for new product development methods that are capable of generating new customized assembly designs based on mature component designs that might be dispersed at geographically distributed partner sites. To cater for this demand, this paper addresses the methodology for complex assembly variant design in agile manufacturing. It consists in fundamental research in two parts: (i) assembly modeling; and (ii) assembly variant design methodology. This paper, the first of a two-part series, presents the assembly variant design system architecture and the assembly modeling methodology. First, a complementary assembly modeling concept is proposed with two kinds of assembly models, the hierarchical assembly model and the relational assembly model. The first explicitly captures the hierarchical and functional relationships between constituent components whereas the second explicitly captures the mating relationships at the form-feature-level. These models are complementary in the sense that each of them models only a specific aspect of assembly-related information but together they include the required assembly-related information. They are further specialized to accommodate the features of assembly variant design. As a result, two kinds of assembly models, the assembly variants model and the assembly mating graph are generated. These assembly models serve as the basis for assembly variant design which is discussed in the companion paper.