Verification Architecture Research Articles

A Machine Learning-Based Algorithm for the Prediction of Eigenfrequencies of Railway Bridges

As part of the development of advanced, data-driven methods for predictive maintenance of railway infrastructure, this paper analyzes and evaluates more realistic predictions of eigenfrequencies of railway bridges, also referred to as natural frequencies, based on a population of already assessed, measured existing bridges using regression techniques. For this purpose, Machine Learning (ML) techniques such as Polynomial Regression (PR), ANN and XGBoost are consistently evaluated and the application of the XGBoost algorithm is identified as the most suitable prediction model for these eigenfrequencies, usable for dynamic train-bridge interactions. The results of the post-processing are incorporated into the safety architecture for bridge verification (risk management). The presented data-based techniques are a steppingstone towards digitalization of structural health monitoring and offer safety and longevity of the railway bridges. Furthermore, the use of these methods can save costs that would be incurred by physical in-situ measurements. The types of bridges analyzed with ML are Filler Beam Bridges (FBE), which outnumber other construction types of bridges in Germany (DB InfraGO AG). This methodology is applicable to any bridge type as long as sufficient data are gathered for training, validation and testing.

Towards efficient and robust face recognition through attention-integrated multi-level CNN

AbstractThe rapid advancement of deep Convolutional Neural Networks (CNNs) has led to remarkable progress in computer vision, contributing to the development of numerous face verification architectures. However, the inherent complexity of these architectures, often characterized by millions of parameters and substantial computational demands, presents significant challenges for deployment on resource-constrained devices. To address these challenges, we introduce RobFaceNet, a robust and efficient CNN designed explicitly for face recognition (FR). The proposed RobFaceNet optimizes accuracy while preserving computational efficiency, a balance achieved by incorporating multiple features and attention mechanisms. These features include both low-level and high-level attributes extracted from input face images and aggregated from multiple levels. Additionally, the model incorporates a newly developed bottleneck that integrates both channel and spatial attention mechanisms. The combination of multiple features and attention mechanisms enables the network to capture more significant facial features from the images, thereby enhancing its robustness and the quality of facial feature extraction. Experimental results across state-of-the-art FR datasets demonstrate that our RobFaceNet achieves higher recognition performance. For instance, RobFaceNet achieves 95.95% and 92.23% on the CA-LFW and CP-LFW datasets, respectively, compared to 95.45% and 92.08% for very deep ArcFace model. Meanwhile, RobFaceNet exhibits a more lightweight model complexity. In terms of computation cost, RobFaceNet has 337M Floating Point Operations Per Second (FLOPs) compared to ArcFace’s 24211M, with only 3% of the parameters. Consequently, RobFaceNet is well-suited for deployment across various platforms, including robots, embedded systems, and mobile devices.

Lung Cancer Prediction and Classification Using Decision Tree and VGG16 Convolutional Neural Networks

Introduction A malignant abnormal growth that starts in the tissues of the lungs is called Lung Cancer. It ranks among the most common and lethal cancers globally. Lung Cancer is particularly dangerous because of its aggressive nature and how quickly it can extend to other areas of the body. We propose a two-step verification architecture to check the presence of Lung Cancer. The model proposed by this paper first assesses the patient based on a few questions about the patient's symptoms and medical background. Then, the algorithm determines whether the patient has a low, medium, or high risk of developing lung cancer by diagnosing the response using the “Decision Tree” classification at an accuracy of 99.67%. If the patient has a medium or high risk, we further validate the finding by examining the patient's CT scan image using the “VGG16” CNN model at an accuracy of 92.53%. Background One of the key areas of research on Lung Cancer prediction is to identify patients based on symptoms and medical history. Its subjective nature makes it challenging to apply in real-world scenarios. Another research area in this field involves forecasting the presence of cancer cells using CT scan imagery, providing high accuracy. However, it requires physician intervention and is not appropriate for early-stage prediction. Objective This research aims to forecast the severity of Lung Cancer by analyzing the patient with a few questions regarding the symptoms and past medical conditions. If the patient has a medium or a high risk, we further examine their CT scan, validate the result and also predict the type of Lung Cancer. Methodology This paper uses the “Decision Tree” algorithm and the Customised “VGG16” model of CNN for the implementation. The “Decision Tree” algorithm is used to analyze the answers given by the patient to distinguish the severity of Lung Cancer. We further use Convolution Neural Networks with a Customised “VGG16” model to examine the patient's CT scan image, validate the result and categorize the type of Lung Cancer. Results The “Decision Tree” approach for forecasting the severity of lung cancer yields an accuracy of 99.67%. The accuracy of the customized “VGG16” CNN model to indicate the type of Lung Cancer suffered by the patient is 92.53% Conclusion This research indicates that our technique provides greater accuracy than the prior approaches for this problem and has extensive use in the prognosis of Lung Cancer.

An Attention-Based Multimodal Siamese Architecture for Tweet-User Verification

With the advent of internet technologies, it has created different ways of writing anonymously, which has lead to criminal and malicious activities over social media platforms. Thus, the automatic authentication checking of the available contents is the need of the hour. Social media sites, such as Facebook, Twitter, and so on, are used heavily by the users for sharing of information about their day-to-day activities. The identity of the suspect user is matched against tweets written by the specific user in tweet-user verification process. Writing styles of different users differ from each other, due to unique word choices, emoji selection, sentence formation, and punctuation usage. We have developed a multimodal Siamese-based architecture, which uses attention between the text and emoji parts of the tweet for generating a combined representation for the tweet. Attention helps in selecting the relevant information from different modalities. Modality attention is used for fusing the two modalities (text and emoji). We have used a newly developed multimodal Twitter dataset for evaluating the performance of the proposed model. We achieved an average accuracy, precision, recall, and <inline-formula> <tex-math notation="LaTeX">$F$</tex-math> </inline-formula>-measure values of 68.50%, 78.52%, 69.47%, and 67.05%, respectively. The results show an increase of 2.14% in <inline-formula> <tex-math notation="LaTeX">$F$</tex-math> </inline-formula>-measure in comparison with the current state-of-the-art (SOTA) models for this dataset.

DS-GAU: Dual-sequences gated attention unit architecture for text-independent speaker verification

Text-independent speaker verification provides people identified from their voice characteristics. In this paper, we propose a new method, Dual-Sequences Gate Attention Unit to improve the accuracy of a massive speaker verification system. Dual-Sequences Gate Attention Unit is based on the Gated Dual Attention Unit and the Gated Recurrent Unit. Two different inputs from the same source are the state pooling layer in the x-vector and the frame layer information in the x-vector. It is developed by applying the attention mechanism to the traditional Gated Recurrent Unit to enhance the learning ability of the x-vector system. The whole system follows the statistics pooling from each time-delay neural network layer of the x-vector baseline. It passes through the Dual-Sequences Gate Attention Unit layer to aggregate more information from the variant temporal context of input features while training at the frame level. We train our model on the Voxceleb2 and then evaluate the accuracy of Voxceleb1 and the Speakers in the Wild dataset for simulation. Finally, the system is compared with the x-vector, L-vector, and ETDNN-OPGRUs x-vector. There is an obvious improvement to our proposed method. Compared with the x-vector system, it shows that at least 17.5% on Voxceleb1 and 0.5% on Speakers in the Wild equal error rate improvement is achieved in the fusion system.

FBN: Federated Bert Network with client-server architecture for cross-lingual signature verification

Online signature verification has a great challenge due to the poor performance of deep learning techniques on cross-lingual datasets under privacy constraints. In this paper, we propose a novel Federated Bert Network (FBN) by embedding the Bidirectional Encoder Representations from Transformers (Bert) into a Federated Learning (FL) framework with client-server architecture. A new Length Alignment Algorithm is employed to unify the signature pairs’ sequence length, and the input representations are fed into the different clients to complete the independent learning of local-models. In addition, the server (coordinator) uses the improved Federated Average Algorithm with Reward-Punishment Mechanism (FedAvgRP) to aggregate these local-models and further generate a global-model. After multiple iterations, the optimal model can be obtained and cross-tested on four datasets (SVC 2004, MCYT-330, BioecurID, and Ours) with skilled forged (random forged) EERs of 7.65% (4.76%), 10.73% (8.46%), 10.09% (7.13%), and 8.28% (5.74%), respectively, far higher than that of the independent learning of state-of-the-art methods. Compared with the domain adaptation and improved FL models, our FBN model performs best in random and skilled forgery scenarios. Moreover, the FedAvgRP algorithm helps our model maintain high performance in the face of data attacks.

Runtime Verification for Anomaly Detection of Robotic Systems Security

Robotic systems are widely used in industry, agriculture, the inspection of infrastructure, and even in our daily lives. The safety and security of robotic systems have become a primary concern as their interaction with humans increases. In this context, attacks on robotic systems have increased for diversified field applications. It is necessary to accurately detect these abnormal events in these systems as soon as possible. However, these systems also need a runtime verification approach on whether they conform to the established specifications. In this study, runtime verification for anomaly detection methods is proposed for the security of the robot operating system (ROS). Firstly, an anomaly detection method is proposed to detect unexpected situations, such as the number of the received packages being decreased under DoS attacks. Then, a holistic runtime verification architecture is proposed for the anomaly detection method. This architecture consists of three major entities: a verification device, an attacker device, and a robotic platform without losing generality. In the verification device, ROSMonitoring and Oracle are used to implement runtime verification. The proposed architecture is verified through an experimental setup. It is shown that the architecture can be used for runtime verification of different anomaly detection algorithms. A discussion on the security of robotic systems is also presented.

Design and verification of memory by using UVM methodology

The design and verification of memory using the Universal Verification Methodology (UVM) methodology is discussed in this research. The advanced verification architecture uses a minimum number of macros, methods, and classes, and it provides high reusability for UVM tests. It makes use of the common attributes between different memory controllers to generate a common and configurable scoreboard, sequences, stimulus, different UVM components, and test cases. The memory controller provides a constructive control of data between the processor and memory. It provides modern structure and building blocks to work with codes, and it allows a dynamic approach. Simulation results show that the designed controller has a good performance and meets all the system specifications.

ACLMHA and FML: A brain-inspired kinship verification framework.

As an extended research direction of face recognition, kinship verification based on the face image is an interesting yet challenging task, which aims to determine whether two individuals are kin-related based on their facial images. Face image-based kinship verification benefits many applications in real life, including: missing children search, family photo classification, kinship information mining, family privacy protection, etc. Studies presented thus far provide evidence that face kinship verification still offers many challenges. Hence in this paper, we propose a novel kinship verification architecture, the main contributions of which are as follows: To boost the deep model to capture various and abundant local features from different local face regions, we propose an attention center learning guided multi-head attention mechanism to supervise the learning of attention weights and make different attention heads notice the characteristics of different regions. To combat the misclassification caused by single feature center loss, we propose a family-level multi-center loss to ensure a more proper intra/inter-class distance measurement for kinship verification. To measure the potential similarity of features among relatives better, we propose to introduce the relation comparison module to measure the similarity among features at a deeper level. Extensive experiments are conducted on the widely used kinship verification dataset-Family in the Wild (FIW) dataset. Compared with other state-of-art (SOTA) methods, encouraging results are obtained, which verify the effectiveness of our proposed method.

LRVP: Lightweight Real-Time Verification of Intradomain Forwarding Paths

The correctness of user traffic forwarding paths is an important goal of trusted transmission. Many network security issues are related to it, i.e., denial-of-service attacks, route hijacking, etc. The current path-aware network architecture can effectively overcome this issue through path verification. At present, the main problems of path verification are high communication and high computation overhead. To this aim, this article proposes a lightweight real-time verification mechanism of intradomain forwarding paths in autonomous systems to achieve a path verification architecture with no communication overhead and low computing overhead. The problem situation is that a packet finally reaches the destination, but its forwarding path is inconsistent with the expected path. The expected path refers to the packet forwarding path determined by the interior gateway protocols. If the actual forwarding path is different from the expected one, it is regarded as an incorrect forwarding path. This article focuses on the most typical intradomain routing environment. A few routers are set as the verification routers to block the traffic with incorrect forwarding paths and raise alerts. Experiments prove that this article effectively solves the problem of path verification and the problem of high communication and computing overhead.

RSKNet-MTSP: Effective and portable deep architecture for speaker verification

The convolutional neural network (CNN) based approaches have shown great success for speaker verification (SV) tasks, where modeling long temporal context and reducing information loss of speaker characteristics are two important challenges significantly affecting the verification performance. Previous works have introduced dilated convolution and multi-scale aggregation methods to address above challenges. However, such methods are also hard to make full use of some valuable information, which make it difficult to substantially improve the verification performance. To address above issues, we construct a novel CNN-based architecture for SV, called RSKNet-MTSP, where a residual selective kernel block (RSKBlock) and a multiple time-scale statistics pooling (MTSP) module are proposed. The RSKNet-MTSP can capture both long temporal context and neighbouring information, and gather more speaker-discriminative information from multi-scale features. In order to design a portable model for real applications with limited resources, we then present a lightweight version of RSKNet-MTSP, namely RSKNet-MTSP-L, which employs a combination technique associating the depthwise separable convolutions with low-rank factorization of weight matrices. Extensive experiments are conducted on two public SV datasets, VoxCeleb and Speaker in the Wild (SITW). The results demonstrate that 1) RSKNet-MTSP significantly outperforms the state-of-the-art deep embedding architectures on all five test sets; 2) RSKNet-MTSP-L achieves competitive performance with 17%-44% less network parameters compared to baseline models. The ablation experiments further illustrate that our proposed approaches can achieve substantial improvement over prior methods.

An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification.

In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large volume of data and associated structures, making it a computationally intensive process. Currently, the state-of-the-art data centers for genome sequencing incur substantial setup and energy costs for maintaining hardware, data storage and cooling systems. To enable low-cost genomics, we propose an energy-efficient architectural methodology for read mapping using a single system-on-chip (SoC) platform. The proposed methodology is based on the q-gram lemma and designed using a novel architecture for filtering and verification. The filtering algorithm is designed using a parallel sorted q-gram lemma based method for the first time, and it is complemented by an in-situ verification routine using parallel Myers bit-vector algorithm. We have implemented our design on the Zynq Ultrascale+ XCZU9EG MPSoC platform. It is then extensively validated using real genomic data to demonstrate up to 7.8× energy reduction and up to 13.3× less resource utilization when compared with the state-of-the-art software and hardware approaches.

Physical layer protection for ADS-B against spoofing and jamming

Automatic Dependent Surveillance-Broadcast (ADS-B) is a widely used secondary surveillance radar standard for aviation and is a significant component in ensuring air traffic safety. Unfortunately, it has been demonstrated that ADS-B has security flaws. This paper addresses some of these issues by proposing a method and system architecture for verification of received signal authenticity on ADS-B In enabled aircraft. The method is based on physical layer signal analysis, i.e. estimation of signal source range and direction-of-arrival. Proposed system architecture includes a directional slotted antenna system and multi-channel receiver on ADS-B In side, but requires no change to existing ADS-B protocol. The proposed techniques provide security against message injection attacks, such as spoofing, and partial security against jamming. We assess estimation of error bounds and performance of the proposed techniques in simulated use-case scenarios.

ConvNet for Finger Vein based Personal Authentication

The human brain, can easily perceive and differentiate the objects in an image. Subsequently the field of computer vision intent to mimic / simulate the human vision system. Finger vein-based user authentication has been used to control access and maintaining privacy of confidential data. The main challenges in the finger vein verification are the quality of an acquired images due to uneven illumination of light, quality of sensor, positional variation and environmental condition. In this article, we used Wiener filter, to improve the quality of finger vein images. These noise free images are provided for training to popular pretrained ConvNet architecture for user verification using finger vein biometric. Then we analysed the performance of ConvNet (convolutional neural networks) such as Alex Net, Squeeze Net, Google Net, Shuffle Net, Efficient Net, Mobile Net, Res Net, Dense Net and NASNet for the finger vein based personal authentication to secure confidential data and maintain privacy. The finger vein images from Kaggle database is used for this research work. The experiment exhibits the outstanding performance of resnet101 with the 97.64% accuracy over its peer networks.

A composite SystemC-UVM abstract optimal path selection verification architecture for complex designs

Universal Verification Methodology (UVM) architectures are highly trained for stimulus generation and verification of System-on-chip (SoC). The cross-functional and cross-platform interactive verification is the limitation of a sole UVM architecture. Sole UVM objects are not efficient to satisfy cross-functional compatibility requirements. A system C verification libraries have a mechanism of introspection. The data introspection is not capable of wide cross-platform use without reusable portable accurate TLM. So a UVM module requires a SystemC block to aim for the cross-functional working of verification. The work shows a composite UVM-SystemC methodology to rationally adhere to optimal test path selection among all test paths. The work presents SC-UVM (SystemC-UVM) architecture for cross-platform working facilitation. The learning methodology works to improvise coverage parameters with the optimization of coverage bins. The methodology earns a significant contribution for early verification by reducing the internal data processing and simulation time. The SystemC-UVM method outperforms the conventional SystemVerilog and Sole UVM verification techniques. The work declares the improvement of 5.26% in simulation time with 5.11% lesser data processing for database creation in front of the sole UVM verification architecture.

ConTrust: A Novel Context-Dependent Trust Management Model in Social Internet of Things

The global population is around 7.4 billion people. This population density requires connectivity to improve the standard of living by transmitting and receiving variety of services. As a result, numerous forms of communication among objects are required for our everyday living demands, independent of their nature. Furthermore, to create a good relationship, every object that is regarded as associate of another object should have distinct criteria such as scalability, interoperability, and trustworthiness. Many security threats, however, have an impact on the social interaction between objects in a social internet of things (SIoT) context, including illegal admittance and suspicious behavior owing to a lack of verification architecture. Others include attempting to provide a proper viewpoint of a malicious object to earn the trust of other objects. As a result, there is a requirement for an acceptable method to check the behavior of objects such as capability, commitment, reliability, and previous job satisfaction before proceeding with any type of job assignment. This will aid in distinguishing between malicious and trustworthy objects by anticipating their upcoming behavior, allowing better judgments regarding service assignment to be made. This study proposes a context-dependent trust management technique (ConTrust) for choosing and allocating jobs in a SIoT environment. The feature-property match approach, as well as the combination of capability, commitment, and satisfaction, were utilized to increase the efficiency of trust assessment and the resolution of context-dependent difficulties. The proposed trust model considers job characteristics, object capabilities and honesty, and the impact of malicious conduct. The experimental results show that the proposed ConTrust model is viable and capable of ensuring the reliability and efficacy of SIoT service sharing between objects as compared to the benchmark models considered in this work.

SEMRES - A Triple Security Protected Blockchain Based Medical Record Exchange Structure

Background and ObjectiveCOVID-19, a serious infectious disease outbreak started in the end of 2019, has caused a strong impact on the overall medical system, which reflects the gap in the volume and capacity of medical services and highlights the importance of clinical data ex-change and application. The most important concerns of medical records in the medical field include data privacy, data correctness, and data security. By realizing these three goals, medical records can be made available to different hospital information systems to achieve the most complete medical care services. The privacy and protection of health data require detailed specification and usage requirements, which is particularly important for cross-agency data exchange. MethodsThis research is composed of three main modules. "Combined Encryption and Decryption Architecture", which includes the hybrid double encryption mechanism of AES and RSA, and encrypts medical records to produce "Secured Encrypted Medical Record". "Decentralize EMR Repository", which includes data decryption and an exchange mechanism. After a data transmission is completed, the content verification and data decryption process will be launched to confirm the correctness of the data and obtain the data. A blockchain architecture is used to store the hash value of the encrypted EMR, and completes the correctness verification of the EMR after transmission through the hash value. ResultsThe results of this study provide an efficient triple encryption mechanism for electronic medical records. SEMRES ensures the correctness of data through the non-repudiation feature of a blockchain open ledger, and complete integrated information security protection and data verification architecture, in order that medical data can be exchanged, verified, and applied in different locations. After the patient receives medical services, the medical record is re-encrypted and verified and stored in the patient's medical record. The blockchain architecture is used to ensure the verification of non-repudiation of medical service, and finally to complete the payment for medical services. ConclusionsThe main aim of this study was to complete a security architecture for medical data, and develop a triple encryption authentication architecture to help data owners easily and securely share personal medical records with medical service personnel.

Blockchain Integrated Healthcare Wireless Body Area Network for Security Enhancement

A greater standard of network confidentiality and protection is generally accepted as a vital component of securing this data when employed by medical practitioners as well as during storage to guarantee that patient data are maintained safe from intruders. This paper develops block chain cryptography and bio-informatics verification architecture for WBANs implementations. As a result, there is a deep desire to solve security and privacy challenges with WBANs. WBANs confront a wide range of problems. Because of its versatility in a wide range of applications, WBAN is a favoured battleground for cybercriminals. This work also provides a blockchain integrity check and bio-informatics authentication framework for WBANs implementations. Hence there is an important interest to address security and privacy problems in WBANs.

Functional verification of a sigma-delta ADC real number model

ABSTRACT Mixed-signal applications form one of the hottest topics in the semiconductor industry. Considerable effort is required for the creation of designs that consist of both analog and digital blocks with high accuracy and performance. Therefore, mixed-signal verification can be considered as a significant matter. Former conventional verification approaches present very slow verification time, which ultimately increases time-to-market. A circuit of interest in modern systems is the sigma-delta analog-to-digital converter (ADC), which is used for encoding analog signals into digital codes, and many other applications. In this work, an effective functional verification architecture using Universal Verification Methodology (UVM) for a SystemVerilog-based sigma-delta ADC real-number model is proposed. The UVM effectiveness of the presented approach encourages the creation of a verification architecture with increased reusability and robustness, with respect to previous literature. The presented verification environment utilises constrained-random stimuli that exploit a novel sine-wave generator, analog assertions and coverage metrics for improved functional verification. Additionally, a metric for verification quality estimation is introduced for comparisons with other reference verification approaches. In all cases, the presented architecture verified the proper operation of the sigma-delta ADC with coverage of more than 98%, in accordance with the specification parameters that were used for the model.

Real-time automated register abstraction active power-aware electronic system level verification framework

All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope up with the ever increasing demand, an active power-aware management verification architecture is necessary to minimize the power consumption. Power reduction techniques include clock-gating, power-gating, multi-voltage, and voltage-frequency scaling. The proposed verification architecture utilizes the Unified Power Format (UPF) 2.1 libraries to achieve early design verification at the Electronic System-Level (ESL) of abstraction. The proposed testbench can verify several designs of different power management schemes. The presented work offers a reduction in power states, CPU time and simulation time as compared to existing techniques. The interactive formal and simulation-based verification methods are used in this paper to remove the simulation artifacts during functional and power co-simulation. Additionally, this paper incorporates functional correctness and power-aware checks for different modules of Design Under Verification (DUV) at Transaction-Level Modeling (TLM).