Architecture For Real-time Implementation Research Articles

Design of real-time video watermarking based on Integer DCT for H.264 encoder

With the advent of technology, video has become a prominent entity that is shared over networks. With easy availability of various editing tools, data integrity and ownership issues have caused great concern worldwide. Video watermarking is an evolving field that may be used to address such issues. Till date, most of the algorithms have been developed for uncompressed domain watermarking and implemented on software platforms. They provide flexibility and simplicity, but at the same time, they are not suited for real-time applications. They work offline where videos are captured and then watermark is embedded in the video. In the present work, a hardware-based implementation of video watermarking is proposed that overcomes the limitation of software watermarking methods and can be readily adapted to the H.264 standard. This paper focuses on an invisible and robust video watermarking scheme, which can be easily implemented as an integral part of the standard H.264 encoder. The proposed watermarking algorithm involves Integer DCT-based watermark embedding method, wherein Integer DCT is calculated with a fully parallel approach resulting in better speed. The proposed video watermarking is designed with pipelining and parallel architecture for real-time implementation. Here, scene change detection technique is used to improve the performance. Different planes of the watermark are embedded in different frames of a particular scene in order to achieve robustness against various temporal attacks.

CORDIC-based VLSI architecture for real time implementation of flat top window

Since decades, popular window techniques such as Hanning, Hamming, Blackman and Flat top window have been used to minimize unwanted effects like spectral leakage and scalloping losses due to direct truncation of signals before fast Fourier transform (FFT) processor. Conventionally, software and further ROM based implementation of aforesaid window functions have been adopted for real time applications where throughput in the case of software implementation and flexibility in the case of ROM based implementation are the main constraints. Recently, variable length FFT architectures to support wide range of applications in the domain of signal, image and communication system have been developed which demand variable length window architectures. To the knowledge of authors, window techniques such as Hanning, Hamming and Blackman are addressed for real time VLSI implementation; however one of the popular window technique, i.e. flat top window has not been addressed for efficient VLSI implementation. In this context, authors in this paper have proposed a novel, flexible and hardware efficient VLSI architecture for flat top window using CORDIC (Co-ordinate rotation digital computer) along with control units to ensure high throughput. This proposed VLSI architecture for implementing flat top window function is prototyped on commercially available FPGA (Field Programmable Gate Array) device, i.e. Spartan 3E XC3S500E. The first order analysis along with implementation results and error analysis of proposed architecture are highlighted.

An Efficient Double-Filter Hardware Architecture for H.264/AVC Deblocking Filtering

In this paper, a novel hardware architecture for real-time implementation of the adaptive deblocking filtering process specified by the H.264/AVC video coding standard, is presented. The deblocking filter is a computationally and data intensive tool resulting in an increased execution time of both the encoding and decoding processes. The proposed architecture is based on a double- filter strategy that results in a significant saving in filtering cycles, memory requirements and gate count when compared with state-of-the-art approaches. The proposed architecture is implemented in synthesizable HDL at RTL level and verified with the reference software. This hardware is designed to be used as part of a complete H.264/A VC video coding system.

A COMPARATIVE ANALYSIS OF H.264 VIDEOCOMPRESSION STANDARD USING DIFFERENT ENTROPY CODING METHODS

In this paper, we present a comparative performance analysis of low power hardware architecture for real time implementation of context adaptive binary arithmetic coding algorithm and Context-based adaptive Variable Length Coding algorithm (CAVLC) used in H.264/ MPEG part 10 video coding standards. The video compression efficiency achieved in H.264 standard is not a result of any single feature but rather a combination of a number of encoding tools. CAVLC requires considerably more processing power to decode. The encoding process is simulated by MATLAB which compress the input video sequence and ensures better performance in video compression. The results that are obtained reveal better performance of both entropy coding methods.

OPTIMAL SYSTOLIC ARRAYS FOR REAL-TIME IMPLEMENTATION OF THE MODIFIED COVARIANCE SPECTRAL ESTIMATOR

The Modified Covariance method of spectral estimation, proposed as a replacement of the conventional short term Fourier transform for use with pulsed Doppler ultrasound blood flow detectors in order to improve time/frequency resolution, is computationally far more demanding. The use of an application specific architecture for real-time implementation is of interest. A cost/benefit selection of systolic arrays, firstly for a matrix solution method with suitable bus width and secondly for calculation of covariance matrix elements, led to the choice of Cholesky matrix decomposition, 12 bit bus width and a bi-linear systolic array designed using a data dependence graph method.

Associative memory architecture for video compression

Video compression is becoming increasingly important, with several applications. There are two kinds of redundancies in a video sequence, namely spatial and temporal. Vector quantisation (VQ) is an efficient technique for exploiting spatial correlation. Temporal redundancies are usually removed by using motion estimation/compensation techniques. The coding performance of VQ may be improved by employing adaptive techniques at the expense of increases in computational complexity. Both VQ and motion estimation algorithms are essentially template matching operations. However, they are computer intensive, necessitating the use of special-purpose architectures for real-time implementation. The authors propose a unified associative memory architecture for real-time implementation of motion estimation and frame-adaptive vector quantisation for video compression. The proposed architecture has the advantage of simplicity, partitionability and modularity and has hence the potential for VLSI implementation.

Stream processing architecture for real-time implementation of perspective spatial transformations

A system is presented which is capable of performing perspective spatial transformations at video rate, by means of a mapping function which can vary at frame rate. The mapping is implemented by two successive applications of a one-dimensional algorithm operating in scan-line order, using a framestore to store an intermediate image. A novel one-dimensional filtering algorithm provides a continuous mapping from source to destination co-ordinates, significantly reducing aliasing. Emphasis is placed on the design of a novel stream processing architecture which, coupled with an efficient pipelined co-ordinate generation system, provides single-cycle per output pixel performance.

A Multiprocessor Architecture for Two-Dimensional Digital Filters

In this paper, a generic computational primitive is developed for the implementation of any arbitrary order one-dimensional or two-dimensional FIR or IIR digital filter. This computational primitive can form the basis for a single chip processor for one-dimensional and two-dimensional digital signal processing. A multiprocessor architecture for real-time implementation of spatial domain filters is developed with each processing unit in the network implementing the computational primitive. This multiprocessor system has a simple control scheme, a simple interconnection network, a very high efficiency, and low data transfers and storage requirements. Thus, it avoids the bottlenecks associated with traditional parallel computers and multiprocessor systems.