Hardware Architecture Research Articles

Introduction to Memristive Mechanisms and Models.

The increase in computational power demand led by the development of Artificial Intelligence is rapidly becoming unsustainable. New paradigms of computation, which potentially differ from digital computation, together with novel hardware architecture and devices, are anticipated to reduce the exorbitant energy demand for data-processing tasks. Memristive systems with resistive switching behavior are under intense research, given their prominent role in the fabrication of memory devices that promise the desired hardware revolution in our intensive data-driven era. They are suggested to provide the hardware substrate to scale up computational capabilities while improving their energy expenditure and speed. This work provides an orientation map for those interested in the vast topic of memristive systems with application to neuromorphic computing. We address the description of the most notable emerging devices and we illustrate models that capture the complex dynamical behavior of these systems under the dynamical-systems framework developed by Chua. We then review the memristive behavior under the perspective of statistical physics and percolation theory suited to describe fluctuations and disorder which are otherwise precluded in the dynamical-system approach. Percolation theory allows the investigation of these systems at the mesoscopic level, enabling material-independent modeling of non-linear conductance networks. We finally discuss recent and less recent successes in deep learning methods that bridge the field of physics-based and biological- inspired neuromorphic computing.

Cloud/VPN-Based Remote Control of a Modular Production System Assisted by a Mobile Cyber-Physical Robotic System-Digital Twin Approach.

This paper deals with a "digital twin" (DT) approach for processing, reprocessing, and scrapping (P/R/S) technology running on a modular production system (MPS) assisted by a mobile cyber-physical robotic system (MCPRS). The main hardware architecture consists of four line-shaped workstations (WSs), a wheeled mobile robot (WMR) equipped with a robotic manipulator (RM) and a mobile visual servoing system (MVSS) mounted on the end effector. The system architecture integrates a hierarchical control system where each of the four WSs, in the MPS, is controlled by a Programable Logic Controller (PLC), all connected via Profibus DP to a central PLC. In addition to the connection via Profibus of the four PLCs, related to the WSs, to the main PLC, there are also the connections of other devices to the local networks, LAN Profinet and LAN Ethernet. There are the connections to the Internet, Cloud and Virtual Private Network (VPN) via WAN Ethernet by open platform communication unified architecture (OPC-UA). The overall system follows a DT approach that enables task planning through augmented reality (AR) and uses virtual reality (VR) for visualization through Synchronized Hybrid Petri Net (SHPN) simulation. Timed Petri Nets (TPNs) are used to control the processes within the MPS's workstations. Continuous Petri Nets (CPNs) handle the movement of the MCPRS. Task planning in AR enables users to interact with the system in real time using AR technology to visualize and plan tasks. SHPN in VR is a combination of TPNs and CPNs used in the virtual representation of the system to synchronize tasks between the MPS and MCPRS. The workpiece (WP) visits stations successively as it is moved along the line for processing. If the processed WP does not pass the quality test, it is taken from the last WS and is transported, by MCPRS, to the first WS where it will be considered for reprocessing or scrapping.

Implementation and Analysis of Enhanced Performance of Elliptic Curve Cryptography Processor Over Prime Field

ABSTRACTDesigning an optimized performance elliptic curve cryptography (ECC) processor capable of rapid point multiplication while saving hardware resources is an essential part of system security. This study introduces the implementation of a field‐programmable gate array (FPGA) design of the ECC processor (ECCP), prioritizing speed, compactness, maximum operating frequency, and resultant throughput rate in the prime field of 256‐bit. The processor enables efficient point multiplication for 256 bits in the twisted Edwards25519 curve, which is vital for the strength of the Edwards curve digital signature algorithm (EdDSA). Unique architectures of hardware for different modular and group operations in the twisted Edwards curve are proposed in this work. The processor achieves modular multiplication, point addition, and doubling in only 257, 1286, and 518 clock cycles, respectively. For 256‐bit keys, a point multiplication takes 0.51 ms, which operates at the highest frequency of 226.7 MHz with a cycle count of 115.2 k and a throughput of 501.9 Kbps. The implementation, executed on the Kintex‐7 platform for FPGA implementation in projective coordinates, utilizes 14.7 k slices. This design demonstrates time‐ and throughput‐efficient design by providing fast scalar multiplication while using minimum hardware resources without compromising security. The proposed ECCP on the Edwards curve's performance is improved in such a way that the device uses optimized area, time, frequency, and throughput rate. To generate a key for the ECCP and EdDSA, we simulate various operations like modular arithmetic operations, group operations, and point operations required for correct ECPM implementation on Xilinx ISE and ModelSim. Then we verify these results using the Maple tool.

Implementation and Preliminary Results of the First Vertical Stabilization Control System for HL-2M

Achieving advanced divertor configurations and high-confinement operating regimes is crucial for mitigating divertor heat loads and exploring enhanced confinement physics in the HL-2M tokamak. However, these scenarios with highly elongated plasmas face severe vertical displacement events that can lead to rapid plasma termination and potential device damage. Robust active control of vertical instability is therefore essential. As HL-2M lacks internal control coils, we developed two sets of vertical stabilization (VS) control systems, each employing a pair of external poloidal field (PF) coils, PF main power supplies, and VS power supplies. This paper details the first vertical stabilization (VS1) control system’s circuit diagram, hardware architecture, and software implementation and discusses issues encountered during commissioning and their solutions. By improving the internal hardware of the VS power supply, the voltage rise time was reduced to approximately 30 μs, resolving branch current imbalances. The transmission delay of the control signals is approximately 38 μs. Preliminary plasma experiments demonstrated effective vertical displacement control with the VS1 control system, achieving a maximum plasma elongation of 1.73 and typical control accuracy of ~20 mm. This work lays the foundation for robust control under high-parameter operational scenarios and the design and implementation of the higher-power second vertical stabilization (VS2) control system.

A high performance heterogeneous hardware architecture for brain computer interface.

Brain-computer interface (BCI) has been widely used in human-computer interaction. The introduction of artificial intelligence has further improved the performance of BCI system. In recent years, the development of BCI has gradually shifted from personal computers to embedded devices, which boasts lower power consumption and smaller size, but at the cost of limited device resources and computing speed, thus can hardly improve the support of complex algorithms. This paper proposes a heterogeneous BCI architecture based on ARM + FPGA, enabling real-time processing of electroencephalogram (EEG) signals. Adopting data quantization, layer fusion and data augmentation to optimize the compact neural network model EEGNet, and design dedicated hardware engines to accelerate the network. Experimental results show that the system achieves 93.3% classification accuracy for steady-state visual evoked potential signals, with a time delay of 0.2ms per trail, and a power consumption of approximately (1.91W). That is 31.5 times faster acceleration is realized at the cost of only 0.7% lower accuracy compared with the conventional processor. The results show that the BCI architecture proposed in this study has strong practicability and high research significance.

Cooperative Spectrum Sensing Architecture for Energy-Efficient Data-Fusion-Based Cognitive Radio Network

This demand can be satisfied by cognitive radio (CR) technology thanks to the growing desire to utilize existing radio frequency bands more effectively. This paper suggests a hardware-efficient, very-large spectrum sensor. In cooperative cognitive radio networks, data fusion is not provided by a new-scale integration (VLSI) architecture. The cooperative method to spectrum sensing and management as a proposed concept uses approaches for data fusion to address the difficulties. Our VLSI system delivers high throughput with exceptional performance by combining the latest sensing algorithms with an effective hardware architecture. The overall performance of the spectrum and spectrum awareness are enhanced by the cooperative theoretical radio communication system. In order to enable the network to make judgements that can be modified utilizing combined data from scattered spectrum sensors, the study examines the integration of network fusion techniques. The suggested scheme's primary characteristics are its hardware efficiency, low power consumption, and real-time flexibility for changing spectrum conditions. Through simulations and comparison with existing methods, it is assessed. System performance is tracked, and the results indicate that faster and more accurate spectrum sensing is required in order to apply notions of spectrum sharing that make sense.

From materials to applications: a review of research on artificial olfactory memory.

Olfactory memory forms the basis for biological perception and environmental adaptation. Advancing artificial intelligence to replicate this biological perception as artificial olfactory memory is essential. The widespread use of various robotic systems, intelligent wearable devices, and artificial olfactory memories modeled after biological olfactory memory is anticipated. This review paper highlights current developments in the design and application of artificial olfactory memory, using examples from materials science, gas sensing, and storage systems. These innovations in gas sensing and neuromorphic technology represent the cutting edge of the field. They provide a robust scientific foundation for the study of intelligent bionic devices and the development of hardware architectures for artificial intelligence. Artificial olfaction will pave the way for future advancements in intelligent recognition by progressively enhancing the level of integration, understanding of mechanisms, and application techniques of machine learning algorithms.

Novel hardware architectures of improved-LEA lightweight cipher for IoT applications

Novel hardware architectures of improved-LEA lightweight cipher for IoT applications

PACE: A Piece-Wise Approximate Floating-Point Divider with Runtime Configurability and High Energy Efficiency

Approximate computing emerges as a viable solution to enhance energy efficiency in applications sensitive to human perception, particularly on edge devices. This work introduces a novel piece-wise approximate floating-point divider that boasts resource efficiency and runtime configurability. Our method leverages a piece-wise approximation algorithm for computing 1/ y by exploiting powers of 2, complemented by an error compensation technique grounded in thorough mathematical analysis. This approach facilitates the realization of a reciprocal-based floating-point divider devoid of multipliers, which not only mitigates hardware resource consumption but also reduces latency. Additionally, we unveil a multi-level runtime configurable hardware architecture that significantly improves flexibility across diverse application contexts. Compared to the existing state-of-the-art approximate dividers and truncated exact dividers, our proposed solution achieves a superior compromise between precision and resource efficiency. Application-level evaluations reveal that our design provides over 87.7% energy saving, while maintaining a negligible impact on output quality.

Hardware Area Efficient and Real-Time FPGA Implementation of PHMMRGB.

For encryption applications on embedded systems, operating in real-time while using minimal system resources is essential. It is expected that efficient and rapid encryption of high-resolution images is to be accomplished with limited hardware resources. Therefore, to ensure the desired efficiency of encryption of high-resolution images, the system must possess a digital architecture capable of achieving high speeds with minimal hardware resources. This study considered the limitations of a hardware architecture for an image encryption algorithm based on the Profile Hidden Markov Model called PHMMRGB. The proposed architecture is relatively simple in comparison to its alternatives. The hardware architecture, designed with the objective of using minimal resources, has been implemented on an FPGA. Based on the results of the proposed architecture, it is believed that the implementation of the specified method on an FPGA would yield high efficiency. Experiments conducted using large-sized satellite images confirmed this expectation.

ALOHA-FP2I: Efficient Algorithms and Hardware for Multi-Mode Rounding of Floating Point to Integer

Modern technology is relying on hardware accelerators to achieve enhanced performance of computing systems. In the modern computing paradigm, floating point representation of numbers has gained popularity owing to its wide dynamic range. Rounding of floating point numbers to integer is used in modern processor architectures e.g., ARM and Intel's architecture (IA) as well as in specific applications such as multimedia. However, the academic literature lacks discussion on hardware designs for rounding binary floating point numbers to integer in different rounding modes. This article presents novel efficient algorithms and hardware architecture designs for rounding binary floating point numbers to the integer for the following rounding modes: round towards zero, round up (towards positive infinity), round down (towards negative infinity), round to the nearest integer, and round to nearest even. The article also proposes an integrated multi-mode rounding (IMR) algorithm and hardware design which can be configured to a specific rounding mode among the above-mentioned five modes. This article proposes a mantissa bit of rounding (MBR) to determine the condition of rounding for the various modes. The MBR is identified on the basis of the dynamic range and precision features of floating point representation. To the best of our knowledge, we present the individual as well as an integrated hardware design for the various rounding modes for the first time in the literature. The proposed designs have been implemented on an FPGA platform to analyze the design metrics such as area, delay, and power. The results imply that the proposed designs are suitable to aid the intended hardware accelerators as they are efficient in terms of the design parameters. Moreover, this article presents the integration of the proposed rounding hardware design with the compression processor and evaluates the integration overhead which is found to be nominal (<1%).

Context-Adaptable Deployment of FastSLAM 2.0 on Graphic Processing Unit with Unknown Data Association

Simultaneous Localization and Mapping (SLAM) algorithms are crucial for enabling agents to estimate their position in unknown environments. In autonomous navigation systems, these algorithms need to operate in real-time on devices with limited resources, emphasizing the importance of reducing complexity and ensuring efficient performance. While SLAM solutions aim at ensuring accurate and timely localization and mapping, one of their main limitations is their computational complexity. In this scenario, particle filter-based approaches such as FastSLAM 2.0 can significantly benefit from parallel programming due to their modular construction. The parallelization process involves identifying the parameters affecting the computational complexity in order to distribute the computation among single multiprocessors as efficiently as possible. However, the computational complexity of methodologies such as FastSLAM 2.0 can depend on multiple parameters whose values may, in turn, depend on each specific use case scenario ( ingi.e., the context), leading to multiple possible parallelization designs. Furthermore, the features of the hardware architecture in use can significantly influence the performance in terms of latency. Therefore, the selection of the optimal parallelization modality still needs to be empirically determined. This may involve redesigning the parallel algorithm depending on the context and the hardware architecture. In this paper, we propose a CUDA-based adaptable design for FastSLAM 2.0 on GPU, in combination with an evaluation methodology that enables the assessment of the optimal parallelization modality based on the context and the hardware architecture without the need for the creation of separate designs. The proposed implementation includes the parallelization of all the functional blocks of the FastSLAM 2.0 pipeline. Additionally, we contribute a parallelized design of the data association step through the Joint Compatibility Branch and Bound (JCBB) method. Multiple resampling algorithms are also included to accommodate the needs of a wide variety of navigation scenarios.

A High-performance NTT/MSM Accelerator for Zero-knowledge Proof Using Load-balanced Fully-pipelined Montgomery Multiplier

Zero-knowledge proof (ZKP) is an attractive cryptographic paradigm that allows a party to prove the correctness of a given statement without revealing any additional information. It offers both computation integrity and privacy, witnessing many celebrated deployments, such as computation outsourcing and cryptocurrencies. Recent general-purpose ZKP schemes, e.g., zero-knowledge succinct non-interactive argument of knowledge (zk-SNARK), suffer from time-consuming proof generation, which is mainly bottlenecked by the large-scale number theoretic transformation (NTT) and multi-scalar point multiplication (MSM). To boost its wide application, great interest has been shown in expediting the proof generation on various platforms like GPU, FPGA and ASIC.So far as we know, current works on the hardware designs for ZKP employ two separated data-paths for NTT and MSM, overlooking the potential of resource reusage. In this work, we particularly explore the feasibility and profit of implementing both NTT and MSM with a unified and high-performance hardware architecture. For the crucial operator design, we propose a dual-precision, load-balanced and fully-pipelined Montgomery multiplier (LBFP MM) by introducing the new mixed-radix technique and improving the prior quotient-decoupled strategy. Collectively, we also integrate orthogonal ideas to further enhance the performance of LBFP MM, including the customized constant multiplication, truncated LSB/MSB multiplication/addition and Karatsuba technique. On top of that, we present the unified, scalable and highperformance hardware architecture that conducts both NTT and MSM in a versatile pipelined execution mechanism, intensively sharing the common computation and memory resource. The proposed accelerator manages to overlap the on-chip memory computation with off-chip memory access, considerably reducing the overall cycle counts for NTT and MSM.We showcase the implementation of modular multiplier and overall architecture on the BLS12-381 elliptic curve for zk-SNARK. Extensive experiments are carried out under TSMC 28nm synthesis and similar simulation set, which demonstrate impressive improvements: (1) the proposed LBFP MM obtains 1.8x speed-up and 1.3x less area cost versus the state-of-the-art design; (2) the unified accelerator achieves 12.1x and 5.8x acceleration for NTT and MSM while also consumes 4.3x lower overall on-chip area overhead, when compared to the most related and advanced work PipeZK.

Fast and efficient hardware architecture of Chebyshev polynomials algorithm for resisting to side channel attacks

Fast and efficient hardware architecture of Chebyshev polynomials algorithm for resisting to side channel attacks

PIMCoSim: Hardware/Software Co-Simulator for Exploring Processing-in-Memory Architectures

As the scope of artificial intelligence (AI) expands and the structure becomes more complex, the amount of data for inference and training has increased. In traditional computer architectures, the memory bandwidth limitations have intensified bottlenecks in AI systems, and processing-in-memory (PIM) architectures have been proposed to overcome this issue. PIM is an architecture that performs computations within memory, thereby reducing data movement between the CPU and memory. However, since PIM is difficult to optimize as a general-purpose architecture, it is essential to adopt an architecture suitable for the target application. While various simulators and emulators have been introduced for the design space exploration (DSE) of different PIM architectures, simulators are limited in debugging hardware operations, and emulators face challenges in flexibly modifying the system configuration, as emulators implement the entire architecture in hardware. Therefore, this paper introduces PIMCoSim, a comprehensive hardware–software co-simulator for the DSE of DRAM-PIM systems. This co-simulator partially emulates simplified hardware-implemented processing elements (PEs) and integrates software models for memory operations, facilitating the DSE of PIM systems. To validate PIMCoSim, we analyzed results for different computational workloads by varying PIM structures and operational policies, demonstrating the efficiency of DRAM-PIM systems. The co-simulation approach in PIMCoSim aims to contribute to analyzing DRAM-PIM configurations and adopting optimized structures.

Digitalization of an Industrial Process for Bearing Production.

The developments in sensing, actuation, and algorithms, both in terms of Artificial Intelligence (AI) and data treatment, have open up a wide range of possibilities for improving the quality of the production systems in diverse industrial fields. The present paper describes the automatizing process performed in a production line for high-quality bearings. The actuation considered new sensing elements at the machine level and the treatment of the information, fusing the different sources in order to detect quality defects in the grinding process (waviness, burns) and monitoring the state of the tool. At a supervision level, an AI model has been developed for monitoring the complete line and compensating deviations in the dimension of the final assembly. The project also contemplated the hardware architecture for improving the data acquisition and communication among the machines and databases, the data treatment units, and the human interfaces. The resulting system gives feedback to the operator when deviations or potential errors are detected so that the quality issues are recognized and can be amended in advance, thereby reducing the quality cost.

Infrastructure and Tools for Testing the Vulnerability of Control Systems to Cyberattacks: A Coal Mine Industrial Facility Case

Testing the vulnerability of information systems to cyberattacks is essential to ensure the operational security of organizations and industrial processes. In particular, it is essential to ensure the resilience of industrial processes, as a possible cyberattack can lead to process malfunctions and even process shutdowns, which can lead to substantial economic losses. The possibility of various attacks, e.g., ransomware, phishing, or advanced persistent threats (APTs), requires the evaluation of the effectiveness of cyberattack detection and incident response mechanisms. In industry, it is often impossible to carry out this type of test without risking system disruption, making it difficult to assess the true effectiveness of security features. This article discusses the issues concerned with testing the cyber resilience of a system operating in a real coal mine. First, this work briefly presents the hardware and software architecture used in the coal mine. Secondly, it describes the problem of replicating a real system in the laboratory and the necessary tools and methods used to implement a resilient system architecture. Finally, the scenarios of cyberattacks are detailed, and the obtained results are discussed.

A Framework for Improving Portability and Ensuring Correctness of Operating System Kernels

Traditional embedded Real-Time Operating Systems (RTOS) or Basic Software (BSW) implementations typically require manual porting to new hardware platforms. However, this approach can be time-consuming and error-prone, especially given the frequent introduction of new or upgraded hardware architectures. In addition, traditional testing methods may not fully capture the complexity and nuances of the system, making it difficult to ensure correctness and dependability. To address these challenges, we propose a comprehensive methodology that integrates formal methods, a WCET tool, and a code generation technique. We use formal methods to create models and verify their correctness against functional and non-functional specifications or properties such as safety, liveness, and timing. We use the WCET tool as a microarchitecture analyzer to analyze the low-level binary code. The intermediate results of the tool are used to verify the correctness of the software implementation against the runtime effects of the hardware, such as data/memory race conditions. Finally, the code is generated from the formal models. Our proposed framework simplifies the maintenance of RTOS or BSW implementations while ensuring their correctness and partially automating portability to new hardware architectures.

ADEPT 2023 Workshop Summary

The Architecture Analysis and Design Language (AADL) is a SAE standard for modeling both hardware and software architecture of embedded systems. Widely embraced by stakeholders in critical real-time embedded systems, the AADL standard is used to address a large set of concerns including performances (latency, schedulability), safety, and security. The ADEPT workshop aims to present and report on current projects in the field of design, implementation, and verification of critical real-time embedded systems where AADL is a first-citizen technology. This article is a summary of the second edition of the workshop in 2023.

Heterogeneous many-core optimization for Monte Carlo path-tracing on new generation Sunway HPC system

We present swRender, a new parallel rendering pipeline based on the new Sunway many-core architecture (SW26010P) for the Monte Carlo path-tracing algorithm. Previous parallel rendering schemes are unsuitable for our task due to issues such as vast differences in hardware architectures and bottlenecks in I/O communication efficiency. To that end, we create a new two-level parallel tile rendering framework to fully utilize the Sunway computing resources, a practical tile-grouping load-balancing method to maintain the framework’s stability, and a novel many-core acceleration optimization to improve the rendering performance at the pixel level. Our method achieves (1) an average speedup of 16x in multiple benchmarks when compared to the baseline path-tracing model on the Sunway architecture, and (2) an average speedup of 2x when compared to state-of-the-art CPU, co-processor, and GPU-based parallel rendering approaches. Moreover, we scale swRender to run on 15 million cores and obtain high scalable parallel efficiency of 92%.