Elliptic Curve Cryptography Architecture Research Articles

RSD-based high-performance radix-4 Montgomery Modular Multiplication for Elliptic Curve Cryptography

This paper proposes a high-performance radix-4 Montgomery Modular Multiplication (MMM) algorithm and its corresponding hardware architecture for Elliptic Curve Cryptography (ECC), in which the quotient and the partial product accumulation are computed in parallel in each iteration. Additionally, in this MMM, the Redundant Signed Digit (RSD) representation and the Signed Digit Adder (SDA) are used to eliminate the long carry chain and achieve parallel computation, as well as remove pre-computation and integrate modular reduction operations. Our MMM algorithm is implemented in 256-bit and 1024-bit versions on Xilinx Virtex-6 and Virtex-7 FPGAs, respectively. It consumes only 1.55k/10.18k Look-Up Tables (LUTs), takes 133/517 clock cycles, and runs at maximum frequencies of 558.8/641.7 MHz. According to the comparison in terms of Area Time Product (ATP), our design can achieve the ATP of 0.369 over the 256-bit NIST prime domain, which is approximately half of that of the state-of-the-art works. The Scalar Point Multiplication (SPM) scheme using this MMM algorithm consumes 14.19k LUTs and completes a single Scalar Point Multiplication (SPM) operation in 0.217 ms, and it also has a lower ATP than most other SPM algorithms currently in existence.

Secured V2X communication using optimized prime field ECC architecture

The objective of this research is to ensure a high level of security in various forms of vehicular communication (V2V, V2I, and V2N) and to support vehicles in safely receiving all keys and messages from Roadside Unit (RSU), other vehicles, or the network with the support of simple cryptographic techniques. Elliptic Curve Cryptography (ECC) is one of the many cryptographic techniques that offer a desirable response to this requirement. The Koblitz curve secp256k1 is supported by the designed ECC processor for 256-bit point multiplication and point addition. A powerful illustration of the "Divide and Conquer" strategy's ability to accelerate multiplication asymptotically is given by the Karatsuba algorithm. The ECC processor's multiplication operation is accelerated further by the incorporation of pipelining. With a maximum clock frequency of 238.40MHz, the proposed Karatsuba-based ECC processor executes 256-bit single point multiplication in 0.937ms, providing 273.21kbps throughput, and taking up 8.42k slices in a Virtex-7 FPGA. Scalar multiplication is extended by incorporating a pipeline by increasing the highest clock frequency by up to 7.97%, which decreases time consumption by 9.90% and boosts throughput by 10.99%. In terms of area, operating frequency, area-delay product, and throughput, the suggested pipelined Karatsuba multiplier based ECC processor performs better than the existing designs.

Power/Area-Efficient ECC Processor Implementation for Resource-Constrained Devices

The use of resource-constrained devices is rising nowadays, and these devices mostly operate with sensitive data. Consequently, security is a key issue for these devices. In this paper, we propose a compact ECC (elliptic curve cryptography) architecture for resource-constrained devices based on López–Dahab (LD) projective point arithmetic operations on GF(2m). To achieve an efficient area-power hardware ECC implementation, an efficient digit-serial multiplier is developed. The proposed multiplier is built on a Bivariate Polynomial Basis representation and a modified Radix-n Interleaved Multiplication (mRnIM) method (for area and power complexities reduction). Furthermore, the LD-Montgomery point multiplication algorithm is adjusted for accurate scheduling in the compact ECC architecture to eliminate data reliance and improve signal management. Meanwhile, the area complexity is reduced by reuse of resources, and clock gating and asynchronous counter are exploited to reduce the power consumption. Finally, the proposed compact ECC architecture is implemented over GF(2m) (m = 163, 233, 283, 409, and 571) on Xilinx FPGAs’ (Field-Programmable Gate Array) Virtex 5, Virtex 6, and Virtex 7, showing that the efficiency of this design outperforms to date when compared to reported works individually. It utilizes less area and consumes low power. The FPGA results clearly demonstrate that the proposed ECC architecture is appropriate for constraint-resources devices.

A Flexible Architecture for Cryptographic Applications: ECC and PRESENT

This work presents a flexible/unified hardware architecture of Elliptic-curve Cryptography (ECC) and PRESENT for cryptographic applications. The features of the proposed work are (i) computation of only the point multiplication operation of ECC over for a 163-bit key generation, (ii) execution of only the variant of an 80-bit PRESENT block cipher for data encryption & decryption and (iii) execution of point multiplication operation (ECC algorithm) along with the data encryption and decryption (PRESENT algorithm). To establish an area overhead for the flexible design, dedicated hardware architectures of ECC and PRESENT are implemented in the first step, and a sum of their hardware area is computed. Then, the implementation of the proposed flexible architecture for ECC and PRESENT algorithms is presented. Implementation results regarding the area, clock cycles, latency, clock frequency, and power after the place-and-route level on Xilinx Virtex-5, Virtex-6, and Virtex-7 FPGA devices are presented. Hence, the implementation results and comparisons show that the proposed architecture suits applications demanding flexible implementation of cryptographic applications.

A High-Performance ECC Processor Over Curve448 Based on a Novel Variant of the Karatsuba Formula for Asymmetric Digit Multiplier

In this paper, we present a high-performance architecture for elliptic curve cryptography (ECC) over Curve448, which to the best of our knowledge, is the fastest implementation of ECC point multiplication over Curve448 to date. Firstly, we introduce a novel variant of the Karatsuba formula for asymmetric digit multiplier, suitable for typical DSP primitive with asymmetric input. It reduces the number of required DSPs compared to previous work and preserves the performance via full parallelization and pipelining. We then construct a 244-bit pipelined multiplier and interleaved fast reduction algorithm, yielding a total of 12 stages of pipelined modular multiplication with four stages of input delay. Additionally, we present an efficient Montgomery ladder scheduling with no additional register is required. The implementation on the Xilinx 7-series FPGA: Virtex-7, Kintex-7, Artix-7, and Zynq 7020 yields execution times of 0.12, 0.13, 0.24, and 0.24 ms, respectively. It increases the throughput by 242% compared to the best previous work on Zynq 7020 and by 858% compared to the best previous work on Virtex-7. Furthermore, the proposed architecture optimizes nearly 63% efficiency improvement in terms of Area×Time tradeoff. Lastly, we extend our architecture with well-known side-channel protections such as scalar blinding, base-point randomization, and continuous randomization.

Low-Power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT

Elliptic curve cryptography (ECC), one of the asymmetric cryptography, is widely used in practical security applications, especially in the Internet of Things (IoT) applications. This paper presents a low-power reconfigurable architecture for ECC, which is capable of resisting simple power analysis attacks (SPA) and can be configured to support all of point operations and modular operations on 160/192/224/256-bit field orders over GF(p). Point multiplication (PM) is the most complex and time-consuming operation of ECC, while modular multiplication (MM) and modular division (MD) have high computational complexity among modular operations. For decreasing power dissipation and increasing reconfigurable capability, a Reconfigurable Modular Multiplication Algorithm and Reconfigurable Modular Division Algorithm are proposed, and MM and MD are implemented by two adder units. Combining with the optimization of operation scheduling of PM, on 55 nm CMOS ASIC platform, the proposed architecture takes 0.96, 1.37, 1.87, 2.44 ms and consumes 8.29, 11.86, 16.20, 21.13 uJ to perform one PM on 160-bit, 192-bit, 224-bit, 256-bit field orders. It occupies 56.03 k gate area and has a power of 8.66 mW. The implementation results demonstrate that the proposed architecture outperforms the other contemporary designs reported in the literature in terms of area and configurability.

High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA.

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over , which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

Novel fault attack resistant architecture for elliptic curve cryptography

Hardware implementations of cryptosystems are susceptible to fault attacks. By analyzing the side channel information from implementation, the attacker can retrieve the secret information. Generally, in the hardware implementations, validations of results are reported at the end of the computation. If faults are injected at the input side of computation, all the computations performed afterward are wasteful and this is a potential situation which can leak the secret key information using side channel attacks. The current work proposes fault attack resistant implementation of an elliptic curve cryptosystem using a shared point validator unit, zero-one detector, and double coherence check by modified Montgomery Powering Ladder Algorithm. The architecture is robust to fault attacks along with power and area efficiency.

A High-Speed Elliptic Curve Cryptography Processor for Teleoperated Systems Security

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.

ACryp-Proc: Flexible Asymmetric Crypto Processor for Point Multiplication

Flexibility is one of the driving agents for 5G architecture development to incorporate enhanced mobile broad band, machine type communication (MTC), and ultra-reliable MTC. While considering flexibility in the domain of security/reliability, we present a unified and flexible hardware architecture, implementing point multiplication algorithm for both elliptic curve cryptography (ECC) and Binary Huff Curves (BHC). The proposed architecture can be used in the scenarios where the users can tradeoff between the algorithmic execution time and different reliability/security levels. To establish an area overhead for the unified design, dedicated architectures for ECC and BHC over the $GF(2^{m})$ field are implemented in the first step and compared with state-of-the-art. Then, a unified architecture for ECC and BHC is implemented. The performance results of proposed unified architecture illustrate the trade-off between execution time and security level.

High-Speed and Low-Latency ECC Processor Implementation Over GF( $2^{m})$ on FPGA

In this paper, a novel high-speed elliptic curve cryptography (ECC) processor implementation for point multiplication (PM) on field-programmable gate array (FPGA) is proposed. A new segmented pipelined full-precision multiplier is used to reduce the latency, and the Lopez-Dahab Montgomery PM algorithm is modified for careful scheduling to avoid data dependency resulting in a drastic reduction in the number of clock cycles (CCs) required. The proposed ECC architecture has been implemented on Xilinx FPGAs' Virtex4, Virtex5, and Virtex7 families. To the best of our knowledge, our single- and three-multiplier-based designs show the fastest performance to date when compared with reported works individually. Our one-multiplier-based ECC processor also achieves the highest reported speed together with the best reported area-time performance on Virtex4 (5.32 μs at 210 MHz), on Virtex5 (4.91 μs at 228 MHz), and on the more advanced Virtex7 (3.18 μs at 352 MHz). Finally, the proposed three-multiplier-based ECC implementation is the first work reporting the lowest number of CCs and the fastest ECC processor design on FPGA (450 CCs to get 2.83 μs on Virtex7).

Efficient algorithm and architecture for elliptic curve cryptography for extremely constrained secure applications

Recently, considerable research has been performed in cryptography and security to optimize the area, power, timing, and energy needed for the point multiplication operations over binary elliptic curves. In this paper, we propose an efficient implementation of point multiplication on Koblitz curves targeting extremely-constrained, secure applications. We utilize the Gaussian normal basis (GNB) representation of field elements over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) and employ an efficient bit-level GNB multiplier. One advantage of this GNB multiplier is that we are able to reduce the hardware complexity through sharing the addition/accumulation with other field additions. We utilized the special property of normal basis representation and squarings are implemented very efficiently by only rewiring in hardware. We introduce a new technique for point addition in affine coordinate which requires fewer registers. Based on this technique, we propose an extremely small processor architecture for point multiplication. Through application-specific integrated circuit (ASIC) implementations, we evaluate the area, performance, and energy consumption of the proposed crypto-processor. Utilizing two different working frequencies, it is shown that the proposed architecture reaches better results compared to the previous works, making it suitable for extremely-constrained, secure environments.

Achieving Authentication and Integrity using Elliptic Curve Cryptography Architecture

Communication security is one of the areas where research is highly required. The data used in communication is very sensitive and needs to be protected and made abstract from intruders of system. This research is all about securing the messages or data that is being communicated among two parties.The recent branch of Network security is Cryptography using Elliptic Curve Architectures which is based on the arithmetic of elliptic curves and discrete logarithmic problems. ECC schemes are public-key based mechanisms that provide encryption, digital signatures and key exchange algorithms. The best known encryption scheme is the Elliptic Curve Integrated Encryption Scheme (ECIES) which is included in IEEE and also in SECG SEC 1 standards. The key establishment protocol is Elliptic Curve MQV, with implicit certificates and symmetric key cryptographic techniques. The research focuses on achieving secrecy using ECIES algorithm for encryption, and authentication using Hashing technique. The hashed plaintext is again encrypted with RSA. At the receiver end, the hashed text is decrypted first. The hash value of the plaintext decrypted is compared with the latter hash. If they are found equal, the integrity can also be assured. The parameters to considered choosing Elliptic Curves are presented in NIST document of recommended elliptic curves.

Reconfigurable Architecture for Elliptic Curve Cryptography Using FPGA

The high performance of an elliptic curve (EC) crypto system depends efficiently on the arithmetic in the underlying finite field. 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The proposed architecture is based on Lopez-Dahab elliptic curve point multiplication algorithm, which uses Gaussian normal basis for <svg style="vertical-align:-2.3205pt;width:58.950001px;" id="M4" height="18.799999" version="1.1" viewBox="0 0 58.950001 18.799999" width="58.950001" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,15.85)"><use xlink:href="#x47"/></g><g transform="matrix(.017,-0,0,-.017,12.217,15.85)"><use xlink:href="#x46"/></g><g transform="matrix(.017,-0,0,-.017,21.209,15.85)"><use xlink:href="#x28"/></g><g transform="matrix(.017,-0,0,-.017,27.091,15.85)"><use xlink:href="#x32"/></g> <g transform="matrix(.012,-0,0,-.012,35.25,7.688)"><use xlink:href="#x31"/></g><g transform="matrix(.012,-0,0,-.012,40.961,7.688)"><use xlink:href="#x36"/></g><g transform="matrix(.012,-0,0,-.012,46.673,7.688)"><use xlink:href="#x33"/></g> <g transform="matrix(.017,-0,0,-.017,53.012,15.85)"><use xlink:href="#x29"/></g> </svg> field arithmetic. The proposed <svg style="vertical-align:-2.3205pt;width:58.950001px;" id="M5" height="18.725" version="1.1" viewBox="0 0 58.950001 18.725" width="58.950001" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns="http://www.w3.org/2000/svg"> <g transform="matrix(.017,-0,0,-.017,.062,15.775)"><use xlink:href="#x47"/></g><g transform="matrix(.017,-0,0,-.017,12.217,15.775)"><use xlink:href="#x46"/></g><g transform="matrix(.017,-0,0,-.017,21.209,15.775)"><use xlink:href="#x28"/></g><g transform="matrix(.017,-0,0,-.017,27.091,15.775)"><use xlink:href="#x32"/></g> <g transform="matrix(.012,-0,0,-.012,35.25,7.613)"><use xlink:href="#x31"/></g><g transform="matrix(.012,-0,0,-.012,40.961,7.613)"><use xlink:href="#x39"/></g><g transform="matrix(.012,-0,0,-.012,46.673,7.613)"><use xlink:href="#x33"/></g> <g transform="matrix(.017,-0,0,-.017,53.012,15.775)"><use xlink:href="#x29"/></g> </svg> is based on an efficient Montgomery add and double algorithm, also the Karatsuba-Ofman multiplier and Itoh-Tsujii algorithm are used as the inverse component. The hardware design is based on optimized finite state machine (FSM), with a single cycle 193 bits multiplier, field adder, and field squarer. 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The FPGA&#x2019;s dedicated multipliers and carry-chain logic are used to obtain the small data path. The different optimization at the hardware level improves the acceleration of the ECC scalar multiplication, increases frequency and the speed of operation such as key generation, encryption, and decryption. Finally, we have to implement our design using Xilinx XC4VLX200 FPGA device.

High-Performance Architecture for Elliptic Curve Cryptography over Prime Fields on FPGAs

High-Performance Architecture for Elliptic Curve Cryptography over Prime Fields on FPGAs

An area/performance trade-off analysis of a GF(2 m) multiplier architecture for elliptic curve cryptography

A hardware architecture for GF(2 m ) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.

Hardware Elliptic Curve Cryptographic Processor Over&lt;tex&gt;$rm GF(p)$&lt;/tex&gt;

A novel hardware architecture for elliptic curve cryptography (ECC) over <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$ GF(p)$</tex> is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications.

Customizable elliptic curve cryptosystems

This paper presents a method for producing hardware designs for elliptic curve cryptography (ECC) systems over the finite field GF(2/sup m/), using the optimal normal basis for the representation of numbers. Our field multiplier design is based on a parallel architecture containing multiple m-bit serial multipliers; by changing the number of such serial multipliers, designers can obtain implementations with different tradeoffs in speed, size and level of security. A design generator has been developed which can automatically produce a customised ECC hardware design that meets user-defined requirements. To facilitate performance characterization, we have developed a parametric model for estimating the number of cycles for our generic ECC architecture. The resulting hardware implementations are among the fastest reported: for a key size of 270 bits, a point multiplication in a Xilinx XC2V6000 FPGA at 35 MHz can run over 1000 times faster than a software implementation on a Xeon computer at 2.6 GHz.