An area/performance trade-off analysis of a GF(2 m) multiplier architecture for elliptic curve cryptography

Abstract

A hardware architecture for GF(2 m ) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.