Architectural Alternatives Research Articles

Identification of non-functional requirements in textual specifications: A semi-supervised learning approach

Context Early detection of non-functional requirements (NFRs) is crucial in the evaluation of architectural alternatives starting from initial design decisions. The application of supervised text categorization strategies for requirements expressed in natural language has been proposed in several works as a method to help analysts in the detection and classification of NFRs concerning different aspects of software. However, a significant number of pre-categorized requirements are needed to train supervised text classifiers, which implies that analysts have to manually assign categories to numerous requirements before being able of accurately classifying the remaining ones. Objective We propose a semi-supervised text categorization approach for the automatic identification and classification of non-functional requirements. Therefore, a small number of requirements, possibly identified by the requirement team during the elicitation process, enable learning an initial classifier for NFRs, which could successively identify the type of further requirements in an iterative process. The goal of the approach is the integration into a recommender system to assist requirement analysts and software designers in the architectural design process. Method Detection and classification of NFRs is performed using semi-supervised learning techniques. Classification is based on a reduced number of categorized requirements by taking advantage of the knowledge provided by uncategorized ones, as well as certain properties of text. The learning method also exploits feedback from users to enhance classification performance. Results The semi-supervised approach resulted in accuracy rates above 70%, considerably higher than the results obtained with supervised methods using standard collections of documents. Conclusion Empirical evidence showed that semi-supervision requires less human effort in labeling requirements than fully supervised methods, and can be further improved based on feedback provided by analysts. Our approach outperforms previous supervised classification proposals and can be further enhanced by exploiting feedback provided by analysts.

Resource aware mapping on coarse grained reconfigurable arrays

Coarse grain reconfigurable array architectures have become increasingly popular due to their flexibility, scalability and performance. However, the mapping of programs on these architectures is characterized by huge complexity. This work presents a new mapping methodology for effectively mapping applications on coarse grained reconfigurable arrays. The core of this methodology comprises of the scheduling and register allocation phases performed, for the first time in the case of CGRAs, in a single step. Additionally, modulo scheduling with backtracking capability is incorporated in this scheme. The main contribution of this work includes a novel technique for minimizing the memory bandwidth bottleneck, a new priority scheme and a new set of heuristics which target on the maximization of the Instruction Level Parallelism by efficiently managing the architecture’s resources. The overall approach is retargetable with respect to a parametric architecture template modelling a large number of architecture alternatives and it has been automated with a prototype tool which permits experimental exploration. The experimental results showed that the achieved performance figures are very close to the most effective ones derived from the theoretical study on the architecture’s resources and the applications requirements. Moreover, the application of the bandwidth optimization technique lead to a 20–130% increase on operation parallelism. Finally, the experiments quantified the benefit from applying the new priority scheme and heuristics.

IPTV transport architecture alternatives and economic considerations

Telecommunications companies are under increased pressure due to competition from multiple system operators, and the changing communications and entertainment needs of residential consumers. These pressures are driving the telecommunications companies to design and deploy metro networks capable of delivering broadcast video and VOD services through IP-based broadband connectivity (known as IPTV). One important architectural consideration for these IPTV networks is the core layer 1 transport infrastructure that supports economical delivery of these high-bandwidth services. This article surveys some of the major layer 1 optical transport network alternatives including DWDM, SONET, and Ethernet-on-fiber as well as its passive WDM/DWDM (PWDM) variation. The article analyzes the architectural and cost performance metrics for these transport options, and explores the economic crossover points with regard to the key network and service parameters such as bandwidth demand, number of subscribers, network topology, and operational constraints. DWDM technology, when coupled with native Ethernet aggregation, is found to have significant applicability for IPTV transport networks. DWDM offers value in capital cost and operations, while delivering the required bandwidth and performance. Ethernet aggregation capability within the transport infrastructure adds scalability, flexibility, and cost advantage for the multiservice network applications of the future.

Editorial: Special Section on CMP Architectures

CHIP multiprocessor (CMP) architectures are formed when multiple compute cores are integrated onto the same chip, forming a single, powerful, computational entity. Nearly every major high-performance processor manufacturer has at least two cores (dual-core) on the die, and their roadmaps are increasingly multicore, signaling that the era of big, monolithic uniprocessors has ended. This results from the fact that ever-larger uniprocessors do not scale well in power/performance, area/performance, or design complexity/performance. Continued performance scaling of these processors will thus be focused primarily on increasing multithreaded throughput. The rapid adoption of small-scale CMP platforms and the quest for high performance continues to accelerate the rate at which processor manufacturers are considering adding more cores on the die. Over the last decade, there has been significant progress in research and development in both academia and industry on CMP architecture and design for client and server platforms. And, while we have successfully entered the era of CMP, there are a significant set of challenges and opportunities that are yet to be investigated deeply. Some of the broad research areas being investigated include CMP architecture alternatives (for core, cache, interconnect, and memory), CMP design and technologies (process implications, new technologies like 3D-stacking, voltage/clock domain management, etc.), CMP performance evaluation (new simulation and modeling techniques, emerging applications and execution environments like virtualization), and novel CMP architectures and use cases (asymmetric or heterogeneous architectures, accelerators, etc.). There are many questions that are still to be answered for CMP architectures. Below, we list a few of the most compelling ones.

IP MULTIMEDIA SUBSYSTEMS - Mobility Testbed for 3GPP2-Based Multimedia Domain Networks

Wireless service providers strive to preserve the quality of service and user experience for mobile users. Several standards bodies are defining architectures that can be used as a platform to provide secure and seamless services to these mobile users. These architectures aim to provide several required functions such as signaling, configuration, security association, encryption, and billing. However, the placement of several functional components and their interaction at several layers contributes to the operational complexity and thus affects the optimal results. Testbed realization of any standardized architecture can help investigate the underlying networking issues. In this article, we describe a mobility test bed implementation based on one of the architecture alternatives of 3GPP2, where the outbound signaling servers are distributed around the edges of the network. We experiment with three different hand-off techniques and analyze the associated experimental results. Analysis of these experimental results and experiences obtained from the testbed implementation can be helpful to any service provider that plans to deploy a version of the MMD (multimedia domain) architecture with distributed signaling servers.

Architectural Alternatives for Information Filtering in Structured Overlays

Content providers are naturally distributed and produce large amounts of new information every day. Peer-to-peer information filtering is a promising approach that offers scalability, adaptivity to high dynamics, and failure resilience. The authors developed two approaches that utilize the chord distributed hash table as the routing substrate, but one stresses retrieval effectiveness, whereas the other relaxes recall guarantees to achieve lower message traffic and thus better scalability. This article highlights the two approaches' main characteristics, presents the issues and trade-offs involved in their design, and compares them in terms of scalability, efficiency, and filtering effectiveness.

Architectures reconfigurable et faible consommation. Réalité ou prospective ?

Reconfigurable computing is a new architectural alternative during design and application implementation process. Rapid advance in technology nowadays allow the design of reconfigurable components supporting complex industrial applications. Thanks to their flexibility, these architectures have a real potential to optimize electrical consumption. Even if power consumption is a new constraint in the reconfigurable architecture design framework, it is integrated at every level in the design flow. In this paper we discuss about the reconfigurable architecytures opportunities, and first results, in the low power consumption field. We also discuss about the way in which the energy efficiency of such architectures may further be improved.

A Cross-Layer Analysis of Session Setup Delay in IP Multimedia Subsystem (IMS) With EV-DO Wireless Transmission

This paper analyzes the session setup delay in the IP multimedia subsystem (IMS) with the CDMA2000 evolution data only rev. A (EV-DO rev. A) standard for wireless transmission. Session setup delay is particularly critical for interactive multimedia applications, such as gaming, push-to-X and voice over IP (VoIP), as it directly translates in user perception of service quality. Keeping signaling delay low, however, is a challenge in IMS due to the text-based nature of the session initiation protocol (SIP) for signaling, and, more significantly, due to the lossy and capacity constrained wireless links. To address this challenge, we analyze the session setup delay end-to-end, by taking into account key system properties across all layers, ranging from radio links to IMS signaling architecture. We present a model for cross-layer performance analysis and simulation, which includes the statistical properties of the EV-DO (rev. A) wireless channel, and also takes into consideration the properties of transport protocols (TCP, UDP) and SIP signaling (message size and compression). By means of analysis and simulations, we study the setup delay performance of a generic, multi-operator IMS communication scenario between two mobile users. We describe how session setup delay can be estimated and reduced in realistic IMS settings and we propose architecture alternatives to the basic IMS scenario. The results derived from this study show that the proposed methods can incrementally lead to a lower setup delay and less sensitivity to the radio transmission quality and frame error rate compared to the base IMS scenario

Gap Analysis and Deployment Architectures for 3GPP2 MMD Networks

Mobile and fixed operators are offering broadband access to the Internet by either adding wireless access to their existing core networks (e.g., CDMA IxEVDO. GPRS, and WiFi) or continuing to evolve existing broadband infrastructures (e.g., DSL, Cable and FTTx). Consequently, IMS and MMD architectures as defined by 3GPP and 3GPP2 are becoming increasingly important to network operators, in particular, for offering ubiquitous service and seamless mobility to end users, along with management and control Although 3GPP2 MMD architecture has adopted most of the 3GPP IMS core functionalities and interfaces, it added several other unique functional components and interfaces to fit the specific need of CDMA2000 access networks Therefore, it is important to understand the gaps and issues associated with the 3GPP2 MMD architecture with regard to the 3GPP IMS architecture. In this paper, we first analyze the functional and protocol level differences between IMS and MMD architectures. Based on our analysis, we then articulate several deployment architectural alternatives for 3GPP2 MMD networks and finally analyze the pros and cons of each architecture.

SEAS ISR Architect: Mapping Department of Defense Architecture Views to Military Outcome

The SEAS ISR Architect maps Department of Defense Architecture Framework (DoDAF) views to military outcome and demonstrates a quick turnaround tool for the Initial Capabilities Document (ICD) phase of the Joint Capabilities Integration and Development System (JCIDS) process. The SEAS ISR Architect allows the user to reconfigure intelligence, surveillance, and reconnaissance (ISR) architectures within the DoD Architecture Framework, to parameterize a Systems Effectiveness and Analysis Simulation (SEAS) with a pre-loaded scenario and present a comparison of the warfighting effectiveness of a range of architectural alternatives based on multiple simultaneous theater simulations.

A tutorial on decomposition methods for network utility maximization

A systematic understanding of the decomposability structures in network utility maximization is key to both resource allocation and functionality allocation. It helps us obtain the most appropriate distributed algorithm for a given network resource allocation problem, and quantifies the comparison across architectural alternatives of modularized network design. Decomposition theory naturally provides the mathematical language to build an analytic foundation for the design of modularized and distributed control of networks. In this tutorial paper, we first review the basics of convexity, Lagrange duality, distributed subgradient method, Jacobi and Gauss-Seidel iterations, and implication of different time scales of variable updates. Then, we introduce primal, dual, indirect, partial, and hierarchical decompositions, focusing on network utility maximization problem formulations and the meanings of primal and dual decompositions in terms of network architectures. Finally, we present recent examples on: systematic search for alternative decompositions; decoupling techniques for coupled objective functions; and decoupling techniques for coupled constraint sets that are not readily decomposable.

Cost Models with Explicit Uncertainties for Electronic Architecture Trade‐off and Risk Analysis

AbstractThis paper discusses how the early phases of developing embedded electronic systems can be improved by enhanced modelling of cost and performance that includes explicit handling of uncertainties. The approach is to add cost information to existing UML models, capture uncertainties using probability distributions, and use Monte Carlo simulation to analyze the risk of not reaching the cost targets. It is demonstrated how the information obtained can be used when evaluating different architecture alternatives, while including both development and product cost as well as risk in the trade‐off.

An Integrated Systems Architecture to Provide Maritime Domain Protection

The focus of this research is to address the criticality and vulnerability of commercial shipping in the Straits of Mallacca by designing and evaluating competing systems architectures that could provide sufficient maritime domain protection. The category of primary concern was the introduction of a weapon of mass destruction (WMD) in a cargo container. The Maritime Domain Protection (MDP) physical architecture alternatives combined five separate systems: 1) a land-based cargo inspection system, 2) a sensor system, 3) a C3I (command and control, communications, and intelligence) system, 4) a force response system, and 5) a sea-based cargo inspection system. Individual models for each system were developed and combined into an overarching integrated architecture model to evaluate overall performance. Study results based on current technology showed that while solutions were found to effectively reduce risk in the WMD threat scenario, effective suppression came at great expense and included the participation of commercial shipping companies. A range of alternative cost-effective solutions were also found, but with limited performance. Future work involves using the developed architecture as a test bed for evaluating the overall impact and effectiveness of new technologies and research (such as “smart containers”) on MDP and homeland security.

Improving aggregated channel performance through decentralized channel monitoring

Aggregating low-speed WAN links into a higher-speed logical link promises to improve data-transfer rates to collaborating communities of wireless mobile multihomed devices. Such bandwidth aggregation systems must adapt to link dynamics as the number of links and the channel conditions vary with time due to mobility, power dissipation, and channel interference. A monitoring architecture that accurately measures the link dynamics and promptly feeds this information to the system is vital to realize significant bandwidth aggregation performance gains. In this paper we present various architectural design alternatives for such a monitoring system, and evaluate them using both analysis and simulation. We show that a properly-designed monitoring system can accurately measure and quickly respond to changes in communication link performance while minimizing the control overhead.

Skiing the embedded systems mountain

UCLA teaches students how to master the steep slopes of the embedded systems mountain. The EE201A graduate course connects high-level design specification to embedded implementation. There is a long-standing and wide culture gap between system designers that create those abstract specifications and the system architects that need to implement them. In industry, the culture gap has separated software from hardware teams, and platform creators from platform users. In an embedded context, where these are very tightly connected, this leads to large inefficiencies both in design time and design results. Our course takes students to both sides of the gap and lets them look at this problem from different perspectives. For a given application, it teaches how to select target architectures, tools, and design methods. The course covers a stepwise systematic design process. It includes specification, transformation, and refinement of an application. Specifications enable systematic and structured expression of an application. Transformations rework specifications into ones that are a better match for a given target architecture. Refinements lower the abstraction level toward the target architecture. The embedded systems mountain is traversed in two directions. A vertical refinement axis covers elements such as power-memory-reduction methods or fixed-point refinement. A horizontal exploration axis covers various architecture alternatives including application-specific integrated circuits (ASIC), domain-specific processors, digital signal processors (DSP), embedded cores, programmable processors, and system-on-chip (SOC). During the course, the students also go through an extensive design project to apply the methods learned in this course. A typical embedded application is used to drive the project. In this paper it is illustrated using an embedded version of an image encoder, more specifically a JPEG encoder. Several commercial tools, design environments, and platforms have been used as alternative implementation targets for this application.

HyPE: hybrid power estimation for IP-based systems-on-chip

In this paper, we present a novel power estimation scheme for programmable systems consisting of predesigned datapath and memory components. The proposed hybrid methodology yields highly accurate estimates within short runtimes by combining high-level simulation with analytical macromodeling of circuit characteristics. The kernel of our methodology is a simulation-free power estimation scheme for memoryless datapaths comprising several IP blocks connected in fixed topologies. The outer shell of our hybrid scheme is a functional simulation, which is performed only on the interfaces between memoryless components and memory blocks. This simulation accurately captures the control signals that affect the flow of data and, consequently, the utilization and power dissipation of hardware. Experimental results validate the accuracy and efficiency of our methodology. We applied our static power estimation kernel to signal processing and data encryption datapaths. For designs of up to 576 IP blocks, the average error of our power estimates is 7.3% in comparison with switch-level simulation results. We implemented our hybrid scheme into a power estimation tool, called HYPE, and used it to explore various architectural alternatives in the design of a 256-state Viterbi decoder and a Rijndael encryptor. For designs with about 1 million transistors, our estimator terminates within seconds. Compared with commercial state-of-the-art gate-level power estimators, our proposed methodology is up to 1000 times faster with 5.4% deviation on average.

Tool support for optimization-based architectural evaluation

Architecting enterprise applications is a complex design activity. This is especially true when considering the myriad of interdependent architectural decisions with an arbitrary number of alternatives that can be employed at each decision point. Further complexities stem from the fact that different alternatives often vary considerably in their support for different quality attributes. Existing software architecture evaluation approaches and tools lack the explicit consideration of design decision interdependencies, as they primarily focus on one decision in isolation. For this purpose, we have earlier developed the ArchDesigner approach to help determining the optimal mix of architectural alternatives. This paper discusses an architectural evaluation support tool that implements the ArchDesigner approach. The novelty of this tool is in its support for evaluating combinations of alternatives against one other, and not only alternatives belonging to one decision. It treats the architectural evaluation problem as a search problem and leverages optimization techniques for evaluating candidate application architectures.

From scenarios to aspects

Software product lines are gaining importance because they allow improvements in time to market, cost, productivity and quality of software products. Architecture evaluation is one important aspect in the development of product lines for large-scale distributed systems. It is desirable to evaluate and compare architectures for functionality and quality attributes before implementing or changing the whole system. Often, the effort required for the thorough evaluation of alternatives using prototypes is prohibitive. In this paper, we present an approach for cost-efficient software architecture evaluation, based on scenario-oriented software specifications, modeling the system services. We show how to map the same set of services to several possible target architectures and give a procedure to generate evaluation prototypes using aspect-oriented programming techniques. This significantly reduces the effort required to explore architectural alternatives. We explain our approach using the Center TRACON Automation System as an example.

Ad hoc peer-to-peer network architecture for vehicle safety communications

This article addresses the design of an architecture for ad hoc peer-to-peer networking of neighboring vehicles to help achieve near-instantaneous communication for safety applications such as collision avoidance warnings. We propose a local peer group (LPG) architecture to organize neighboring vehicles that have frequently changing neighbors and have no inherent relationships with one another. We study two architectural alternatives for LPG in this article, and consider areas of improvement for ad hoc vehicle networking protocols to support safety communications including multihop throughput, connection setup time, and configuration.

Current Trends in Wireless Sensor Network Design

The self-organizing nature of sensor networks, their autonomous operation and potential architectural alternatives make them suitable for different data-centric applications. Their wider acceptance seems to be rising on the horizon. In this article, we present an overview of the current state of the art in the field of wireless sensor networks. We also present various open research issues and provide an insight about the latest developments that need to be explored in greater depth that could possibly make this emerging technological area more useful than ever.