Architectural Techniques Research Articles

Cache Design with Domain Wall Memory

Domain wall memory (DWM) is a recently developed spin-based memory technology in which several bits of data are densely packed into the domains of a ferromagnetic wire. DWM has shown great promise in enabling non-volatile memory with very high density and energy efficiency, and has been explored for secondary storage and off-chip memory. In this work, we explore the use of DWM within the on-chip cache hierarchy of general purpose computing platforms. Our work is motivated by the fact that DWMs enable much higher density compared to SRAM, DRAM, and other spin-based memory technologies such as STT-MRAM. However, DWMs also pose the unique challenge of serial access to the bits stored in a cell, leading to large and variable access latencies. In addition, DWMs share the inherent write inefficiency of other spin-based memories. We propose TapeCache, a DWM-based cache design that employs device, circuit, and architectural techniques to address these challenges. At the device level, we perform write optimization by employing a new write mechanism based on domain wall shifts to achieve fast, energy-efficient writes in DWM. At the circuit level, we propose different DWM bit-cell designs that are tailored to the distinct architectural requirements of different levels in the cache hierarchy. At the architecture level, we propose a new cache organization and suitable management policies that mitigate the performance penalty arising from serial access to bits in a DWM cell. We show that the holistic device-circuit-architecture co-design enables all the levels in the cache hierarchy to be realized using DWM and benefit from its improved density. Over a wide range of SPEC CPU 2006 benchmarks, TapeCache achieves an average energy improvement of 7.5 $\times$ , with virtually identical performance and 7.8 $\times$ improvement in area, compared to an iso-capacity SRAM cache. Compared to an iso-capacity STT-MRAM cache, TapeCache obtains 3.1 $\times$ improvement in area and 2 $\times$ average energy savings along with 1.1 percent performance improvement.

Tensile strength of compacted rammed earth materials

A rammed earth technique is a traditional architectural technique to build soil structures by compacting geo-materials in a form. In this study, tensile strength properties of rammed earth materials and effects of test conditions are evaluated by conducting direct tension tests and splitting tests on several specimens. It is inferred from the result of these test that the direct tension test should be used to evaluate tensile strength of a layer interface, while the splitting test might evaluate the strength related to the tensile strength inside a compaction layer. When rammed earth structures are constructed, the results from the experiments indicate that it is important to scarify interfaces during compaction in order to prevent reduction and variation of the tensile strength of the layer interfaces. The tensile strength of the rammed earth specimens made of compacted soils without lime increased with the decrease in their water contents. The tensile strengths of the specimens represent 5.0–12.5% of corresponding values of unconfined compression strength at the same water content range. The tensile strength of rammed earth specimens made of lime-mixed soil was in the range of 15–20% of the corresponding unconfined compression strength at 28 days curing. In the series of cyclic tensile loading test, no significant reduction of tensile strengths was observed even after undergoing the cyclic loading history.

Recent Architectural Developments for Reducing Power Consumption and Increasing Performance

Background: Power consumption has become one of the most serious obstacles ahead of performance increase. Due to increased power consumption, increasing number of transistors does not seem to be viable anymore. We are being forced to consider other ways of increasing performance without increasing power consumption. To fınd solution to the problem, the power consumption issue is being looked at more and more carefully at architectural level. Methods: Recent publications and patent databases are reviewed to find extraordinary and innovative architectural techniques developed for reducing power consumption and increasing performance. Results: In most of the cases the focus was specifically on memory area because of the studies that indicated that memory is the biggest power consumer in a typical processor system. The focus of the most methods was also on the cache memory part of the processor system since cache memory is a part that is used with every instruction execution. Any reduction in power cost of the cache memory results in sizable power reduction. Among the methods suggested were techniques of linking cache memory cells to reduce number of operations, reducing size of the cache memory by using multiple small cache memories activated one at a time. Conclusion: Based on the study it can be concluded that future innovative developments to reduce power consumption should concentrate on: a) Main memory part: to reduce the power consumption of main memory by turning on/off unused blocks of memory without effecting performance, b) Cache memory part: use of cache memory efficiently without decreasing performance, c) Efficient multiprocessing architectures. By integrating above mentioned methods to multiprocessors it may be possible to reduce the power consumption further. Keywords: Instruction Set Architecture (ISA), power, Register File (RF), Register lock, multiprocessing, linked cache, one bit tagged cache, code compression, shared resources.

Toward a Better Understanding of Deep Neural Network Based Acoustic Modelling: An Empirical Investigation

Recently, deep neural networks (DNNs) have outperformed traditional acoustic models on a variety of speech recognition benchmarks.However, due to system differences across research groups, although a tremendous breadth and depth of related work has been established, it is still not easy to assess the performance improvements of a particular architectural variant from examining the literature when building DNN acoustic models. Our work aims to uncover which variations among baseline systems are most relevant for automatic speech recognition (ASR) performance via a series of systematic tests on the limits of the major architectural choices.By holding all the other components fixed, we are able to explore the design and training decisions without being confounded by the other influencing factors. Our experiment results suggest that a relatively simple DNN architecture and optimization technique produces strong results.These findings, along with previous work, not only help build a better understanding towards why DNN acoustic models perform well or how they might be improved, but also help establish a set of best practices for new speech corpora and language understanding task variants.

VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache

In this paper, we investigate the feasibility of voltage adjustment in a large capacity cache, and propose the architecture of voltage-adaptable nonuniform cache access (VANUCA) that exploits near-threshold computing and multivoltage domain to approach the limit of $V_{\rm dd}$ in a low-power cache. However, the adoption of near-threshold voltage (NTV) leads to a rocketing error probability in SRAM arrays, which has to be addressed by effective fault-tolerant techniques. Instead of using error correction code or data duplication, the VANUCA exploits the natural data redundancy across the whole memory hierarchy to enable fast fault recovery in the NTV cache. Based on the discovered data resilience and the multi- $V_{\rm dd}$ architecture, the VANUCA is able to match vulnerable/invulnerable data clusters to available high-/low-voltage domains by utilizing the data migration mechanism in dynamic NUCA. The proposed VANUCA includes two important architectural techniques: 1) static assignment that assumes a fixed voltage domain partitioning and 2) DataMotion that dynamically fits the working set into heterogeneous cache banks through $V_{\rm dd}$ switching. Experimental results show that the VANUCA achieves considerable improvements in energy efficiency over the conventional single-voltage domain NUCA cache.

A Survey of Architectural Techniques for Managing Process Variation

Process variation—deviation in parameters from their nominal specifications—threatens to slow down and even pause technological scaling, and mitigation of it is the way to continue the benefits of chip miniaturization. In this article, we present a survey of architectural techniques for managing process variation (PV) in modern processors. We also classify these techniques based on several important parameters to bring out their similarities and differences. The aim of this article is to provide insights to researchers into the state of the art in PV management techniques and motivate them to further improve these techniques for designing PV-resilient processors of tomorrow.

Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions

In this article, we investigate the application of different techniques for mitigating the impact of process variations on the custom functional unit (CFU) of extensible processors. The techniques include using extra cycles for the CFU and extending the clock period for the extensible processor. The former technique is based on providing an extra clock cycle to those custom instructions (CIs) that have timing yields smaller than one. For this purpose, we make use of a lookup table (LUT) for each fabricated processor. Based on a post-fabrication analysis, the need for an extra clock cycle for some CIs is determined. Consequently, the CI timing violations are prevented, and all manufactured extensible processors will work with a predefined clock cycle time. To study the effect of the objective function (used during the CI selection phase) on the efficacy of the suggested architectural technique, we investigate three different objective functions. In the second technique, the clock period extension is used to guarantee a design yield of one. Our results demonstrate that combining both techniques helps increase the speedup achieved by the extensible processor. To assess the efficacies of the proposed methods, several benchmarks from different application domains are used. Results of the study reveal that the suggested techniques provide considerable improvements in the speedups of the extensible processors when compared to those of approaches that do not consider the impact of process variations.

Rambus: A Puzzle to Solve

Anyone who has spent any time with Mark knows that he loves puzzles. His office at Stanford is full of puzzles: some he built himself, some crafted from beautiful hardwood, and some simple children?s toys. Each of them has their own aesthetic and their unique attraction to Mark. So, in many ways, it's no surprise that what attracted him to cofounding Rambus back in 1990 was a puzzle posed by Rambus cofounder Mike Farmwald: could they, using circuit and architecture techniques, increase the bandwidth of the dynamic random access memory (DRAM) interface tenfold without changing process technology?

Mark Horowitz's Link to Chip-to-Chip Communication: His Significant and Fundamental Contributions

Prof. Mark Horowitz has been focusing on how to enhance the performance of integrated circuits (ICs) and digital systems for over 30 years. In the late 1980s and early 1990s, he was among the pioneers who recognized the impact of technology scaling on a single-chip microprocessor and focused his research on architectural techniques, which was previously only possible on large expensive mainframes. His work on projects such as Mips-X [3], Torch, Dash [11], and flash [10] led to advancements in many areas including compilers, computer-aided design development, memories, high-speed logic, clocking, and mixed-signal design [12]. One such area of research is high-speed integrated input–output (I/O) interfaces and serialization/deserialization (SerDes).

Treatises and <i>Ars construendi</i>: Teaching’s Method Theory and Practice of Critical History’s Application Based on Teacher-Student Relationships

The topic of this lecture is the results’ description obtained during many years of teaching. We shall illustrate how students use the same analytical techniques to study two different aspects: 1) Architectural Treatises are first studied separately and then in a comparative way. The purpose of this graphic analysis is to reach a new interpretation of them through the realization of original graphics; 2) The Roman Ars construendi: architectural techniques and buildings’ typologies used by the Romans are investigated in the archaeological sites, where the reading of buildings’ stratification in different historical periods becomes an important teaching tool.

The Necessity of Revitalizing the Traditional Elements Effective on Economic Sustainability and Cost Management (Case Study of Tabatabai's House)

Abstract The application of sustainable development and value engineering concepts in the architecture opens a new discussion called economic sustainability, ecologic architecture, green architecture, and environment architecture; all of which refer to the same concept of environment-friendly architecture. Lack of attention to the foundations for sustainability of traditional architecture of Iran and the diverse factors affecting it has charged us a worn and unstable urban fabric. In this world, along with other scientists the architects have been looking for the new ways to reduce costs and maintain energy as a sensitive duty of them. Regarding the ideas and various theories of scholars on the sustainable development, the main points of focus are: 1. Design for human; 2. Resource saving and economic justification; 3. Renewable materials and resources, and recyclables. The present study is intended to investigate the effective factors in moving toward sustainable development and examines the economic justification of vernacular architecture. Hence, by a review of the references and library documents, it conducts an analysis of Tabatabai's house which is a sample of the traditional architecture of Iran and an appropriate pattern showing the techniques of urban architecture. At the end, some strategies will be provided in line with sustainable development and energy preservation.

Improve Diversity with OFDM Technique in V-BLAST Architecture

There are several technologies to transmit any signal in wireless communication. Technologies are: Integration, Differentiation, TDM (Time Division Multiplexing), FDM (Frequency Division Multiplexing), OFDM (Orthogonal Frequency Division Multiplexing). In which OFDM is superior to any other technology. It is widely used in MIMO schemes also where multiple transmission and reception process done with different types of antennas.V-BLAST is the technique where the completion of strongest signal capturing and it gives sturdiest output with the help of different receiver approximation techniques like MMSE (Minimum Mean Square Error), ZF (Zero Forcing) and ML (Maximum Likelihood). In this paper we throw some light on why choose MMSE, ZF and ML to identify overall Throughput, adjustment in pre-coding, performance of FFT (Fast Fourier Transform) and IFFT (Inverse FFT) in OFDM-VBLAST. Also examine which receiver technique is widely and very useful in practical scenario.

A Survey of Architectural Techniques for Near-Threshold Computing

Energy efficiency has now become the primary obstacle in scaling the performance of all classes of computing systems. Low-voltage computing, specifically, near-threshold voltage computing (NTC), which involves operating the transistor very close to and yet above its threshold voltage, holds the promise of providing many-fold improvement in energy efficiency. However, use of NTC also presents several challenges such as increased parametric variation, failure rate, and performance loss. This article surveys several recent techniques that aim to offset these challenges for fully leveraging the potential of NTC. By classifying these techniques along several dimensions, we also highlight their similarities and differences. It is hoped that this article will provide insights into state-of-the-art NTC techniques to researchers and system designers and inspire further research in this field.

Proportional Systems in Late-Modern Architecture: the Case of Alejandro de la Sota

The aim of this paper is the analysis, in terms of proportional systems, of a number of buildings designed by the Spanish architect Alejandro de la Sota, whose work is characterized in general by a particularly clever and unconventional use of different dimensional and proportional systems, and can therefore be regarded as a significant perspective in the understanding of the design strategies in Modern architecture. Beyond the well-documented use of modules and grids in his work, these analyses try to show the presence of proportional systems based on the Golden Mean in some of this architect’s designs. These analyses lead also to a discussion on the nature of proportioning techniques in architecture, their relationship to analogous structures in musical composition, and the necessary compromises between the ideal proportions and the reality of construction, something inherent to the very nature of the architectural object.

Exploiting Instruction Set Encoding for Aging-Aware Microprocessor Design

Microprocessors fabricated at nanoscale nodes are exposed to accelerated transistor aging due to bias temperature instability and hot carrier injection. As a result, device delays increase over time, reducing the mean time to failure (MTTF) and hence lifetime of the processor. To address this challenge, many (micro)-architectural techniques target the execution stage of the instruction pipeline, as this one is typically most critical. However, also the decoding stages can become aging critical and limit the microprocessor lifetime, as we will show in this work. Therefore, we propose a novel aging-aware instruction set-encoding methodology (ArISE) that improves the instruction encoding iteratively using a heuristic algorithm. In addition, the switching activities of the affected memory elements are considered in order to co-optimize lifetime and energy efficiency. Our experimental results show that MTTF of the decoding stages can be improved by 2.3× with negligible implementation costs.

An Efficient List Decoder Architecture for Polar Codes

Long polar codes can achieve the symmetric capacity of arbitrary binary-input discrete memoryless channels under a low complexity successive cancelation (SC) decoding algorithm. However, for polar codes with short and moderate code length, the decoding performance of the SC algorithm is inferior. The cyclic redundancy check (CRC) aided successive cancelation list (SCL) decoding algorithm has better error performance than the SC algorithm for short or moderate polar codes. In this paper, we propose an efficient list decoder architecture for the CRC aided SCL algorithm, based on both algorithmic reformulations and architectural techniques. In particular, an area efficient message memory architecture is proposed to reduce the area of the proposed decoder architecture. An efficient path pruning unit suitable for large list size is also proposed. For a polar code of length 1024 and rate $\frac{1}{2}$, when list size $L=2$ and 4, the proposed list decoder architecture is implemented under a TSMC 90nm CMOS technology. Compared with the list decoders in the literature, our decoder achieves 1.33 to 1.96 times hardware efficiency.

Making climate change visible: A critical role for landscape professionals

The central message of this essay is to make climate change more visible and meaningful to community members through landscape architectural techniques and building literacy. It identifies general principles for opening people's eyes to climate change, demonstrating the potentially powerful role that landscape can play in helping citizens to see and foresee climate change in their own backyards, where they care the most.In this context, the author emphasizes the value of local landscape & place-based experience, as well as the importance of designing visible solutions. The essay describes two linked frameworks that address respectively the possibility of seeing and recognizing climate change, and the need to consider not only climate change impacts but also its causes, mitigation and adaptation solutions. Landscape architects and landscape planners can play an integrative, educational & visionary role in creative design and engagement of communities on climate change. The essay offers four pathways for landscape professionals to integrate & enhance public engagement and literacy on climate change, through: applying landscape messaging to make climate change more visible on the ground; using compelling visual tools that reveal signs of climate change in local landscapes and depict resilient, low-carbon futures; local climate change visioning processes to help communities understand the implications for communities; and helping neighbours to self-educate and mobilize for local climate change action. Better training and a professionally endorsed code of ethics for visual media are needed to support this vital work.

Lifetime Reliability Enhancement of Microprocessors

Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however, makes NBTI the most serious threat to chip lifetime reliability in today's and future process technologies. The delay of microprocessors gradually increases as time goes by, due to stress and recovery phases. The delay eventually becomes higher than the value required to meet design constraints, which results in failed systems. In this article, the mechanism of NBTI and its effects on lifetime reliability are presented, then various techniques to mitigate NBTI degradation on microprocessors are introduced. The mitigation can be addressed at either the circuit level or architectural level. Circuit-level techniques include design-time techniques such as transistor sizing and NBTI-aware synthesis. Forward body biasing, and adaptive voltage scaling are adaptive techniques that can mitigate NBTI degradation at the circuit level by controlling the threshold voltage or supply voltage to hide the lengthened delay caused by NBTI degradation. Reliability has been regarded as something to be addressed by chip manufacturers. However, there are recent attempts to bring lifetime reliability problems to the architectural level. Architectural techniques can reduce the cost added by circuit-level techniques, which are based on the worst-case degradation estimation. Traditional low-power and thermal management techniques can be successfully extended to deal with reliability problems since aging is dependent on power consumption and temperature. Self-repair is another option to enhance the lifetime of microprocessors using either core-level or lower-level redundancy. With a growing thermal crisis and constant scaling, lifetime reliability requires more intensive research in conjunction with other design issues.

Fast detecting Hot-IPs in high speed networks

Hot-IPs, hosts appear with high frequency in networks, cause many threats for systems such as denial of service attacks or Internet worms. One of their main characteristics is quickly sending a large number of packets to victims in a short time in network. This paper presents a solution to find Hot-IPs by using non-adaptive group testing approach. The proposed solution has been implemented in combination with the distributed architecture and parallel processing techniques to quickly detect Hot-IPs in ISP networks. Experimental results can be applied to detect Hot-IPs in ISP networks.

A Review and Taxonomy of Choice Architecture Techniques

AbstractWe present a taxonomy of choice architecture techniques that focus on intervention design, as opposed to the underlying cognitive processes that make an intervention work. We argue that this distinction will facilitate further empirical testing and will assist practitioners in designing interventions. The framework is inductively derived from empirically tested examples of choice architecture and consists of nine techniques targeting decision information, decision structure, and decision assistance. An inter‐rater reliability test demonstrates that these techniques can be used in an intersubjectively replicable way to describe sample choice architectures. We conclude by discussing limitations of the framework and key issues concerning the use of the techniques in the development of new choice architectures. Copyright © 2015 John Wiley & Sons, Ltd.