Arbiter Physical Unclonable Function Research Articles

A Hardware Security Protection Method for Conditional Branches of Embedded Systems.

The branch prediction units (BPUs) generally have security vulnerabilities, which can be used by attackers to tamper with the branches, and the existing protection methods cannot defend against these attacks. Therefore, this article proposes a hardware security protection method for conditional branches of embedded systems. This method calculates the number of branch target buffer (BTB) updates every 80 clock cycles. If the number exceeds the set threshold, the BTB will be locked and prevent any process from tampering with the BTB entries, thereby resisting branch prediction analysis (BPA) attacks. Moreover, to prevent attackers from stealing the critical information of branches, the method designs the hybrid arbiter physical unclonable function (APUF) circuit to encrypt and decrypt the directions, addresses, and indexes of branches. This circuit combines the advantages of double APUF and Feed-Forward APUF, which can enhance the randomness of output response and resist machine learning attacks. If attackers still successfully tamper with the branches and disrupt the control flow integrity (CFI), this method detects tampering with the instruction codes, jump addresses, and jump directions in a timely manner through dynamic and static label comparison. The proposed method is implemented and tested on FPGA. The experimental results show that this method can achieve fine-grained security protection for conditional branches, with about 5.4% resource overhead and less than 5.5% performance overhead.

Analysis the performance of Delay Locked Loop Physically Unclonable Functions for smart energy meter

The provision of secure and sustainable energy services is ensured by this research, also contributing to the advancement of technology align with the Sustainable Development Goals (SDGs). The motivation behind this study stems from the critical need to bolster hardware security within cutting-edge smart grid infrastructure, and more specifically, for smart energy metering technology. To address this need, this paper introduces a feasible and modular approach for enhancing the security through the implementation of a cryptographic key generator. This key generator is based on a modified Delay-based Physically Unclonable Function (PUF), which incorporates the innovative concept of a Delay Locked Loop(DLL).The reliability of the proposed PUFs has been rigorously assessed, demonstrating impressive performance levels of 98.02% and 99.1% across a wide temperature and supply voltage, spanning from -40°C to 80°C and (3.0-3.6) V. This is showcasing exceptional functionality within the smart meter’s operational parameters.The effectiveness of this approach is confirmed through practical testing conducted on the ZYNQ-7 ZC 702 Field-Programmable Gate Array (FPGA) platform.The outcomes are encouraging by substantial uniqueness (55.96% and 56.2%) and uniformity (51.2% and 49.15%). This research significantly advances the state of the art by surpassing previous investigations into XOR Arbiter PUF (XOR APUF) and Configurable Ring Oscillator PUF (CRO PUF) designs. Furthermore, the paper delves into an examination of the proposed design’s resilience against modeling attacks, along with comprehensive security assessments.

Advancing Hardware Security: A Review and Novel Design of Configurable Arbiter PUF with DCM-Induced Metastability for Enhanced Resource Efficiency and Unpredictability

As the Internet of Things (IoT) and Blockchain technologies continue to assert their dominance in the technical landscape, the demand to enhance security measures becomes foremost. In this context, Physical Unclonable Functions (PUFs) are widely used hardware security primitives that can be used to solve a wide range of security issues. To support hardware security solutions, this paper presents an extensive overview and analysis of the existing Physical Unclonable Functions (PUFs) used as True Random Number Generators (TRNGs). Recognizing the shortcomings of current PUF designs, we propose a configurable Arbiter PUF design employing Digital Clock Manager (DCM)-induced metastability as an entropy source, presenting a robust solution for evolving hardware security. To mitigate the adverse consequences of metastability, the proposed Arbiter PUF includes a Carry Chain primitive with four Flip-Flop clones. Acknowledging the constantly evolving IoT and Blockchain environment, the suggested configurable Arbiter PUF is made to satisfy the highest security standards. By exploiting the inherent variations in FPGA technology, we aim to reduce system resource and area consumption, aligning with the efficiency criteria of modern applications. The system's performance is additionally enhanced by an on-chip post-processing based on DSP. Simulation results demonstrate successful implementation on a Xilinx Basys-3 FPGA board, offering a scalable and efficient solution. The generated sequences of the proposed PUF undergo rigorous testing, including National Institute of Standards and Technology (NIST) statistical tests for uniqueness, reliability, and randomness. This holistic approach aims to improve the PUF's performance and security.

A dependable and resource-frugal ring oscillator physically unclonable function

ABSTRACT Silicon Physical Unclonable Function (PUF) is a crucial component for hardware security, providing unique device identification in networks. PUF provides robust security for cryptographic keys and IC digital fingerprints. However, resource constraints in network devices limit its use in security protocols. To address this challenge, PUF offers a lightweight hardware security solution with two main types: strong PUF (e.g. arbiter PUF) and Ring Oscillator (RO) PUF. The first option produces large CRPs with improved security but incurs hardware overhead, whereas the second option offers lower overhead with smaller CRP size, leading to reduced security. This paper introduces a novel, cost-effective solution to enhance RO PUF security while reducing hardware limitations. Our proposal involves a resource sharing technique with scan flip-flops, multiplexers, and inverter logic. This approach takes advantage of existing scan chains in circuit netlists to reduce PUF area without sacrificing uniqueness. A specific set of test patterns and odd number of inverters transform the memory-based PUF into an RO PUF. Our solution also leverages pass transistor-based implementation to significantly reduce power consumption and area overhead. Simulation results show that our approach effectively reduces area and power consumption while maintaining PUF uniqueness.

PN-APUF: A MOSFET threshold loss based strong arbiter PUF with double-edge sampling

PN-APUF: A MOSFET threshold loss based strong arbiter PUF with double-edge sampling

A Response-Feedback-Based Strong PUF with Improved Strict Avalanche Criterion and Reliability.

Physical Unclonable Functions (PUFs) are significant in building lightweight Internet of Things (IoT) authentication protocols. However, PUFs are susceptible to attacks such as Machine-Learning(ML) modeling and statistical attacks. Researchers have conducted extensive research on the security of PUFs; however, existing PUFs do not always possess good statistical characteristics and few of them can achieve a balance between security and reliability. This article proposes a strong response-feedback PUF based on the Linear Feedback Shift Register (LFSR) and the Arbiter PUF (APUF). This structure not only resists existing ML modeling attacks but also exhibits good Strict Avalanche Criterion (SAC) and Generalized Strict Avalanche Criterion (GSAC). Additionally, we introduce a Two-Level Reliability Improvement (TLRI) method that achieves 95% reliability with less than 35% of the voting times and single-response generation cycles compared to the traditional pure majority voting method.

CAPUF: Design of a configurable circular arbiter PUF with enhanced security and hardware efficiency

Conventional security systems incur considerable computational resources, which become a significant hindrance for resource constraints internet of things (IoT) and wireless sensor network applications. Downsizing the existing security processes necessitates demand for lightweight cryptography for a secure system. The Physically Unclonable Function (PUF) extracts the uncontrollable randomness in the physical variation of integrated circuits (ICs). It is now proven to be promising security primitive for many hardware security applications, including authentication and anti-counterfeiting. The Arbiter PUF (APUF) provides a viable solution with minimal design overhead. This work proposes a new PUF variant, the Configurable Circular Arbiter PUF (CAPUF), for hardware security applications. In the CAPUF, the position of switches in an APUF are selectively altered to amalgam non-linearity and Strict Avalanche Criterion (SAC) properties, which enhances its security at low design overhead. An important feature of the CAPUF is that it is configurable, and this flexibility gives it a considerable advantage over many existing PUF variants. Simulation results and statistical analyses establish that the CAPUF outperforms the existing APUF variants through a combination of cost-effective architecture, SAC property, adequate modeling robustness, and the trade-off between security and hardware overhead.

Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead

Physical unclonable function (PUF) is a hardware security primitive with significant application potential. However, strong PUF is vulnerable to machine learning attacks based on modeling attacks. Although various resistance techniques have been proposed, strong PUF suffers from deficiencies in its resistance to machine learning attacks, hardware overhead, and reliability. This study proposes a highly reliable and secure lightweight PUF that complicates the original challenge using an internal response. Specifically, the internal response is used to determine the odd/even bit flip or left/right cyclic shift of the original challenge to achieve preliminary obfuscation, and byte substitution that exploits an S-box is performed on the preliminary obfuscated challenge to achieve deep nonlinear obfuscation. Experimental results on a Xilinx Artix-7 FPGA show that the proposed PUF is not only highly resistant to machine learning (ML) attacks but also has a low hardware overhead. An arbiter PUF(APUF), which uses the proposed obfuscated scheme with a 64-bit challenge length, was evaluated by three advanced machine learning algorithms with up to 600,000 challenge–response-pairs (CRPs) in the dataset, and the observed prediction accuracy was less than 56 %. Moreover, the PUF is unique, reliable, and has a significantly lower hardware overhead than other prior anti-attack PUFs.

Modeling-Attack-Resistant Strong PUF Exploiting Stagewise Obfuscated Interconnections With Improved Reliability

This article presents an obfuscated-interconnection physical unclonable function (OIPUF) to resist modeling attacks. By introducing nonlinear operations through exploiting the random interconnections of delay stages, the proposed OIPUF can theoretically improve the PUF security while consuming the same hardware resources as the conventional XOR Arbiter PUF (XOR APUF). We further propose the metastability-detection (MD) arbiter to effectively improve the PUF reliability. Implemented on Xilinx Artix-7 FPGA, both the proposed (64,4)-and (64,8)-OIPUF demonstrate a good reliability and uniformity, with the proposed (64,8)-OIPUF showing a better uniqueness and strict avalanche criterion (SAC) performance. Measurement results also show that the proposed MD arbiter can reduce the bit error rate (BER) of the (64,4)-and (64,8)-OIPUF by.68 and.48 at up to 100.C, respectively. Evaluated using the Logistic Regression (LR), Artificial Neural Network (ANN), and Covariance Matrix Adaptation-Evolution Strategy (CMAES) machine learning (ML) algorithms, the proposed (64,4)-and (64,8)-OIPUF can achieve a worst case prediction accuracy of 61.47% and 50.59% with up to 10M CRPs as training set, respectively, demonstrating a significant improvement over similar prior arts.

ANV-PUF: Machine-Learning-Resilient NVM-Based Arbiter PUF

Physical Unclonable Functions (PUFs) have been widely considered an attractive security primitive. They use the deviations in the fabrication process to have unique responses from each device. Due to their nature, they serve as a DNA-like identity of the device. But PUFs have also been targeted for attacks. It has been proven that machine learning (ML) can be used to effectively model a PUF design and predict its behavior, leading to leakage of the internal secrets. To combat such attacks, several designs have been proposed to make it harder to model PUFs. One design direction is to use Non-Volatile Memory (NVM) as the building block of the PUF. NVM typically are multi-level cells, i.e, they have several internal states, which makes it harder to model them. However, the current state of the art of NVM-based PUFs is limited to ‘weak PUFs’, i.e., the number of outputs grows only linearly with the number of inputs, which limits the number of possible secret values that can be stored using the PUF. To overcome this limitation, in this work we design the Arbiter Non-Volatile PUF (ANV-PUF) that is exponential in the number of inputs and that is resilient against ML-based modeling. The concept is based on the famous delay-based Arbiter PUF (which is not resilient against modeling attacks) while using NVM as a building block instead of switches. Hence, we replace the switch delays (which are easy to model via ML) with the multi-level property of NVM (which is hard to model via ML). Consequently, our design has the exponential output characteristics of the Arbiter PUF and the resilience against attacks from the NVM-based PUFs. Our results show that the resilience to ML modeling, uniqueness, and uniformity are all in the ideal range of 50%. Thus, in contrast to the state-of-the-art, ANV-PUF is able to be resilient to attacks, while having an exponential number of outputs.

QR-PUF: Design and Implementation of a RFID-Based Secure Inpatient Management System Using XOR-Arbiter-PUF and QR-Code

In recent years, Physical Unclonable Functions (PUFs) have played a major role in providing low-cost physical security for IoT devices such as Radio Frequency Identification (RFID) tags. PUFs take advantage of the physical properties of the device to build unique security primitives that can be used by authentication mechanisms. Meanwhile, the security and convenience of QR codes for device authentication on mobile devices has been widely recognized. The point-to-point communication makes it less vulnerable to interception and analysis by adversaries. In this article, we propose a <i>new</i> RFID-based secure inpatient management system for identifying a legitimate patient. Our proposed system uses an XOR Arbiter PUF to generate a secret key-stream and then uses the key-stream to construct a secure QR code for secure identification. Also, since PUFs are vulnerable to machine learning attacks, we propose a modeling attack resilience obfuscation framework to enhance the security of the proposed protocol. Security analysis of the proposed scheme using ProVerif shows that the scheme is effective against a variety of imperative attacks on RFID devices. To show the applicability of the proposed scheme, we also provide a case study of an inpatient management system in hospitals.

Physically non-cloneable arbiter -type function with non-linear path pairs

Physically unclonable functions (PUFs) are basic physical cryptographical primitives, providing to solve tasks such as unclonable identification, digital device authentication and copyright authentication, true random sequence generation, etc. The major features of PUFs are stability, unpredictability and irreproducibility, due to uncontrollable random variations of distinctive features of the raw materials and technological processes used during their manufacturing. Generally, PUF are digital circuits that extract such variations and convert them into a binary format, which applied for further use. Among the variety of PUF types, an Arbiter PUF (APUF) is distinguished, which is a digital circuit with N-bit challenge input and single output for one-bit response generation. The functionality of APUF is based on comparison of transition time of two copies of the test signal along a pair of configurable paths, selected by the challenge value CH from a set of 2N all possible pairs. The result of the comparison is the binary value of the response. The set of all challenge-response pairs is a random, unpredictable and irreproducible in the cases of implementation of cloned PUF circuits both on single and/or on another chips, also using different technologies. This article presents a new approach to the synthesis of the APUF circuits, based on the permutation network elements, which allow to construct the nonlinear structures of pair of paths. This implies the potential complication of building an APUF model to attack its implemented instances. This article presents new schematic solutions for the synthesis of APUF circuits. Also, the main characteristics of the proposed APUF circuits implemented on the Xilinx Zynq-7000 FPGA is analyzed.

MA-GRNN:a high-efficient modeling attack approach utilizing generalized regression neural network for XOR arbiter physical unclonable functions

MA-GRNN:a high-efficient modeling attack approach utilizing generalized regression neural network for XOR arbiter physical unclonable functions

Automatic Balancing of “Arbiter” Physical Unclonable Function Paths

The features of building on the basis of programmable logic integrated circuits of “arbiter” physical unclonable functions (APUF) are considered. The problem of asymmetry of pairs of APUF paths is indicated and the negative impact of this phenomenon on their characteristics is noted. A time measuring system based on a ring oscillator scheme, which is used to analyze the time characteristics of APUF paths, is described. A method for automatic balancing of signal propagation delays through the APUF paths based on the calculation of the corrective value is proposed. The consistency of the proposed balancing technique is experimentally confirmed based on the improvement in the characteristics of the APUF after its implementation. A digital scheme of this technique is presented, which can form the basis for the development of a delay auto correction scheme through APUF paths with different levels of autonomy.

Birds of the Same Feather Flock Together: A Dual-Mode Circuit Candidate for Strong PUF-TRNG Functionalities

Physically Unclonable Functions (PUFs) and True Random Number Generators (TRNGs) are two highly useful hardware primitives to build up the root-of-trust for embedded devices in Internet-of-Things and Cyber-Physical System applications. These applications demand the primitives be lightweight, yet flexible. However, PUFs are designed to offer <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">repetitive and instance-specific</i> randomness, whereas TRNGs are expected to be <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">invariably</i> random. A challenging but thought-provoking problem from a hardware designer's perspective would be to design a circuit that serves the purpose of both PUF and TRNG depending on the exact requirement of the application. Here, we present a dual-mode PUF-TRNG design that utilises two different hardware-intrinsic properties, i.e. oscillatory metastability of Transition Effect Ring Oscillator (TERO) cell and propagation delay of a buffer within the cell to achieve this goal. A 48.62% reduction in area is accomplished due to the integration in comparison to separate instances of standalone PUFs/ TRNG designs, built from Programmable Delay Line (PDL) based Arbiter PUFs (APUFs) and TERO-TRNG. Our final design has a hardware footprint of 618 Look-Up Tables (LUTs) and 447 Flip-Flops (FFs). Furthermore, experimental analysis of the state-of-the-art modelling attacks, reliability attacks on the proposed PUF design shows a prediction accuracy of 55.37% and 50.14% respectively for 5.2M Challenge Response Pairs (CRPs). Additionally, the TRNG passes evaluation through National Institute of Standards and Technology (NIST) Special Publication (SP) 800-22 and German Federal Office for Information Security (BSI) Application Notes and Interpretation of the Scheme (AIS)-31 tests.

Recursive Challenge Feed Arbiter Physical Unclonable Function (RC-FAPUF) In 180nm Process For Reliable Key Generation In IOT Security

Physical Unclonable Functions (PUFs) are significant hardware primitives that use physical variations in the manufacturing process to build unclonable keys. They exploit the process variations (PVs) in transistors across the Integrated Circuits (ICs) that generate a unique signature for each chip for identification and authentication. In this article, a novel Recursive Challenge Feed Arbiter Physical Unclonable Function (RC-FAPUF) is proposed to generate unique, unpredictable, and reliable keys which are independent of the challenges that are generally fed by the user. Subsequently, the uncertainty in the prediction of the key increases while performing the security breach on IoT-enabled access systems like smartcards. The proposed design has a significant advantage in the feed-forward arbitration mechanism to generate reliable keys against PVs. Moreover, the robustness of the keys is measured by reliability is achieved as 99.91% when performed over a temperature that ranges from −40°C to +125°C and 99.23% with ±10% variations in supply voltage. The proposed RC-FAPUF is implemented in a 180 nm CMOS process and the responses regarding PVs are validated through a prediction analysis of 48% with Linear Regression (LR) against security attacks. It is confirmed that a significant improvement over previous works is witnessed with our design.

A sequential strong PUF architecture based on reconfigurable neural networks (RNNs) against state-of-the-art modeling attacks

Modeling attacks such as machine learning attacks are pretty efficient in breaking hardware security primitives like silicon strong physical unclonable functions (PUFs). As compared to regular strong PUFs such as arbiter PUFs and lightweight (LW)-PUFs, subthreshold current array (SCA)-PUFs exhibit a better resilience against modeling attacks since they utilize the non-linear relationship between the subthreshold current and gate voltage of transistors to obfuscate the corresponding relationship between input challenge and output response. Unfortunately, the degree of non-linearity (DoNL) within SCA-PUFs is still not sufficiently high to resist against state-of-the-art modeling attacks. Therefore, to further enhance DoNL for resisting against modeling attacks, a new strong PUF architecture is proposed in this paper by embedding reconfigurable neural networks (RNNs) into SCA-PUFs. Mathematical foundations are established for finding appropriate RNNs that are able to maximize the DoNL of an SCA-PUF. As shown in the result, when state-of-the-art modeling attacks like Lagrange multiplier attacks (LMAs) are selected, the robustness of the proposed RNN-embedded SCA-PUF is enhanced over 20 times with less than 18.5% power and area overhead as compared to a regular SCA-PUF.

A Problem-tailored Adversarial Deep Neural Network-Based Attack Model for Feed-Forward Physical Unclonable Functions

With the exceeding advancement in technology, the sophistication of attacks is considerably increasing. Standard security methods fall short of achieving the security essentials of IoT against physical attacks due to the nature of IoTs being resource-constrained elements. Physical Unclonable Functions (PUFs) have been successfully employed as a lightweight memoryless solution to secure IoT devices. PUF is a device that exploits the integrated circuits’ inherent randomness originated during the fabrication process to give each physical entity a unique identifier. Nevertheless, because PUFs are vulnerable to mathematical clonability, Feed-Forward Arbiter PUF (FF PUF) was introduced to withstand potential attack methods. Motivated by the necessity to expose a critical vulnerability of the standard FF PUFs design, we introduce a problem-tailored adversarial model to attack FF PUF design using a carefully engineered loop-specific neural network-based design calibrated and trained using FPGA-based in-silicon implementation data to exhibit real-world attacking scenarios posed on FF PUFs, in addition to applying simulated data. The empirical results show that the proposed adversarial model adds outperforming results to the existing studies in attacking FF PUFs, manifesting the improved efficiency in breaking FF PUFs. We demonstrate our high-performing results in numerical experiments of language modeling using the deep Neural Networks method.

Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version

We study a new transistor-level side-channel leakage caused by charges trapped in between stacked transistors namely residual electric charges (RECs). Building leakage models is important in designing countermeasures against side-channel attacks (SCAs). The conventional work showed that even a transistor-level leakage is measurable with a local electromagnetic measurement. One example is the current-path leak [1], [2]: an attacker can distinguish the number of transistors in the current path activated during a signal transition. Addressing this issue, Sugawara et al. proposed to use a mirror circuit that has the same number of transistors on its possible current paths. We show that this countermeasure is insufficient by showing a new transistor-level leakage, caused by RECs, not covered in the previous work. RECs can carry the history of the gate's state over multiple clock cycles and changes the gate's electrical behavior. We experimentally verify that RECs cause exploitable side-channel leakage. We also propose a countermeasure against REC leaks and designed advanced encryption standard-128 (AES-128) circuits using IO-masked dual-rail read-only memory with a 180-nm complementary metal-oxide-semiconductor (CMOS) process. We compared the resilience of our AES-128 circuits against EMA attacks with and without our countermeasure and investigated an RECs' effect on physically unclonable functions (PUFs). We further extend RECs to physically unclonable function. We demonstrate that RECs affect the performance of arbiter and ring-oscillator PUFs through experiments using our custom chips fabricated with 180- and 40-nm CMOS processes*.

Shrink Generator-based Strong PUF Architecture with Improved Uniqueness and Reliability on an FPGA

Silicon-based Physically Unclonable Functions (PUFs) are a source of physical security primitive that is either implemented on ASICs or FPGAs. A class of these security primitives that provide an exponentially large set of Challenge- Response Pairs (CRPs) is termed Strong PUF. That notwithstanding, the Arbiter and Feedforward Arbiter PUFs which are traditionally Strong PUFs, are not suitable for FPGA implementation. In this paper, a newly proposed PUF architecture that improves on the existing Configurable Ring Oscillator (CRO) PUF by increasing its dynamic configurability and its level of entropy is presented. To maintain the exponentially large set of CRPs, the Shrink Generator is applied to the traditionally Weak CRO-PUF. The proposed design is implemented and tested on a spartan-6 FPGA board using the Xilinx ISE tool. The proposed architecture demonstrates a uniqueness of 50.01% and is 96.43% reliable.