Approximate multipliers play vital role in the error-resilience applications by balancing accuracy and power efficiency. In this article, we improved the accuracy of approximate multipliers using a set of proposed approximate compressors which are able to compress any number of inputs to arbitrary numbers of output bits. To achieve better accuracy, probability of being one in the input bits is used to determine the compression ratio. Also, a novel scheme for allocating approximate and exact compressors in PPM is proposed to decrease column reduction stages. Error metrics namely PE, MED, MRED, and NED are calculated to evaluate accuracy of our approximate compressors. Experimental results show an average of 35% accuracy improvement, in comparison with the previous approximate compressors. We implemented four different multipliers including 8-bit, 12-bit, 16-bit, and 24-bit multipliers to prove goodness of our proposed algorithm. The multipliers are designed by Verilog and synthesized in a 45-nm standard CMOS technology. The experimental results demonstrate major accuracy superiority of our proposed multipliers in comparison with the state of the art approximate multipliers in terms of MED, MRED, and NED. According to the experimental results, the delay is improved 22%, on average, compared with exact multipliers.