Approximate Circuit Research Articles

Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

ABSTRACTThe error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.

Hybrid Radix-4 SESA/SEDA Adders for Medical Image Processing

Adders play a critical role as primary modules in circuit design, supporting error-tolerant applications such as machine learning, digital image processing, and signal processing. Therefore, the development of adders with low power consumption and energy efficiency is of utmost importance. Approximate adders outperform exact adders in VLSI chips. Among approximate adders, the hybridization of Single Exact and Single Approximation (SESA) and Single Exact and Dual Approximation (SEDA) techniques has emerged as a promising solution. These hybrid adders offer superior power and energy savings relative to other accurate and approximate adder designs. In this scheme, we propose the integration of hybrid radix-4 adders with approximation adders to achieve enhanced performance and pave the way for future hybrid approximate adder circuits. Extensive simulations validated the efficacy of the proposed approach. Furthermore, practical applications demonstrated the versatility and potential of hybrid adders in real-world scenarios. The proposed methodology ensures cost-effectiveness and facilitates seamless future updates and extensions. Overall, this research contributes to the advancement of efficient and low-power adder designs, addressing the evolving requirements of modern digital systems.

A Cheap and Basic Solar-Powered Smart Irrigation System Proposal for Medium and Small-Scale Farming

Nowadays, the need for water consumption for agricultural production is increasing. Economical use of water has become mandatory both to increase agricultural product yield and to eliminate the damage caused by excessive irrigation to the soil. Preferred instead of traditional irrigation, Drip irrigation, sprinkler irrigation, and pivot irrigation systems are now being replaced by “Smart Irrigation Systems” that save more water. In this study, a basic solar energy-supported mobile phone-controlled smart irrigation system, recommended for medium and small-scale agricultural enterprises, is proposed. In the study, the basic elements that make up the system, their approximate prices and circuit connection ways are shown. In the study, the cost, water, energy consumption, and payback periods of smart irrigation systems with traditional drip, sprinkler, and pivot irrigation methods were compared. As a result, although the initial investment cost in smart irrigation systems seems relatively high, it offers significant advantages in terms of resource efficiency and environmental sustainability. It is a fact that modern irrigation systems will make important contributions to national economies in the long term by increasing agricultural production and saving energy and water.

Low-Power Approximate Unsigned and Signed Multipliers with Configurable Error Recovery

In the field of Digital Signal Processing and similar applications, Approximate circuits are being explored as a means to enhance performance and energy efficiency by sacrificing a degree of accuracy. Within these circuits, Multipliers play a crucial role and are being investigated for their potential impact on overall system optimization. In this paper, a novel approximate multiplier with a low power consumption and a short critical path is proposed for high-performance DSP applications. This multiplier leverages a newly designed approximate adder that limits its carry propagation to the nearest neighbours for fast partial product accumulation. Different levels of accuracy can be achieved by using either OR gates or the proposed approximate adder in a configurable error recovery. The multipliers using these two error reduction strategies are referred to as Approximate Multiplier 1 (AM1) and Approximate Multiplier 2 (AM2), respectively. Both AM1 and AM2 have a low mean error distance, i.e., most of the errors are not significant in magnitude. Compared with a Unsigned multiplication multiplier, with the signed multiplication. The signed multiplication tends to have lower power consumption is observed. By utilizing an appropriate error recovery, the proposed approximate multipliers achieve similar processing accuracy as traditional exact multipliers, but with significant improvements in power.

An efficient approximate multiplier: Design, error analysis and application

Approximate circuits are extensively considered in error-resilient applications to reduce the design complexity. A multiplier is known as a key arithmetic unit of computational block, and thus improving the performance of the multiplier is significantly important to achieve an effective processor. In this paper, we develop two new inaccurate multipliers using approximate 4:2 compressor. Applying error correction block in the structure of these 8-bit multipliers remarkably increases the accuracy of design. The design performance and error metrics of the multipliers are analyzed. Furthermore, as an image processing application, we consider several benchmark images, and compare the quality metrics of image multiplication of our proposed multipliers to those obtained from different under-test multipliers of the previous studies. The design of multipliers is performed using HSPICE with 14 nm FinFET technology. The results demonstrate that the proposed multipliers provide suitable efficiency in the error analysis when compared to the exact multiplier in image processing application.

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design

LSAC: A Low-Power Adder Tree for Digital Computing-in-Memory by Sparsity and Approximate Circuits Co-Design

Analysis on the low-frequency electromagnetic pulse coupling to horizontal electrically short lines

In this study, we investigated the coupling features of the nuclear electromagnetic pulse (NEMP) on overhead cables in the middle-and-far regions, different from the transmission line model commonly used for field-line coupling in high-frequency cases, using a simpler lumped approximation to solve the electrically small size model in low-frequency cases. To verify its effectiveness, a simulation model with the same conditions was set up using the software of Computer Simulation Technology (CST), and cable coupling experiments were performed in a laboratory environment using a bounded-wave electromagnetic pulse simulator. The calculated results of the lumped approximation circuit were compared with the CST simulation and measured results, and the agreement was good. The results also shows that the load exhibits a differential response in the case of the low impedance and it is consistent with the excitation signal in the case of the high impedance. Finally, some more experiments were constructed to analyzed the effect of different cable parameters on the cable load response through experiments, and the experimental results are also in general agreement with the theoretical analysis, in which the induced signal of the low-impedance load is mainly determined by the magnetic field in the direction normal to the cable and the ground loop and the induced signal of the high-impedance load is mainly determined by the electric field in the direction of the height of the cable erection.

Quantum Financial Modeling on Noisy Intermediate-Scale Quantum Hardware: Random Walks Using Approximate Quantum Counting

Quantum computers are expected to contribute more efficient and accurate ways of modeling economic processes. Quantum hardware is currently available at a relatively small scale, but effective algorithms are limited by the number of logic gates that can be used, before noise from gate inaccuracies tends to dominate results. Some theoretical algorithms that have been proposed and studied for years do not perform well yet on quantum hardware in practice. This encourages the development of suitable alternative algorithms that play similar roles in limited contexts. This paper implements this strategy in the case of quantum counting, which is used as a component for keeping track of position in a quantum walk, which is used as a model for simulating asset prices over time. We introduce quantum approximate counting circuits that use far fewer 2-qubit entangling gates than traditional quantum counting that relies on binary positional encoding. The robustness of these circuits to noise is demonstrated. While this paper is mainly about robust simplified quantum circuit designs, we compare some aspects of the results with price change distributions from stock indices, and compare the behavior of circuits with and without mid-measurement to trends in the housing market.

Information scrambling and entanglement in quantum approximate optimization algorithm circuits

Information scrambling and entanglement in quantum approximate optimization algorithm circuits

Построение эквивалентных схем в системах троирования

Triple-Modular Redundancy (TMR) technique is one of the widely used approaches to provide reliable functioning of logical circuits. In recent years, it has become possible to insert Trojan Circuits into the same line of each identical circuit of TMR, such an opportunity makes the TMR technique vulnerable. The way out of this situation is to use instead of three identical circuits either two approximate circuits or three equivalent circuits that differ in structural implementation from each other. The obtained equivalent circuits, in contrast to the use of approximating circuits, does not create an unprotected area in the TMR technique. An approach is proposed to obtain equivalent circuits based on distortion of the irredundant system of SoPs, which describes the behavior of the primary circuit of the TMR technique. The resulting distorted systems of SoPs and the original system of SoPs are used for the synthesis of circuits.

Modified restoring array-based power efficient approximate square root circuit and its application

In this paper, the authors present an investigation into the benefits of approximate computing in energy-efficient error-resilient applications. It proposes an approximate square root (SQR) circuit based on the modified restoring array square root (MRAS) architecture. The MRAS design incorporates strategic elimination, optimization, and simplification of restoring subtractor cells (SC) within a conventional restoring array SQR circuit. As a result, the proposed MRAS circuit efficiently computes the square root of a 2n-bit unsigned integer, offering a 27 percent reduction in area, 13 percent faster computation, and 50 percent lower power consumption compared to the exact SQR design. To introduce approximation, configurable SCs are integrated into the MRAS circuit, enabling dual operation modes for both accuracy and approximation. This feature allows the proposed approximate modified restoring array SQR (AMRAS) design to cater to both error-resilient and error-sensitive applications. The evaluation involves a thorough analysis of accuracy and design metrics for 16-bit unsigned exact, state-of-the-art, and proposed square rooters. The designs are implemented on Artix7 FPGA using Verilog-HDL and simulated in the Xilinx Vivado simulator. The results demonstrate that the proposed AMRAS achieves a good trade-off between accuracy and hardware, presenting an impressive 80 percent reduction in power consumption and a 36 percent faster computation. Additionally, the paper showcases the practical application of the proposed AMRAS square rooters in the Sobel edge detection for image processing.

Data-Driven Feature Selection Framework for Approximate Circuit Design

The ever-growing data scale and computation complexity raise tremendous concerns about computer systems’ efficiency (i.e., lower hardware overhead and power consumption). Orthogonal to the advancement in semiconductor manufacturing technologies, approximate computing provides an alternative paradigm to reduce the hardware cost and power dissipation by relaxing computation quality for error-resilient applications. Voltage over-scaling (VOS) and approximate logic design (ALD) have become two mainstream approaches of approximate computing due to their superior performance in efficiency-critical designs. VOS reduces the power in quadratic by scaling down supply voltage while ALD saves hardware overhead by redesigning an approximate version of a given circuit (e.g., trimming less significant circuitry). However, these primitive approximate circuits (PAC) inevitably introduce notable errors and require additional error compensation circuits (ECC) to preserve computation accuracy. In existing works of ECC design, there lacks a systematic method that can generalize well to different approximate computing approaches. In this paper, we present a data-driven feature selection framework for approximate circuit design, which is applicable to both VOS and ALD. We propose novel algorithms that profoundly analyze the correlation between input data and output errors and select the most critical features to generate compensation circuits. Extensive evaluations are performed over a variety of circuits using approximate finite impulse response (FIR) filters and the prevalent approximate computing benchmark AxBench. The experimental results show that the proposed approach achieves superior compensation performance, boosting the circuit accuracy while only introducing trivial area overhead.

HEDALS: Highly Efficient Delay-Driven Approximate Logic Synthesis

Approximate computing is an emerging paradigm for error-tolerant applications. By introducing a reasonable amount of inaccuracy, both the area and delay of a circuit can be reduced significantly. To produce approximate circuits automatically, many approximate logic synthesis (ALS) algorithms are proposed. However, they mainly focus on area reduction and are not optimal in reducing the circuit delay. In this paper, we propose HEDALS, a highly efficient delay-driven ALS framework, which supports various types of local approximate changes (LACs), circuit representations, and average error metrics. To reduce delay, HEDALS builds a critical error graph (CEG) consisting of nodes on the critical paths and error information, and finds an optimized set of LACs in the CEG by either a maximum flow-based method or a priority cut-based method. The resulting set of LACs is applied to shorten all critical paths simultaneously so that the circuit delay is reduced. Besides, the simultaneous application of multiple LACs also makes HEDALS extremely fast. Compared to a state-of-the-art method, on average, HEDALS can reduce the circuit delay by 32.3%, while being 167W faster. The code of HEDALS is made open-source.

On the Use of Low-power Devices, Approximate Adders and Near-threshold Operation for Energy-efficient Multipliers

With the rising importance of power consumption in battery-powered devices, approximate computing techniques have emerged as a promising approach to strike a balance between exact computation and power savings, leading to improved delays. This paper investigates the combination of near-threshold operation and approximate adders to design power-efficient multipliers. We analyzed four multiplier architectures using 16 nm low-power and high-performance models. At the transistor level, three strategies for approximate full adders are explored, focusing on both partial product reduction and the final addition stage of the multipliers. Eleven test cases are thoroughly evaluated to identify the most suitable approximate circuit, considering the trade-offs among power, performance, and accuracy. The obtained results demonstrate a substantial reduction in power consumption at near-threshold operation. The replacement of exact full adders with the approximate copy strategy in the least significant bits of the multipliers leads to a reduction of up to 34.4% in power consumption and 19.2% in delay. The design-space exploration carried out in this study provides valuable insights for designers to choose the best approximate multiplier based on specific design requirements.

Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs

Numerous approximate computing (AC) techniques have been developed to reduce the design costs in error-resilient application domains, such as signal and multimedia processing, data mining, machine learning, and computer vision, to trade-off computation accuracy with area and power savings or performance improvements. Selecting adequate techniques for each application and optimization target is complex but crucial for high-quality results. In this context, Approximate High-Level Synthesis (AHLS) tools have been proposed to alleviate the burden of hand-crafting approximate circuits by automating the exploitation of AC techniques. However, such tools are typically tied to a specific approximation technique or a difficult-to-extend set of techniques whose exploitation is not fully automated or steered by optimization targets. Therefore, available AHLS tools overlook the benefits of expanding the design space by mixing diverse approximation techniques toward meeting specific design objectives with minimum error. In this work, we propose an AHLS design methodology for FPGAs that automatically identifies efficient combinations of multiple approximation techniques for different applications and design constraints. Compared to single-technique approaches, decreases of up to \(30\% \) in mean squared error and absolute increases of up to \(6.5\% \) in percentage accuracy were obtained for a set of image, video, signal processing and machine learning benchmarks.

Constrained optimization via quantum Zeno dynamics

Constrained optimization problems are ubiquitous in science and industry. Quantum algorithms have shown promise in solving optimization problems, yet none of the current algorithms can effectively handle arbitrary constraints. We introduce a technique that uses quantum Zeno dynamics to solve optimization problems with multiple arbitrary constraints, including inequalities. We show that the dynamics of quantum optimization can be efficiently restricted to the in-constraint subspace on a fault-tolerant quantum computer via repeated projective measurements, requiring only a small number of auxiliary qubits and no post-selection. Our technique has broad applicability, which we demonstrate by incorporating it into the quantum approximate optimization algorithm (QAOA) and variational quantum circuits for optimization. We evaluate our method numerically on portfolio optimization problems with multiple realistic constraints and observe better solution quality and higher in-constraint probability than state-of-the-art techniques. We implement a proof-of-concept demonstration of our method on the Quantinuum H1-2 quantum processor.

A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators

Approximate Computing Techniques (ACTs) take advantage of resilience computing applications to trade off among output precision, area, power, and performance. ACTs can lead to significant gains at affordable costs when efficiently implemented on Field Programmable Gate Array– (FPGA) based accelerators. Although several novel ACTs works have been proposed for FPGA accelerators, their applicability to high-assurance systems has not been explored as much. ACTs are becoming necessary in many critical Edge computing systems, such as self-driving cars and Earth observation satellites, to increase computational efficiency. However, an important question comes to mind when targeting critical systems: Does ACT optimization negatively affect the reliability of the system and how can one find optimal design architectures that blend classic mitigation techniques like Triple Modular Redundancy with approximation- and precise-based arithmetic hardware units to achieve the best possible computational efficiency without compromising dependability? This work aims to solve this research problem by introducing a Design Space Exploration (DSE) methodology that employs ACTs in arithmetic units of the design and identifies Pareto-optimal microarchitectures that balance all relevant gains of ACTs, such as area, speed, power, failure rate, and precision, by inserting the correct amount of approximation in the design. In a nutshell, our DSE methodology has formulated the DSE with a Multi-Objective Optimization Problem (MOP). Each Pareto-optimal solution of our tool finds which arithmetic units of the design to implement with precise and approximate circuits and which units to selectively triplicate to remove single points of failure that compromise system reliability below acceptable thresholds. We also suggest another formulation of the DSE into a Single-Objective constraint Optimization Problem (ScOP) producing a single optimal point, and that the user may demand, as a less time-consuming alternative to the MOP if a complete Pareto-front is not needed. Our methodology generates fault-tolerant versions of the Pareto-optimal approximate designs (or simple optimized approximate designs if the ScOP choice is picked) by selectively applying mitigation techniques in a way that the overheads of redundant resources for fault-tolerance do not negate the gains of approximation in comparison to the fault-tolerant versions of the precise design. We evaluate our method on two FPGA-based accelerators: a JPEG encoder and an H.264/Advanced Video Coding decoder. Our experimental results show significant gains in area, frequency, and power consumption without compromising output quality and system reliability compared to classic solutions that replicate all or a part of the resources of the precise design to increase dependability metrics.

Efficient Table-based Function Approximation on FPGAs Using Interval Splitting and BRAM Instantiation

This article proposes a novel approach for the generation of memory-efficient table-based function approximation circuits for edge devices in general and FPGAs in particular. Given a function f(x) to be approximated in a given interval [ x 0 , x 0+a ) and a maximum approximation error E a , the goal is to determine a function table implementation with a minimized memory footprint, i.e., number of entries that need to be stored. Rather than state-of-the-art work performing an equidistant sampling of the given interval by so-called breakpoints and using linear interpolation between two adjacent breakpoints to determine f(x) at the maximum error bound, we propose and compare three algorithms for splitting the given interval into sub-intervals to reduce the required memory footprint drastically based on the observation that in sub-intervals of low gradient, a coarser sampling grid may be assumed while guaranteeing the maximum interpolation error bound E a . Experiments on elementary mathematical functions show that a large fraction in memory footprint may be saved. Second, a hardware architecture implementing the sub-interval selection, breakpoint lookup, and interpolation at a latency of just 9 clock cycles is introduced. Third, for each generated circuit design, BRAMs are automatically instantiated rather than synthesizing the reduced footprint function table using LUT primitives, providing an additional degree of resource efficiency. The approach presented here for FPGAs can equally be applied to other circuit technologies for fast and, at the same time, memory-optimized function approximation at the edge.

Efficient Error Estimation for High-Level Design Space Exploration of Approximate Computing Systems

This article presents an error estimation technique for a data-flow graph (DFG) representation of an approximate computing (AC) circuit. The technique, which may be used during the high-level design of digital circuits, estimates error metrics for the outputs of the approximate circuit. The proposed technique receives as an input, output error characterizations of arithmetic modules in a high-level library. The error modeling of a library module is accomplished by dividing the input (operand) ranges into intervals and then characterizing the output error for different combinations of these input intervals. Subsequently, the error for each combination is stored in a lookup table (LUT). The module error models are integrated into a design space exploration (DSE) framework to evaluate different combinations of exact and approximate realizations of various operations in the DFG. The DSE, which performs error calculation and propagation from inputs to outputs of the target DFG, may be used to explore trade-offs between the output error and other design metrics of the approximate circuit, e.g., energy efficiency. The efficacy of the proposed method is assessed for three image processing benchmarks. Results for these benchmarks demonstrate that the framework can efficiently generate the Pareto frontier (PF) in the trade-off space of accuracy versus energy efficiency for the targeted benchmarks. Compared to a purely simulation-based exploration, the proposed technique provides an average of 92 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> speed improvement.

Designing of Energy-Efficient Approximate Multiplier Circuit for Processing Unit of IoT Devices

Designing of Energy-Efficient Approximate Multiplier Circuit for Processing Unit of IoT Devices