Approximate Booth Multipliers Research Articles

Design and evaluation of low power and area efficient approximate Booth multipliers for error tolerant applications

Approximate computing is an innovative design methodology to reduce the design complexity with an improvement in power efficiency, performance and area by compromising on the requirement of accuracy. In this paper, 8-bit approximate Booth multipliers have been proposed based on the approximate Radix-4 modified Booth encoding algorithm and approximate compressors for partial product accumulation to produce the final products are proposed. Two approximate Probability Based Booth Encoders (PBBE-1 and PBBE-2) have been proposed and used in the Booth multipliers. Error parameters have been measured and compared with the existing approximate booth multipliers. Exact booth multiplier of novel design existing in the literature has also been implemented for comparison purpose. The proposed approximate multipliers are then used in applications like image multiplication and IIR bi-quad filtering to prove their performance. Simulation results prove that the proposed booth multipliers outperform the existing approximate booth multipliers in terms of power and area with better accuracy. Synthesis results prove that the proposed Multiplier 6 was found to be the most efficient with a 56 % power consumption improvement and a 47 % area improvement when compared to the exact multiplier. All the simulations are carried out using Cadence® Genus with 180 nm CMOS process technology.

A design of multiplier based on Radix_4 Booth algorithm and 4-2 Wallace compression tree

In a multitude of computational and signal processing scenarios, the multiplier functions as a fundamental arithmetic component. Given the complex hardware arrangement of multipliers and their usual positioning within the crucial pathway of digital systems, their significance is substantial. Therefore, approximations of multipliers can greatly optimize system performance. This essay examines the fundamental ideas behind the Wallace tree, the Carry ahead adder, and the Radix-4 Booth algorithm. Additionally, instead of the more common 3-2 compressors, a Wallace tree structure with 4-2 compressors is used to compact these products for the manufacture of partial products. This reduction in compression stages to three significantly curtails delays along critical paths, thereby substantially improving overall performance. The compressed outcomes from the Wallace tree undergo processing via a 64 bit carry ahead adder, effectively addressing delays stemming from mutual carry propagation among sequentially connected regular full adders. Leveraging these principles and processes, a 32-bit signed multiplier is designed. Building upon this foundation, an approximate Booth multiplier is developed, enhancing both computational speed and reducing critical path delays. The functionality of the multiplier was validated using Vivado simulation, demonstrating its correctness. Additionally, the RTL-level circuitry of different segments of the multiplier was showcased.

Design and analysis of leading one/zero detector based approximate multipliers

Approximate multipliers are widely used in error-tolerant applications to improve circuit performance. For signed multiplication, previous approximate Booth multipliers usually have a large relative error with operands around “0”, while approximate leading one detector based (LOD-based) multipliers are not energy-efficient due to the extra preprocessing module. In this paper, a low relative error leading one/zero detector based approximate multiplier (LOZDAM) is proposed for signed multiplication, which dynamically truncates the operands according to the location of their most significant bits for signed complement data. Its accuracy can be configured to suit fault-tolerant applications with different accuracy requirements. A compensation strategy is proposed to reduce the calculation error of LOZDAMs at a low cost. All proposed designs are evaluated in 28nm/0.9 V/TT/25 °C CMOS. Compared with the exact design, the proposed LOZDAM6/7/8/9 with the width of Booth multiplier being 6/7/8/9-bit reduces average power by 64%/43%/33%/21%, with the mean relative error distance by 2.94%/1.46%/0.73%/0.36%, respectively. Case studies of image sharpening and serial Fast Fourier Transform system both show acceptable error and good power/area savings, which verifies the feasibility of our designs. In general, our proposed LOZD-based approximate multipliers achieve both high accuracy and low power.

Simplified Compressor and Encoder Designs for Low-Cost Approximate Radix-4 Booth Multiplier

In this brief, we present a novel design methodology of cost-effective approximate radix-4 Booth multipliers, which can significantly reduce the power consumption of error-resilient signal processing tasks. In contrast that the prior studies only focus on the approximation of either the partial product generation with encoders or the partial product reductions with compressors, the proposed method considers two major processing steps jointly by forcing the generated error directions to be opposite to each other. As the internal errors are naturally balanced to have zero mean, as a result, the proposed approximate Booth multiplier can minimize the required processing energy under the same number of approximate bits compared to the previous designs. Simulation results on FIR filtering and image classification applications reveal that the proposed approximate Booth multiplier shows the most attractive energy-performance trade-offs, achieving 28% and 34% of energy reduction compared to the exact Booth multiplier, respectively, with negligible accuracy loss.

Design of approximate Booth multipliers based on error compensation

With the rapid development of the Internet of Things, terminal equipment is greatly restricted in hardware resources and power supply. Therefore, there is an urgent need for new low-power computing units. Aiming at the problem of high power consumption of the arithmetic unit, a low-power approximate Booth multiplier based on complementary error is proposed. Among them, the new Booth encoder will produce positive errors and the approximate Wallace tree structure will produce negative errors. The mutual compensation of the two errors can improve the accuracy of the approximate Booth multiplier to a certain extent. The experimental results show that, compared with the existing multipliers, the proposed approximate Booth multiplier reduces the power consumption by 20.62% and the delay by 14.45%, saving 19.68% of the area. At the same time, its normalized average error distance is better than the existing approximate multiplier. Finally, the results of image filtering verify the practicality of the proposed approximate Booth multiplier.

ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design

Approximate computing technique has been adopted in recent years to develop low power design solutions targeted towards error-tolerant applications. Since the accuracy requirements of an application can vary dynamically at run-time, there is a justified need to design reconfigurable approximate circuits with varying power requirements proportional to computational accuracy. In this paper, we have proposed a novel accuracy reconfigurable approximate booth multiplier circuit. The design involves partial error correction through the addition of sign bits in a broken array multiplier. The design space of sign inclusive 16-bit broken array multipliers is thoroughly analyzed to include only non-redundant accuracy modes. The horizontal and vertical breaks introduced in the booth multiplier circuit are controlled using external control signals stored in a ROM. The proposed reconfigurable multiplier achieves significant power savings compared to accurate multiplier circuit and state-of-the-art accuracy configurable multiplier designs.

Design and Implementation of Low Power, High-Speed Configurable Approximation 8-Bit Booth Multiplier

Multimedia, machine learning and deep learning applications have a significant constraint on power consumption. A multiplier is a crucial component for many error-aware applications. An efficient approximate computing scheme is used for the error-tolerant applications due to higher accuracy in power cases. In the Booth, multiplier approximation is implemented for partial product generation and accumulations network. The significant stage of a multiplier is accumulation. In this paper, an efficient accumulation stage is suggested for the Radix-4 and 8-bit approximate Booth multiplier. The proposed accumulation multiplier has high speed, minimum area, negligible path delay and low power consumption. Compared to the Booth multiplier design with modified Booth encoding and conventional carry look-ahead adder for product generation with no other error, the proposed 8-bit multiplier design-I reduced power consumption, area and delay a maximum of 13.7%, 8.4% and 19.8%, respectively. Also, our proposed design is compared with the design of Booth multiplier with approximate Booth encoding and conventional carry look-ahead adder for product generation. The proposed 8-bit multiplier design-II reduced power consumption, area and delay by a maximum of 38.2%, 28.3% and 13.7%, respectively.

Hybrid Low Radix Encoding-Based Approximate Booth Multipliers

Radix-4 Booth encoding provides ease in the generation of partial products, thus is widely used to achieve power-efficient and low-area signed multipliers. Conversely, the radix-8 Booth encoding exhibits low-performance as it requires generation of odd multiples of the multiplicand. In this brief, this issue is addressed by approximating the odd multiples of radix-8 to their nearest power of two such that the errors complement each other. In the pursuit of an accuracy-energy trade-off, hybrid low radix (HLR) based two approximate Booth multipliers (HLR-BM1 and HLR-BM2) are designed. HLR-BM2, compared to the previous best error-optimized design (ABM1), achieved a reduced energy of 22% with a comparable MRED. Moreover, HLR-BM2 achieves an improvement of 75% in MRED and 11% in energy consumption compared to the previously best energy-optimized design (RAD64). As a case study, performance for image transformation is evaluated. A high peak signal-to-noise ratio (PSNR, close to 50dB) is obtained for the proposed multiplier designs.

Design, evaluation and application of approximate‐truncated Booth multipliers

Approximate computing provides a promising way to achieve low power design at the cost of acceptable error. As a core component in a processor, the performance of the multiplier is important. This study presents designs of approximate-truncated Booth multipliers (ATBMs) using proposed approximate modified radix-4 Booth encoders (AMBEs), approximate 4-2 compressors (ACs) and gradually truncated partial products. The accuracy of the ATBMs is adjustable with the so-called approximation factors that indicate the number of AMBEs and ACs used. The normalised mean error distance and the product of the power and delay are used to evaluate the error and the hardware performance of the multipliers. The results show that the proposed ATBMs outperform previous approximate Booth multipliers. Their validity is also shown with case studies of image processing, K-means clustering and handwritten digit recognition.

SIBAM—Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications

Approximate computing has emerged as a promising technique to develop energy efficient design solutions for error-tolerant applications. Many research efforts have been directed towards proposing approximations in power-hungry multiplier circuits. In this brief, we have introduced two variants of a broken array approximate booth multiplier design called SIBAM with partial error correction through discarded sign bit addition. Experimental results show that up to 63% of energy savings can be achieved compared to accurate multipliers with Mean Relative Error Distance (MRED) constrained at 1.5%. Moreover, extensive analysis shows that the proposed design outperforms state-of-the-art multipliers with energy savings achievable up to 24% at 0.3% MRED constraint.

Design and Analysis of Area and Power Efficient Approximate Booth Multipliers

Approximate computing is an emerging technique in which power-efficient circuits are designed with reduced complexity in exchange for some loss in accuracy. Such circuits are suitable for applications in which high accuracy is not a strict requirement. Radix-4 modified Booth encoding is a popular multiplication algorithm which reduces the size of the partial product array by half. In this paper, three Approximate Booth Multiplier Models (ABM-M1, ABM-M2, and ABM-M3) are proposed in which approximate computing is applied to the radix-4 modified Booth algorithm. Each of the three designs features a unique approximation technique that involves both reducing the logic complexity of the Booth partial product generator and modifying the method of partial product accumulation. The proposed approximate multipliers are demonstrated to have better performance than existing approximate Booth multipliers in terms of accuracy and power. Compared to the exact Booth multiplier, ABM-M1 achieves up to a 23 percent reduction in area and 15 percent reduction in power with a Mean Relative Error Distance (MRED) value of $7.9\times 10^{-4}$7.9×10-4. ABM-M2 has area and power savings of up to 51 and 46 percent respectively with a MRED of $2.7\times 10^{-2}$2.7×10-2. ABM-M3 has area savings of up to 56 percent and power savings of up to 46 percent with a MRED of $3.4\times 10^{-3}$3.4×10-3. The proposed designs are compared with the state-of-the-art existing multipliers and are found to outperform them in terms of area and power savings while maintaining high accuracy. The performance of the proposed designs are demonstrated using image transformation, matrix multiplication, and Finite Impulse Response (FIR) filtering applications.

Design and Analysis of Approximate Redundant Binary Multipliers

As technology scaling is reaching its limits, new approaches have been proposed for computional efficiency. Approximate computing is a promising technique for high performance and low power circuits as used in error-tolerant applications. Among approximate circuits, approximate arithmetic designs have attracted significant research interest. In this paper, the design of approximate redundant binary (RB) multipliers is studied. Two approximate Booth encoders and two RB 4:2 compressors based on RB (full and half) adders are proposed for the RB multipliers. The approximate design of the RB-Normal Binary (NB) converter in the RB multiplier is also studied by considering the error characteristics of both the approximate Booth encoders and the RB compressors. Both approximate and exact regular partial product arrays are used in the approximate RB multipliers to meet different accuracy requirements. Error analysis and hardware simulation results are provided. The proposed approximate RB multipliers are compared with previous approximate Booth multipliers; the results show that the approximate RB multipliers are better than approximate NB Booth multipliers especially when the word size is large. Case studies of error-resilient applications are also presented to show the validity of the proposed designs.

Low-Power Approximate Multipliers Using Encoded Partial Products and Approximate Compressors

Approximate computing has been considered to improve the accuracy-performance tradeoff in error-tolerant applications. For many of these applications, multiplication is a key arithmetic operation. Given that approximate compressors are a key element in the design of power-efficient approximate multipliers, we first propose an initial approximate 4:2 compressor that introduces a rather large error to the output. However, the number of faulty rows in the compressor's truth table is significantly reduced by encoding its inputs using generate and propagate signals. Based on this improved compressor, two 4 × 4 multipliers are designed with different accuracies and then are used as building blocks for scaling up to 16 × 16 and 32×32 multipliers. According to the mean relative error distance (MRED), the most accurate of the proposed 16 × 16 unsigned designs has a 44% smaller power-delay product (PDP) compared to other designs with comparable accuracy. The radix-4 signed Booth multiplier constructed using the proposed compressor achieves a 52% reduction in the PDP-MRED product compared to other approximate Booth multipliers with comparable accuracy. The proposed multipliers outperform other approximate designs in image sharpening and joint photographic experts group applications by achieving higher quality outputs with lower power consumptions. For the first time, we show the applicability and practicality of approximate multipliers in multiple-input multiple-output antenna communication systems with error control coding.

Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications

In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance. Non-iterative ALMs, that use three inexact mantissa adders, are presented. The proposed iterative ALMs (IALMs) use a set-one adder in both mantissa adders during an iteration; they also use lower-part-or adders and approximate mirror adders for the final addition. Error analysis and simulation results are also provided; it is found that the proposed approximate LMs with an appropriate number of inexact bits achieve higher accuracy and lower power consumption than conventional LMs using exact units. Compared with conventional LMs with exact units, the normalized mean error distance of 16-bit approximate LMs is decreased by up to 18% and the power-delay product has a reduction of up to 37%. The proposed approximate LMs are also compared with previous approximate multipliers; it is found that the proposed approximate LMs are best suitable for applications allowing larger errors, but requiring lower energy consumption. Approximate Booth multipliers fit applications with less stringent power requirements, but also requiring smaller errors. Case studies for error-tolerant computing applications are provided.

Design of Approximate Radix-4 Booth Multipliers for Error-Tolerant Computing

Approximate computing is an attractive design methodology to achieve low power, high performance (low delay) and reduced circuit complexity by relaxing the requirement of accuracy. In this paper, approximate Booth multipliers are designed based on approximate radix-4 modified Booth encoding (MBE) algorithms and a regular partial product array that employs an approximate Wallace tree. Two approximate Booth encoders are proposed and analyzed for error-tolerant computing. The error characteristics are analyzed with respect to the so-called approximation factor that is related to the inexact bit width of the Booth multipliers. Simulation results at 45 nm feature size in CMOS for delay, area and power consumption are also provided. The results show that the proposed 16-bit approximate radix-4 Booth multipliers with approximate factors of 12 and 14 are more accurate than existing approximate Booth multipliers with moderate power consumption. The proposed R4ABM2 multiplier with an approximation factor of 14 is the most efficient design when considering both power-delay product and the error metric NMED. Case studies for image processing show the validity of the proposed approximate radix-4 Booth multipliers.

Approximate Radix-8 Booth Multipliers for Low-Power and High-Performance Operation

The Booth multiplier has been widely used for high performance signed multiplication by encoding and thereby reducing the number of partial products. A multiplier using the radix- $4$ (or modified Booth) algorithm is very efficient due to the ease of partial product generation, whereas the radix- $8$ Booth multiplier is slow due to the complexity of generating the odd multiples of the multiplicand. In this paper, this issue is alleviated by the application of approximate designs. An approximate $2$ -bit adder is deliberately designed for calculating the sum of $1\times$ and $2\times$ of a binary number. This adder requires a small area, a low power and a short critical path delay. Subsequently, the $2$ -bit adder is employed to implement the less significant section of a recoding adder for generating the triple multiplicand with no carry propagation. In the pursuit of a trade-off between accuracy and power consumption, two signed $16\times 16$ bit approximate radix-8 Booth multipliers are designed using the approximate recoding adder with and without the truncation of a number of less significant bits in the partial products. The proposed approximate multipliers are faster and more power efficient than the accurate Booth multiplier. The multiplier with 15-bit truncation achieves the best overall performance in terms of hardware and accuracy when compared to other approximate Booth multiplier designs. Finally, the approximate multipliers are applied to the design of a low-pass FIR filter and they show better performance than other approximate Booth multipliers.

Array-Based Approximate Arithmetic Computing: A General Model and Applications to Multiplier and Squarer Design

We propose a general model for array-based approximate arithmetic computing (AAAC) to guide the minimization of processing error. As part of this model, the Error Compensation Unit (ECU) is identified as a key building block for a wide range of AAAC circuits. We develop theoretical analysis geared towards addressing two critical design problems of the ECU, namely, determination of optimal error compensation values and identification of the optimal error compensation scheme. We demonstrate how this general AAAC model can be leveraged to derive practical design insights that lead to optimal tradeoffs between accuracy, energy dissipation and area overhead. To further minimize energy consumption, delay and area of AAAC circuits, we perform ECU design simplification by introducing logic don't cares. By applying this model and using a commercial 90 nm CMOS standard cell library, we propose an approximate 16 × 16 fixed-width Booth multiplier that consumes 44.85% and 28.33% less energy and area compared with theoretically the most accurate fixed-width Booth multiplier. Furthermore, it reduces average error, max error and mean squared error by 11.11%, 28.11%, and 25.00%, respectively, when compared with the most accurate reported approximate Booth multiplier and outperforms the same design significantly by 19.10% for the energy-delay-mean squared error product. Using the same approach, significant energy consumption, area and error reduction is achieved for a squarer unit. To further reduce error and cost by utilizing extra signatures and don't cares, we demonstrate a 16-bit fixed-width squarer that improves the energy-delay-max error product by 15.81%.