Approximate Arithmetic Research Articles

A comprehensive exploration of approximate DNN models with a novel floating-point simulation framework

This paper introduces TorchAxf11https://github.com/knuscent/TorchAxf., a framework for fast simulation of diverse approximate deep neural network (DNN) models, including spiking neural networks (SNNs). The proposed framework utilizes various approximate adders and multipliers, supports industrial standard reduced precision floating-point formats, such as bfloat16, and accommodates user-customized precision representations. Leveraging GPU acceleration on the PyTorch framework, TorchAxf accelerates approximate DNN training and inference. In addition, it allows seamless integration of arbitrary approximate arithmetic algorithms with C/C++ behavioral models to emulate approximate DNN hardware accelerators.We utilize the proposed TorchAxf framework to assess twelve popular DNN models under approximate multiply-and-accumulate (MAC) operations. Through comprehensive experiments, we determine the suitable degree of floating-point arithmetic approximation for these DNN models without significant accuracy loss and offer the optimal reduced precision formats for each DNN model. Additionally, we demonstrate that approximate-aware re-training can rectify errors and enhance pre-trained DNN models under reduced precision formats. Furthermore, TorchAxf, operating on GPU, remarkably reduces simulation time for complex DNN models using approximate arithmetic by up to 131.38× compared to the baseline optimized CPU implementation. Finally, we compare the proposed framework with state-of-the-art frameworks to highlight its superiority.

VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration

VLSI Architectures of Approximate Arithmetic Units Applied to Parallel Sensors Calibration

Performance Improvement of Processor Through Configurable Approximate Arithmetic Units in Multicore Systems

Performance Improvement of Processor Through Configurable Approximate Arithmetic Units in Multicore Systems

AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch

Current state-of-the-art employs approximate multipliers to address the highly increased power demands of DNN accelerators. However, evaluating the accuracy of approximate DNNs is cumbersome due to the lack of adequate support for approximate arithmetic in DNN frameworks. We address this inefficiency by presenting AdaPT, a fast emulation framework that extends PyTorch to support approximate inference as well as approximation-aware retraining. AdaPT can be seamlessly deployed and is compatible with the most DNNs. We evaluate the framework on several DNN models and application fields including CNNs, LSTMs, and GANs for a number of approximate multipliers with distinct bitwidth values. The results show substantial error recovery from approximate re-training and reduced inference time up to 53.9x with respect to the baseline approximate implementation.

Implementation of Hardware and Energy Efficient Approximate Multiplier Architectures Using 4-2 Compressor for Images

Abstract: Approximate computing is tentatively applied in some digital signal processing applications which have an inherent tolerance for erroneous computing results. The approximate arithmetic blocks are utilized in them to improve the electrical performance of these circuits. Multiplier is one of the fundamental units in computer arithmetic blocks. Moreover, the 4-2 compressors are widely employed in the parallel multipliers to accelerate the compression process of partial products. In this brief, three novel approximate 4-2 compressors are proposed and utilized in 8-bit multipliers. Meanwhile, an error-correcting module (ECM) is presented to promote the error performance of approximate multiplier with the proposed 4-2 compressors. In this brief, the number of the approximate 4-2 compressor’s outputs is innovatively reduced to one, which brings further improvements in the energy-efficiency. This Design is implemented using Verilog HDL and simulated by Modelsim 6.4 c and synthesized by Xilinx tool.

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks.

In this paper, we explore efficient hardware implementation of feedforward artificial neural networks (ANNs) using approximate adders and multipliers. Due to a large area requirement in a parallel architecture, the ANNs are implemented under the time-multiplexed architecture where computing resources are re-used in the multiply accumulate (MAC) blocks. The efficient hardware implementation of ANNs is realized by replacing the exact adders and multipliers in the MAC blocks by the approximate ones taking into account the hardware accuracy. Additionally, an algorithm to determine the approximate level of multipliers and adders due to the expected accuracy is proposed. As an application, the MNIST and SVHN databases are considered. To examine the efficiency of the proposed method, various architectures and structures of ANNs are realized. Experimental results show that the ANNs designed using the proposed approximate multiplier have a smaller area and consume less energy than those designed using previously proposed prominent approximate multipliers. It is also observed that the use of both approximate adders and multipliers yields, respectively, up to 50% and 10% reduction in energy consumption and area of the ANN design with a small deviation or better hardware accuracy when compared to the exact adders and multipliers.

Spatial biases in approximate arithmetic are subject to sequential dependency effects and dissociate from attentional biases

The notion that mental arithmetic is associated with shifts of spatial attention along a spatially organised mental number representation has received empirical support from three lines of research. First, participants tend to overestimate results of addition and underestimate those of subtraction problems in both exact and approximate formats. This has been termed the operational momentum (OM) effect. Second, participants are faster in detecting right-sided targets presented in the course of addition problems and left-sided targets in subtraction problems (attentional bias). Third, participants are biased toward choosing right-sided response alternatives to indicate the results of addition problems and left-sided response alternatives for subtraction problems (Spatial Association Of Responses [SOAR] effect). These effects potentially have their origin in operation-specific shifts of attention along a spatially organised mental number representation: rightward for addition and leftward for subtraction. Using a lateralised target detection task during the calculation phase of non-symbolic additions and subtractions, the current study measured the attentional focus, the OM and SOAR effects. In two experiments, we replicated the OM and SOAR effects but did not observe operation-specific biases in the lateralised target-detection task. We describe two new characteristics of the OM effect: First, a time-resolved, block-wise analysis of both experiments revealed sequential dependency effects in that the OM effect builds up over the course of the experiment, driven by the increasing underestimation of subtraction over time. Second, the OM effect was enhanced after arithmetic operation repetition compared to trials where arithmetic operation switched from one trial to the next. These results call into question the operation-specific attentional biases as the sole generator of the observed effects and point to the involvement of additional, potentially decisional processes that operate across trials.

An RRAM-Based Digital Computing-in-Memory Macro With Dynamic Voltage Sense Amplifier and Sparse-Aware Approximate Adder Tree

RRAM is a promising candidate to implement large-capacity in-memory computing on edge AI devices due to its high density. However, the efficiency and accuracy of RRAM-based computing-in-memory (CIM) works are limited by large accumulation currents and device variations. The SRAM-based digital CIM achieves superior performance and efficiency while the adder tree dominates the area. In this brief, a digital RRAM CIM macro is proposed to achieve a better trade-off between accuracy, energy, and performance by three techniques. First, a dynamic voltage sense amplifier is designed to reduce >90% read currents of low resistance state (LRS) cell. Second, an OR gate approximate adder tree is proposed to reduce the area of the adder tree by 40%. Third, a sparse-aware finetuning algorithm is proposed to reduce the accuracy loss of approximate arithmetic to 0.4% on Cifar-10 dataset. The proposed design achieves 1966TOPS/W energy efficiency and 51.2GOPS/Kb normalized throughput at 1-bit precision which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.2\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.8\times $ </tex-math></inline-formula> higher than previous RRAM-based designs. This brief demonstrates the advantage of digital CIM using RRAM devices.

The relevance of basic numerical skills for fraction processing: Evidence from cross-sectional data.

Recent research indicated that fraction understanding is an important predictor of later mathematical achievement. In the current study we investigated associations between basic numerical skills and students' fraction processing. We analyzed data of 939 German secondary school students (age range = 11.92 to 18.00 years) and evaluated the determinants of fraction processing considering basic numerical skills as predictors (i.e., number line estimation, basic arithmetic operations, non-symbolic magnitude comparison, etc.). Additionally, we controlled for general cognitive ability, grade level, and sex. We found that multiplication, subtraction, conceptual knowledge, number line estimation, and basic geometry were significantly associated with fraction processing beyond significant associations of general cognitive ability and sex. Moreover, relative weight analysis revealed that addition and approximate arithmetic should also be considered as relevant predictors for fraction processing. The current results provide food for thought that further research should focus on investigating whether recapitulating basic numerical content in secondary school mathematics education can be beneficial for acquiring more complex mathematical concepts such as fractions.

DESIGN AND IMPLEMENTATION OF A NOVEL ENERGY-EFFICIENT MULTIPLIER CIRCUIT USING APPROXIMATE COMPUTING TECHNIQUE

A promising paradigm for many imprecision-tolerant applications has recently been identified as approximate arithmetic. By reducing accuracy standards, it can significantly reduce circuit complexity, latency, and energy consumption. In this research, we present a unique significance-driven logic compression (SDLC) approach for an energy-efficient approximate multiplier design. An algorithmic and adjustable lossy compression of the partial product rows based on their progressive bit importance is the core of this approach. To lessen the number of product rows, the resulting product terms are then commutatively remapped. As a result, the multiplier's complexity in terms of the number of logic cells and the lengths of critical routes is significantly decreased.

Training on number comparison, but not number line estimation, improves preschoolers’ symbolic approximate arithmetic

Although the performance of number comparison and number line estimation are correlated with symbolic approximate arithmetic ability, it is unclear whether they contribute differently to it. We conducted a training study with 96 preschoolers using pre- and post-tests measuring number comparison, number line estimation, and symbolic approximate arithmetic tasks. Participants were randomly divided into three groups (number comparison training, number line training, and control). The children in the training groups were trained using board games. The results showed that the number comparison training group showed a greater improvement in symbolic approximate arithmetic than did the other two groups. Further, improvement in number comparison was only found in the number comparison training group, whereas improvement in number line estimation was found in both training groups. These results indicate that symbolic approximate arithmetic relies on number comparison processing more than on number line estimation processing in preschoolers. Moreover, the cognitive mechanisms that number comparison and number line estimation abilities depend on are not exactly the same.

Approximate Arithmetic Circuit Design for Error Resilient Applications

When the application context is ready to accept different levels of exactness in solutions and is supported by human perception quality, then the term ‘Approximate Computing’ tossed before one decade will become the first priority . Even though computer hardware and software are working to generate exact results, approximate results are preferred whenever an error is in predefined bound and adaptive. It will reduce power demand and critical path delay and improve other circuit metrics. When it comes to traditional arithmetic circuits, those generating correct results with limitations on performance are rapidly getting replaced by approximate arithmetic circuits which are the need of the hour, and so on about their design.

FDFB: Full Domain Functional Bootstrapping Towards Practical Fully Homomorphic Encryption

Computation on ciphertexts of all known fully homomorphic encryption (FHE) schemes induces some noise, which, if too large, will destroy the plaintext. Therefore, the bootstrapping technique that re-encrypts a ciphertext and reduces the noise level remains the only known way of building FHE schemes for arbitrary unbounded computations. The bootstrapping step is also the major efficiency bottleneck in current FHE schemes. A promising direction towards improving concrete efficiency is to exploit the bootstrapping process to perform useful computation while reducing the noise at the same time. We show a bootstrapping algorithm, which embeds a lookup table and evaluates arbitrary functions of the plaintext while reducing the noise. Depending on the choice of parameters, the resulting homomorphic encryption scheme may be either an exact FHE or homomorphic encryption for approximate arithmetic. Since we can evaluate arbitrary functions over the plaintext space, we can use the natural homomorphism of Regev encryption to compute affine functions without bootstrapping almost for free. Consequently, our algorithms are particularly suitable for arithmetic circuits over a finite field with many additions and scalar multiplication gates. We achieve significant speedups when compared to binary circuit-based FHE. For example, we achieve 280-1200x speedups when computing an affine function of size 784 followed by any univariate function when compared to FHE schemes that compute binary circuits. With our bootstrapping algorithm, we can efficiently convert between arithmetic and boolean plaintexts and extend the plaintext space using the Chinese remainder theorem. Furthermore, we can run the computation in an exact and approximate mode where we trade-off the size of the plaintext space with approximation error. We provide a tight error analysis and show several parameter sets for our bootstrapping. Finally, we implement our algorithm and provide extensive tests. We demonstrate our algorithms by evaluating different neural networks in several parameter and accuracy settings.

Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit

Approximate arithmetic circuit (AAC) has emerged as a promising high-performance and energy-efficient circuit paradigm, which can be used in many applications with inherent error tolerance. To guarantee the usability of AACs and the availability of resilient applications, it is necessary to analyze the reliability of AACs. Most current literature focus on the error characteristics of AACs and few methods can be applied to estimate the reliability of AACs. These methods mostly have exponential time complexities and evaluate the average reliability assuming the input combinations are equally likely. In reality, the primary input (PI) signals can be given with any probability from 0 to 1. In this article, we assume that the PIs have random signal probabilities and propose approaches to reliability boundary estimation for AACs. First, we propose a new efficient and accurate method to evaluate the reliability of AACs. The method mainly calculates the AAC reliability for an input vector set, and furthermore, during the calculation, the correlation problem is considered to increase accuracy. Then, based upon the proposed AAC reliability evaluation method, we present the approaches to finding the reliability boundary. Randomly given signal probabilities of every PI, two heuristic search algorithms are utilized to find the lowest reliability. A comparison of the results on three series of AACs and the circuits in the EvoApprox8b library confirms that the proposed reliability evaluation method is more accurate and efficient than the previous method. Further experiments verify the plausibility of the calculated reliability boundary of AACs.

Arithmetic operations without symbols are unimpaired in adults with math anxiety.

This study characterises a previously unstudied facet of a major causal model of math anxiety. The model posits that impaired "basic number abilities" can lead to math anxiety, but what constitutes a basic number ability remains underdefined. Previous work has raised the idea that our perceptual ability to represent quantities approximately without using symbols constitutes one of the basic number abilities. Indeed, several recent studies tested how participants with math anxiety estimate and compare non-symbolic quantities. However, little is known about how participants with math anxiety perform arithmetic operations (addition and subtraction) on non-symbolic quantities. This is an important question because poor arithmetic performance on symbolic numbers is one of the primary signatures of high math anxiety. To test the question, we recruited 92 participants and asked them to complete a math anxiety survey, two measures of working memory, a timed symbolic arithmetic test, and a non-symbolic "approximate arithmetic" task. We hypothesised that if impaired ability to perform operations was a potential causal factor to math anxiety, we should see relationships between math anxiety and both symbolic and approximate arithmetic. However, if math anxiety relates to precise or symbolic representation, only a relationship between math anxiety and symbolic arithmetic should appear. Our results show no relationship between math anxiety and the ability to perform operations with approximate quantities, suggesting that difficulties performing perceptually based arithmetic operations do not constitute a basic number ability linked to math anxiety.

Using Algorithmic Transformations and Sensitivity Analysis to Unleash Approximations in CNNs at the Edge.

Previous studies have demonstrated that, up to a certain degree, Convolutional Neural Networks (CNNs) can tolerate arithmetic approximations. Nonetheless, perturbations must be applied judiciously, to constrain their impact on accuracy. This is a challenging task, since the implementation of inexact operators is often decided at design time, when the application and its robustness profile are unknown, posing the risk of over-constraining or over-provisioning the hardware. Bridging this gap, we propose a two-phase strategy. Our framework first optimizes the target CNN model, reducing the bitwidth of weights and activations and enhancing error resiliency, so that inexact operations can be performed as frequently as possible. Then, it selectively assigns CNN layers to exact or inexact hardware based on a sensitivity metric. Our results show that, within a 5% accuracy degradation, our methodology, including a highly inexact multiplier design, can reduce the cost of MAC operations in CNN inference up to 83.6% compared to state-of-the-art optimized exact implementations.

A survey of approximate arithmetic circuits and blocks

Abstract Approximate computing has become an emerging research topic for energy-efficient design of circuits and systems. Many approximate arithmetic circuits have been proposed, therefore it is critical to summarize the available approximation techniques to improve performance and energy efficiency at a acceptable accuracy loss. This paper presents an overview of circuit-level techniques used for approximate arithmetic. This paper provides a detailed review of circuit-level approximation techniques for the arithmetic data path. Its focus is on identifying critical circuit-level approximation techniques that apply to computational units and blocks. Approximate adders, multipliers, dividers, and squarer are introduced and classified according to their approximation methods. FFT and MAC are discussed as computational blocks that employ an approximate algorithm for implementation.

Interactive Proofs for Rounding Arithmetic

Interactive proofs are a type of verifiable computing that secures the integrity of computations. The need is increasing as more computations are outsourced to untrusted parties, e.g., cloud computing platforms. Existing techniques, however, have mainly focused on exact computations, but not approximate arithmetic (e.g., floating-point or fixed-point arithmetic). This makes it hard to apply them to certain types of computations (e.g., machine learning or financial applications) that inherently require approximate arithmetic. In this paper, we present an efficient interactive proof system for arithmetic circuits with rounding gates that can represent approximate arithmetic. The main idea is to reduce the rounding gate into a small sub-circuit without rounding, and reuse the machinery of the Goldwasser, Kalai, and Rothblum’s protocol (also known as the GKR protocol) and its recent refinements. Specifically, we shift the algebraic structure from a field to a ring to better deal with the notion of “digits”, and generalize the original GKR protocol over a ring. Then, we reduce the rounding operation to a low-degree polynomial over a ring, and develop a novel, optimal circuit construction of an arbitrary polynomial to transform the rounding polynomial to an optimal circuit representation. Moreover, further optimization on the proof generation cost for rounding is presented employing a Galois ring. Our experimental results show the efficiency of our protocol for approximate arithmetic, e.g., the implementation performed two orders of magnitude better than the existing system for a nested 128 by 128 matrix multiplication of depth 12 on the 16-bit fixed-point arithmetic.

Design Space Exploration on High-Order QAM Demodulation Circuits: Algorithms, Arithmetic and Approximation Techniques

Every new generation of wireless communication standard aims to improve the overall performance and quality of service (QoS), compared to the previous generations. Increased data rates, numbers and capabilities of connected devices, new applications, and higher data volume transfers are some of the key parameters that are of interest. To satisfy these increased requirements, the synergy between wireless technologies and optical transport will dominate the 5G network topologies. This work focuses on a fundamental digital function in an orthogonal frequency-division multiplexing (OFDM) baseband transceiver architecture and aims at improving the throughput and circuit complexity of this function. Specifically, we consider the high-order QAM demodulation and apply approximation techniques to achieve our goals. We adopt approximate computing as a design strategy to exploit the error resiliency of the QAM function and deliver significant gains in terms of critical performance metrics. Particularly, we take into consideration and explore four demodulation algorithms and develop accurate floating- and fixed-point circuits in VHDL. In addition, we further explore the effects of introducing approximate arithmetic components. For our test case, we consider 64-QAM demodulators, and the results suggest that the most promising design provides bit error rates (BER) ranging from 10−1 to 10−4 for SNR 0–14 dB in terms of accuracy. Targeting a Xilinx Zynq Ultrascale+ ZCU106 (XCZU7EV) FPGA device, the approximate circuits achieve up to 98% reduction in LUT utilization, compared to the accurate floating-point model of the same algorithm, and up to a 122% increase in operating frequency. In terms of power consumption, our most efficient circuit configurations consume 0.6–1.1 W when operating at their maximum clock frequency. Our results show that if the objective is to achieve high accuracy in terms of BER, the prevailing solution is the approximate LLR algorithm configured with fixed-point arithmetic and 8-bit truncation, providing 81% decrease in LUTs and 13% increase in frequency and sustains a throughput of 323 Msamples/s.

The causal impact of objective numeracy on judgments: Improving numeracy via symbolic and non-symbolic approximate arithmetic training yields more consistent risk judgments

Park and Brannon (2013, https://doi.org/10.1177/0956797613482944) found that practicing non-symbolic approximate arithmetic increased performance on an objective numeracy task, specifically symbolic arithmetic. Manipulating objective numeracy would be useful for many researchers, particularly those who wish to investigate causal effects of objective numeracy on performance. Objective numeracy has been linked to performance in multiple areas, such as judgment-and-decision-making (JDM) competence, but most existing studies are correlational. Here, we expanded upon Park and Brannon’s method to experimentally manipulate objective numeracy and we investigated whether numeracy’s link with JDM performance was causal. Experimental participants drawn from a diverse internet sample trained on approximate-arithmetic tasks whereas active control participants trained on a spatial working-memory task. Numeracy training followed a 2 × 2 design: Experimental participants quickly estimated the sum of OR difference between presented numeric stimuli, using symbolic numbers (i.e., Arabic numbers) OR non-symbolic numeric stimuli (i.e., dot arrays). We partially replicated Park and Brannon’s findings: The numeracy training improved objective-numeracy performance more than control training, but this improvement was evidenced by performance on the Objective Numeracy Scale, not the symbolic arithmetic task. Subsequently, we found that experimental participants also perceived risks more consistently than active control participants, and this risk-consistency benefit was mediated by objective numeracy. These results provide the first known experimental evidence of a causal link between objective numeracy and the consistency of risk judgments.