In industry-scale IC production, continuous improvements in processing and testing have resulted in defect test escape rates gradually reaching levels below 100 PPB for analog and mixed-signal ICs. Newer methodologies are needed to reduce these rates even further in light of the ever-tightening reliability requirements in the automotive industry while minimizing additional costs. Detecting latent defects is a major challenge today. A research experiment was conducted to assess and improve the latent defect test escape rate of industry-scale AMS testing at test time. This experiment altered the IC production process to artificially introduce latent gate oxide defects of different sizes and locations in a commercially available automotive IC in a 350high-voltage BCD process currently in production. The standard industrial test program was able to detect 58.4% of the latent defects at a yield loss of 6.2%. The latent defect detection rate has been improved to 95.5% at an additional yield loss of only 0.8% using Support Vector Machine (SVM) classifiers on the dataset of measurements resulting from the standard test program. This type of classifier is chosen for its optimal use of available data. The results show that a significant gain in coverage is possible without adding extra tests. In the experiment, testing at high temperatures (HOT) proved crucial in achieving this coverage benefit. Furthermore, while traditional tests mainly detect latent defects close to the source of transistors, the SVM approach significantly improves the detection of pinhole latent defects closer to the drain.