Fault Localization Approach Research Articles

Automated Fault Localization for C Programs

If a program does not fulfill a given specification, a model checker delivers a counterexample, a run which demonstrates the wrong behavior. Even with a counterexample, locating the actual fault in the source code is often a difficult task for the verification engineer.We present an automatic approach for fault localization in C programs. The method is based on model checking and reports only components that can be changed such that the difference between actual and intended behavior of the example is removed. To identify these components, we use the bounded model checker CBMC on an instrumented version of the program. We present experimental data that supports the applicability of our approach.

Interactive, visual fault localization support for end-user programmers

End-user programmers are writing an unprecedented number of programs, primarily using languages and environments that incorporate a number of interactive and visual programming techniques. To help these users debug these programs, we have developed an entirely visual, interactive approach to fault localization. This paper presents the approach. We also present the results of a think-aloud study that examined interactive, human-centric issues that arise in end-user debugging using a fault localization approach. Our results provide insights into the contributions such approaches can make to the end-user debugging process.

Test-Based Failure Analysis – Part 1: Fault Models

Abstract Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.