Design Space Exploration Approach Research Articles

Search-space Decomposition for System-level Design Space Exploration of Embedded Systems

The development of large-scale multi- and many-core platforms and the rising complexity of embedded applications have led to a significant increase in the number of implementation possibilities for a single application. Furthermore, rising demands on safe, energy-efficient, or real-time capable application execution make the problem of determining feasible implementations that are optimal with respect to such design objectives even more of a challenge. State-of-the-art Design Space Exploration (DSE) techniques for this problem demonstrably suffer from the vast and sparse search spaces posed by modern embedded systems, emphasizing the need for novel design methodologies in this field. Based on the idea of reducing problem complexity by a suitable decomposition of the system specification—in particular, by a reduction of target architecture or task mapping options—the work at hand proposes a portfolio of dynamic decomposition mechanisms that automatically decompose any system specification based on a short pre-exploration of the complete system. We present a two-phase approach consisting of (a) a set of novel data extraction and representation techniques combined with (b) a selection of filtering operations that automatically extract a decomposed system specification based on information gathered during pre-exploration. In particular, we employ heat map data structures and threshold as well as graph-partitioning filters to reduce problem complexity. The proposed decomposition procedure can seamlessly be integrated in any DSE flow, constituting a flexible extension for existing DSE approaches. Furthermore, it improves existing static decomposition techniques and other heuristics relying on information about the problem instance, since systems with irregular architectural topology or distribution of resource types can now be decomposed based on an automatic, problem-independent pre-exploration phase. We illustrate the efficiency of the proposed decomposition portfolio applied to state-of-the-art DSEs for many-core systems as well as networked embedded systems from the automotive domain. Experimental results show significant increases in optimization quality of up to 87% within constant DSE time compared to existing approaches.

From the Sensor to the Cloud: Intelligence Partitioning for Smart Camera Applications.

The Internet of Things has grown quickly in the last few years, with a variety of sensing, processing and storage devices interconnected, resulting in high data traffic. While some sensors such as temperature, or humidity sensors produce a few bits of data periodically, imaging sensors output data in the range of megabytes every second. This raises a complexity for battery operated smart cameras, as they would be required to perform intensive image processing operations on large volumes of data, within energy consumption constraints. By using intelligence partitioning we analyse the effects of different partitioning scenarios for the processing tasks between the smart camera node, the fog computing layer and cloud computing, in the node energy consumption as well as the real time performance of the WVSN (Wireless Vision Sensor Node). The results obtained show that traditional design space exploration approaches are inefficient for WVSN, while intelligence partitioning enhances the energy consumption performance of the smart camera node and meets the timing constraints.

Enhanced function-means modeling supporting design space exploration

AbstractOne problem in incremental product development is that geometric models are limited in their ability to explore radical alternative design variants. In this publication, a function modeling approach is suggested to increase the amount and variety of explored alternatives, since function models (FM) provide greater model flexibility. An enhanced function-means (EF-M) model capable of representing the constraints of the design space as well as alternative designs is created through a reverse engineering process. This model is then used as a basis for the development of a new product variant. This work describes the EF-M model's capabilities for representing the design space and integrating novel solutions into the existing product structure and explains how these capabilities support the exploration of alternative design variants. First-order analyses are executed, and the EF-M model is used to capture and represent already existing design information for further analyses. Based on these findings, a design space exploration approach is developed. It positions the FM as a connection between legacy and novel designs and, through this, allows for the exploration of more diverse product concepts. This approach is based on three steps – decomposition, design, and embodiment – and builds on the capabilities of EF-M to model alternative solutions for different requirements. While the embodiment step of creating the novel product's geometry is still a topic for future research, the design space exploration concept can be used to enable wider, more methodological, and potentially automated design space exploration.

IGOR, Get Me the Optimum! Prioritizing Important Design Decisions During the DSE of Embedded Systems

Design Space Exploration (DSE) techniques for complex embedded systems must cope with a huge variety of applications and target architectures as well as a wide spectrum of objectives and constraints. In particular, existing design automation approaches are either problem-independent, in that they do not exploit any knowledge about the optimization problem at hand, or are tailored to specific a priori assumptions about the problem and/or a specific set of design objectives. While the latter are only applicable within a very limited scope of design problems, the former may struggle to deliver high-quality solutions for problems with large design spaces and/or complex design objectives. As a remedy, we propose Importance-Guided Order Rearrangement (IGOR) as a novel approach for DSE of embedded systems. Instead of relying on an a priori problem knowledge, IGOR uses a machine-learning-inspired technique to dynamically analyze the importance of design decisions, i.e., the impact that these decisions—within the specific problem that is being optimized—have on the quality of explored problem solutions w.r.t. the given design objectives. Throughout the DSE, IGOR uses this information to guide the optimization towards the most promising regions of the design space. Experimental results for a variety of applications from different domains of embedded computing and for different optimization scenarios give evidence that the proposed approach is both scalable and adaptable, as it can be used for the optimization of systems described by several thousands constraints, where it outperforms both problem-specific and problem-independent optimization approaches and achieves ε-dominance improvements of up to 95%.

SystemC-based electronic system-level design space exploration environment for dedicated heterogeneous multi-processor systems

This work faces the problem of the Electronic System-Level (ESL) HW/SW co-design of dedicated electronic digital systems based on heterogeneous multi-processor architectures. In particular, the work presents a prototype SystemC-based environment that exploits a Design Space Exploration (DSE) approach able to suggest an HW/SW partitioning of the system specification and a mapping onto an automatically defined architecture. The descriptions of the reference HW/SW co-design methodology and the main design issues related to the developed DSE SW tools, supported by two reference use cases that allows to understand the role of the DSE step in the whole design flow, represent the core of the paper.

Grey Wolf Optimizer Driven design space exploration: A novel framework for multi-objective trade-off in architectural synthesis

Abstract Initiating Design Space Exploration (DSE) procedure during architectural synthesis is a highly intricate and tedious process. It involves optimal arrangement of resource utilizations within a design search space to resolve conflicting objectives of power-performance as well as area occupied by different types of resources. To arrive at an arrangement with minimum completion time among all of the permuted arrangements is a Non-Polynomial-hard problem. The problem becomes acute when it involves multi-objectives, as in the case of DSE for ensuring reliable power-performance-area trade-off of application specific processors. Many heuristic algorithms are being considered to derive an optimal solution for this multi-objective DSE procedure. A comprehensive mapping process and reliable solution evaluation approach called Grey Wolf Optimizer Driven DSE (GWO-DSE) is proposed in this article. The contributions of the article are as follows: i) Introduction of a novel GWO-DSE methodology for power-performance-area trade-off ii) Unique solution evaluation methodology called Utility Coefficients and Utility Ranking iii) Unique fitness evaluation function Grey wolf optimizer iv) Comparative benchmarks using digital filter transfer functions v) Substantial improvement in solution arrival within search space (average > 51%) and reduction in exploration time (>89%) when compared to recent DSE approaches for the tested benchmarks.

A Memetic Algorithm-Based Design Space Exploration for Datapath Resource Allocation During High-Level Synthesis

System designers have started adopting high-level synthesis (HLS) for architectural design because of the higher levels of abstraction offered. The HLS tools provide multiple design choices with tradeoff among different design parameters. Design Space Exploration (DSE) involves optimizing the synthesis options to achieve best tradeoffs among the metrics of interest. With the aim of exploring the design space in a feasible amount of time, we present a novel automated DSE approach. In particular, meeting the constraints presented by different parameters of interest is modeled as a multi-objective problem and solved using Memetic algorithm. The effectiveness of different variations of the Memetic algorithm in solving the DSE problem is studied and a Firefly algorithm-based solution is proposed with a novel probabilistic local search mechanism. The proposed approach is compared with existing solutions and the results prove that the proposed approach outperforms both existing solutions and other variations of Memetic algorithms in terms of convergence time and quality of results. In addition to that, a case study has been included to demonstrate the applicability of the approach. Results show that the proposed approach achieves a 33% improvement in cost, [Formula: see text] improvement in speed and [Formula: see text] improvement in hypervolume.

Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization

State-of-the-art system synthesis techniques employ meta-heuristic optimization techniques for Design Space Exploration (DSE) to tailor application execution, e.g., defined by a dataflow graph, for a given target platform. Unfortunately, the performance evaluation of each implementation candidate is computationally very expensive, in particular on recent multi-core platforms, as this involves compilation to and extensive evaluation on the target hardware. Applying heuristics for performance evaluation on the one hand allows for a reduction of the exploration time but on the other hand may deteriorate the convergence of the optimization technique toward performance-optimal solutions with respect to the target platform. To address this problem, we propose DSE strategies that are able to dynamically trade off between (i) approximating heuristics to guide the exploration and (ii) accurate performance evaluation, i.e., compilation of the application and subsequent performance measurement on the target platform. Technically, this is achieved by introducing a set of additional, but easily computable guiding objective functions, and varying the set of objective functions that are evaluated during the DSE adaptively. One major advantage of these guiding objectives is that they are generically applicable for dataflow models without having to apply any configuration techniques to tailor their parameters to the specific use case. We show this for synthetic benchmarks as well as a real-world control application. Moreover, the experimental results demonstrate that our proposed adaptive DSE strategies clearly outperform a state-of-the-art DSE approach known from literature in terms of the quality of the gained implementations as well as exploration times. Amongst others, we show a case for a two-core implementation where after about 3 hours of exploration time one of our proposed adaptive DSE strategies already obtains a 60% higher performance value than obtained by the state-of-the-art approach. Even when the state-of-the-art approach is given a total exploration time of more than 2 weeks to optimize this value, the proposed adaptive DSE strategy features a 20% higher performance value after a total exploration time of about 4 days.

Design optimisation of separate-jet exhausts for the next generation of civil aero-engines

ABSTRACTThe next generation of civil large aero-engines will employ greater bypass ratios compared with contemporary architectures. This results in higher exchange rates between exhaust performance and specific fuel consumption (SFC). Concurrently, the aerodynamic design of the exhaust is expected to play a key role in the success of future turbofans. This paper presents the development of a computational framework for the aerodynamic design of separate-jet exhaust systems for civil aero-engines. A mathematical approach is synthesised based on class-shape transformation (CST) functions for the parametric geometry definition of gas-turbine exhaust components such as annular ducts and nozzles. This geometry formulation is coupled with an automated viscous and compressible flow solution method and a cost-effective design space exploration (DSE) approach. The framework is deployed to optimise the performance of a separate-jet exhaust for very-high-bypass ratio (VHBR) turbofan engine. The optimisations carried out suggest the potential to increase the engine’s net propulsive force compared with a baseline architecture, through optimum exhaust re-design. The proposed method is able to identify and alleviate adverse flow-features that may deteriorate the aerodynamic behaviour of the exhaust system.

Symmetry-Eliminating Design Space Exploration for Hybrid Application Mapping on Many-Core Architectures

Large scale many-core systems are able to execute concurrently changing mixes of different parallel applications. Hybrid application mapping combines the strengths of design-time exploration/analysis of resource constellations for task-to-core mappings with the flexibility of choosing concrete mappings at run time. However, state-of-the-art design space exploration (DSE) techniques so far ignore the problem of symmetries in modern heterogeneous architectures: not only recurring patterns in the architecture but the mapping of tasks to instances of the same processor type may unnecessarily increase the search space by redundant, symmetrical implementations which typically affects the quality of the DSE. As a remedy, we propose a novel meta-heuristic DSE approach that eliminates architectural symmetries by abstracting the problem to a clustering of tasks and their mapping to processor types. However, we demonstrate that simple task clustering and type mappings may again introduce encoding symmetries in our search space. Thus, we present a formulation of the task clustering and type mapping as a 0–1 integer linear program (ILP) which eliminates all architectural as well as encoding symmetries from the search space. We also contribute a formal feasibility check to ensure that only implementations with at least one feasible concrete mapping are considered. To further improve the search process for feasible solutions, we apply satisfiability modulo theories-like learning techniques: from each infeasible implementation, we extract conditions why the implementation is infeasible and enrich our 0–1 ILP by additional constraints continuously during the DSE. Experimental results show that a DSE equipped with the novel symmetry-eliminating search space and the proposed learning techniques clearly outperforms a state-of-the-art approach known from literature in terms of the quality of the gained implementation classes.

Fuzzy Logic-Based DSE Engine: Reconfiguration for Optimization of Multicore Architectures

Moore’s law has been one of the reason behind the evolution of multicore architectures. Modern multicore architectures offer great amount of parallelism and on-chip resources that remain underutilized. This is partly due to inefficient resource allocation by operating system or application being executed. Consequently the poor resource utilization results in greater energy consumption and less throughput. This paper presents a fuzzy logic-based design space exploration (DSE) approach to reconfigure a multicore architecture according to workload requirements. The target design space is explored for L1 and L2 cache size and associativity, operating frequency, and number of cores, while the impact of various configurations of these parameters is analyzed on throughput, miss ratios for L1 and L2 cache and energy consumption. MARSSx86, a cycle accurate simulator, running various SPALSH-2 benchmark applications has been used to evaluate the architecture. The proposed fuzzy logic-based DSE approach resulted in reduction in energy consumption along with an overall improved throughput of the system.

Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems

Due to the growing complexity of Systems-on-Chip (SoC) and the increasing cost of their redesign and fabrication, industrials are urgently looking for design methodologies allowing them to identify issues early in the design flow and to explore the largest possible space of solutions. Several aspects should be taken into account in this context, among which power consumption is considered as a major concern. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach facilitates designers work by abstracting the energetic behavior of embedded systems through high-level models targeting an automatic generation of power-aware simulation code. It offers also the possibility to model dynamic power management aspects in order to use the corresponding generated code for DSE. This approach was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile and its simulator. This paper illustrates the proposed approach through a Software-Defined Radio (SDR) case study integrating the Dynamic Slack Reclamation (DSR) policy for dynamic power management. The processor power estimates obtained by the generated simulation code were compared to those obtained from physical implementation on the Xilinx Zynq-7000 platform. This comparison showed that our MDE approach allows to take efficient design decisions early in the design flow.

Clustering-Based Selection for the Exploration of Compiler Optimization Sequences

A large number of compiler optimizations are nowadays available to users. These optimizations interact with each other and with the input code in several and complex ways. The sequence of application of optimization passes can have a significant impact on the performance achieved. The effect of the optimizations is both platform and application dependent. The exhaustive exploration of all viable sequences of compiler optimizations for a given code fragment is not feasible. As this exploration is a complex and time-consuming task, several researchers have focused on Design Space Exploration (DSE) strategies both to select optimization sequences to improve the performance of each function of the application and to reduce the exploration time. In this article, we present a DSE scheme based on a clustering approach for grouping functions with similarities and exploration of a reduced search space resulting from the combination of optimizations previously suggested for the functions in each group. The identification of similarities between functions uses a data mining method that is applied to a symbolic code representation. The data mining process combines three algorithms to generate clusters: the Normalized Compression Distance, the Neighbor Joining, and a new ambiguity-based clustering algorithm. Our experiments for evaluating the effectiveness of the proposed approach address the exploration of optimization sequences in the context of the ReflectC compiler, considering 49 compilation passes while targeting a Xilinx MicroBlaze processor, and aiming at performance improvements for 51 functions and four applications. Experimental results reveal that the use of our clustering-based DSE approach achieves a significant reduction in the total exploration time of the search space (20× over a Genetic Algorithm approach) at the same time that considerable performance speedups (41% over the baseline) were obtained using the optimized codes. Additional experiments were performed considering the LLVM compiler, considering 124 compilation passes, and targeting a LEON3 processor. The results show that our approach achieved geometric mean speedups of 1.49 × , 1.32 × , and 1.24 × for the best 10, 20, and 30 functions, respectively, and a global improvement of 7% over the performance obtained when compiling with -O2.

Multi-objective kernel mapping and scheduling for morphable many-core architectures

A new optimization framework to maximize the performance and efficiency of morphable many-core accelerators is proposed. The devised methodology supports the co-existence of multiple optimization goals and constraints (e.g., computational performance, power, energy consumption and runtime reconfiguration overhead) by relying on a design space exploration approach based on a convenient adaptation of a Multi-Objective Evolutionary Algorithm. In accordance, the proposed algorithm allows the generation of a comprehensive set of execution plans, specifically targeting an efficient runtime adaptation of the processing elements instantiated in morphable slots of the processing structure. The conducted experimental evaluation shows significant gains in terms of the attained performance and energy efficiency when considering both highly parallel and data dependent applications, achieving peak power dissipation and energy consumption reductions as high as 54% and 45%, respectively.

Component-Based Synthesis of Embedded Systems Using Satisfiability Modulo Theories

Constraint programming solvers, such as Satisfiability Modulo Theory (SMT) solvers, are capable tools in finding preferable configurations for embedded systems from large design spaces. However, constructing SMT constraint programs is not trivial, in particular for complex systems that exhibit multiple viewpoints and models. In thisarticle we propose CoDeL: a component-based description language that allows system designers to express components as reusable building blocks of the system with their parameterizable properties, models, and interconnectivity. Systems are synthesized by allocating, connecting, and parameterizing the components to satisfy the requirements of an application. We present an algorithm that transforms component-based design spaces, expressible in CoDeL, to an SMT program, which, solved by state-of-the-art SMT solvers, determines the satisfiability of the synthesis problem, and delivers a correct-by-construction system configuration. Evaluation results for use cases in the domain of scheduling and mapping of distributed real-time processes confirm, first, the performance gain of SMT compared to traditional design space exploration approaches, second, the usability gains by expressing design problems in CoDeL, and third, the capability of the CoDeL/SMT approach to support the design of embedded systems.

Full-factorial design space exploration approach for multi-criteria decision making of the design of industrial halls

Industrial halls pose high energy saving potential that is not yet explored under current design practice. Common design approaches such as parametric study or optimization are largely constrained by the assumptions and do not promote flexibility in the decision making process. Based on the unique characteristics of industrial halls, this paper develops a full factorial design space exploration approach to support multi-criteria design decision making. Energy performance, environmental impact, and cost effectiveness are studied over the whole life cycle. The approach is demonstrated with a case study of a warehouse in Amsterdam. Design parameters of interest are the insulation values, construction types, skylight coverage and transpired solar collector coverage. The results indicate that this approach offers design solutions that might not be otherwise identified. The non-case-specific one-time investigation allows objective space of derived performance to be generated dynamically based on even changing information or inputs specified by the users at the time of making the decision. This new design support approach facilitates designers to assess feasibility of any design solution based on their own desired set of performance requirement under different probable scenarios in the future.

Combining structural performance and designer preferences in evolutionary design space exploration

Abstract This paper addresses the need to consider both quantitative performance goals and qualitative requirements in conceptual design. A new computational approach for design space exploration is proposed that extends existing interactive evolutionary algorithms for increased inclusion of designer preferences, overcoming the weaknesses of traditional optimization that have limited its use in practice. This approach allows designers to set the evolutionary parameters of mutation rate and generation size, in addition to parent selection, in order to steer design space exploration. This paper demonstrates the potential of this approach through a numerical parametric study, a software implementation, and series of case studies.

Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis

Technology evolution and energy of particle impact both plays a major role in inducing multi-cycle transient fault (longer duration transient) in a device. However, designing an optimized multi-cycle fault tolerant system is non-trivial. This paper presents a novel design space exploration (DSE) approach for multi-cycle transient fault tolerant datapath based on user power-delay constraints during high level synthesis (HLS). To the best of the authors’ belief, this is the first work to solve this problem in the literature so far. More specifically, the current work in the literature so far utilizes ‘triple modular redundancy (TMR)’ to design a fault tolerant datapath, however, this paper proposes a ‘dual modular redundancy (DMR) design with equivalent circuit’ scheme to achieve the same. The novel equivalent circuit that works with DMR systems performs the function of extracting the correct output from the DMR design. Further, the proposed work is the first work in the literature that handles multi-cycle transient faults during design space exploration of fault tolerant datapath. Therefore, key contributions of this paper are as follows: (a) novel multi-cycle transient fault tolerant algorithm that has capability to isolate original and duplicate units in a DMR with respect to the transient fault; (b) novel DSE approach that combines our fault tolerant algorithm along with user specified conflicting power-performance constraint that guides this intractable search problem to reach an high quality fault tolerant solution without violating the power budget and delay requirement; (c) integrates a heuristic based on bacterial foraging optimization algorithm (BFOA) that performs adaptive searching. Finally, results indicated an average improvement in Quality of Results (QoR) of >24% and reduction in hardware usage of >57% of the final solution compared to similar approach.

Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing

A novel automated design space exploration (DSE) approach of multi-cycle transient fault detectable datapath based on multi-objective user constraints (power and delay) for application specific computing is presented in this paper. To the best of the authors’ knowledge, this is the first work in the literature to solve this problem. The presented approach, driven by bacterial foraging optimization (BFO) algorithm provides easy flexibility to change direction in the design space through tumble/swim actions if a search path is found ineffective. The approach is highly capable of reaching true Pareto optimal curve indicated by the closeness of our non-dominated solutions to the true Pareto front and their uniform distribution over the Pareto curve (implying diversity). The contributions of this paper are as follows: (a) novel exploration approach for generating a high quality fault detectable structure based on user provided requirements of power-delay, which is capable of transient error detection in the datapath; (b) novel fault detectable algorithm for handling single and multi-cycle transient faults.The results of the proposed approach indicated an average improvement in Quality of Results (QoR) of >9% and reduction in hardware usage of >23% compared to recent approaches that are closer in solving a similar objective.

Exploration of compiler optimization sequences using clustering-based selection

Due to the large number of optimizations provided in modern compilers and to compiler optimization specific opportunities, a Design Space Exploration (DSE) is necessary to search for the best sequence of compiler optimizations for a given code fragment (e.g., function). As this exploration is a complex and time consuming task, in this paper we present DSE strategies to select optimization sequences to both improve the performance of each function and reduce the exploration time. The DSE is based on a clustering approach which groups functions with similarities and then explore the reduced search space provided by the optimizations previously suggested for the functions in each group. The identification of similarities between functions uses a data mining method which is applied to a symbolic code representation of the source code. The DSE process uses the reduced set identified by clustering in two ways: as the design space or as the initial configuration. In both ways, the adoption of a pre-selection based on clustering allows the use of simple and fast DSE algorithms. Our experiments for evaluating the effectiveness of the proposed approach address the exploration of compiler optimization sequences considering 49 compilation passes and targeting a Xilinx MicroBlaze processor, and were performed aiming performance improvements for 41 functions. Experimental results reveal that the use of our new clustering-based DSE approach achieved a significant reduction on the total exploration time of the search space (18x over a Genetic Algorithm approach for DSE) at the same time that important performance speedups (43% over the baseline) were obtained by the optimized codes.