Applied Gate Bias Research Articles

Trap States of the Oxide Thin Film Transistor

We investigated the temperature dependent recovery of the threshold voltage shift observed in both ZnO and indium gallium zinc oxide (IGZO) thin film transistors (TFTs) after application of gate bias and light illumination. Two types of recovery were observed for both the ZnO and IGZO TFTs; low temperature recovery (below 110 °C) which is attributed to the trapped charge and high temperature recovery (over 110 °C) which is related to the annihilation of trap states generated during stresses. From a comparison study of the recovery rate with the analysis of hydrogen diffusion isochronal annealing, a similar behavior was observed for both TFT recovery and hydrogen diffusion. This result suggests that hydrogen plays an important role in the generation and annihilation of trap states in oxide TFTs under gate bias or light illumination stresses.

A passive UHF RFID tag with a dynamic-Vth-cancellation rectifier

This paper presents a passive UHF RFID tag with a dynamic-Vth-cancellation (DVC) rectifier. In the rectifier, the threshold voltages of MOSFETs are cancelled by applying gate bias voltages, which are dynamically changed according to the states of the MOSFETs. The DVC rectifier enables both low ON-resistance and small reverse leakage of the MOSFETs, resulting in high power conversion efficiency (PCE). An area-efficient demodulator with a novel average detector is also designed, which takes advantage of the rectifier's first stage as the envelope detector. The whole tag chip is implemented in a 0.18 μm CMOS process with a die size of 880 × 950 μm2. Measurement results show that the rectifier achieves a maximum PCE of 53.7% with 80 kΩ resistor load.

Hard x-ray photoelectron spectroscopy and electrical characterization study of the surface potential in metal/Al2O3/GaAs(100) metal-oxide-semiconductor structures

Hard x-ray photoelectron spectroscopy (HAXPES) has been used to study metal-oxide-semiconductor (MOS) structures fabricated with both high (Ni) and low (Al) work-function metals on 8-nm thick Al${}_{2}$O${}_{3}$ dielectric layers, deposited on sulfur passivated $n$- and $p$-doped GaAs substrates. A binding energy difference of 0.6 eV was measured between the GaAs core levels of the $n$- and $p$-doped substrates in the absence of gate metals, indicating different Fermi level positions in the band gap. Subsequent photoemission measurements made on the MOS structures with the different work-function metals displayed very limited change in the GaAs core level binding energies, indicating that the movement of the Fermi level at the Al${}_{2}$O${}_{3}$/GaAs interface is restricted. Using a combination of HAXPES measurements and theoretical calculations, the Fermi level positions in the band gap have been determined to be in the range of 0.4--0.75 eV and 0.8--1.11 eV above the valence band maximum for $p$- and $n$-type GaAs, respectively. Analysis of capacitance voltage (C-V) measurements on identically prepared samples yield very similar Fermi level positions at zero applied gate bias. The C-V analysis also indicates a higher interface defect density ($D$${}_{it}$) in the upper half of the GaAs bandgap.

Amorphous InGaZnO ultraviolet phototransistors with double-stack Ga2O3/SiO2 dielectric

This study investigates the electrical performance of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors with Ga2O3 gate dielectric and applied on deep-ultraviolet phototransistors. To reduce the leakage current, we introduce the SiO2 interlayer dielectric, which effectively reduces the off-current. Under the illumination of 250 nm, the measured responsivity of the device was 3.2 A/W at an applied gate bias of 0 V. The photo-generated carriers were injected into the channel by the applied electric field and Fowler-Nordheim tunneling. A large photocurrent and responsivity can be obtained which is attributed to the high mobility of the a-IGZO channel.

Low Leakage Current and High-Cutoff Frequency AlGaN/GaN MOSHEMT Using Submicrometer-Footprint Thermal Oxidized TiO2/NiO as Gate Dielectric

AlGaN/GaN metal oxide semiconductor high electron mobility transistors (MOSHEMTs) with thick (>35 nm), high-κ (TiO2/NiO), submicrometer-footprint (0.4 μm) gate dielectric are found to exhibit two orders of magnitude in lower gate leakage current (~1 nA/mm up to +3-V applied gate bias), higher IMAX (709 mA/mm), and higher drain breakdown voltage, compared to Schottky barrier (SB) HEMTs of the same geometry. The maximum extrinsic transconductance of both the MOSHEMTs and the SBHEMTs with 2 × 80-μm gate fingers is measured to be 149 mS/mm. The addition of the submicrometerfootprint gate oxide layer only results in a small reduction of the current gain cutoff frequency (21 versus 25 GHz, derived from S-parameter test data) because of the high permittivity (κ ≈ 100) of the gate dielectric. This high-performance submicrometer-footprint MOSHEMT is highly promising for microwave power amplifier applications in communication and radar systems.

Solitonic Dirac fermion wave guide networks on topological insulator surfaces

Magnetic texturing on the surface of a topological insulator allows the design of wave guide networks and beam splitters for domain-wall Dirac fermions. Guided by simple analytic arguments, we model a Dirac domain-wall fermion interferometer consisting of two parallel pathways imprinted by solitonic ferromagnetic texturing. A specially developed staggered-grid leap-frog discretization scheme in 2 + 1 dimensions with absorbing boundary conditions is employed to study the interferometer in an open device geometry. Its net transmission can be tuned from constructive to destructive interference, either by variation of the magnetization texture (effective path length) or an applied gate bias (wavelength). Possible ways to observe and utilize this effect are discussed.

Manipulating the Hysteresis in Poly(vinyl alcohol)‐Dielectric Organic Field‐Effect Transistors Toward Memory Elements

AbstractThe origins of hysteresis in organic field‐effect transistors (OFETs) and its applications in organic memory devices is investigated. It is found that the orientations of the hydroxyl groups in poly(vinyl alcohol) (PVA) gate dielectrics are correlated with the hysteresis of transfer characteristics in pentacene‐based OFETs under the forward and backward scan. The applied gate bias partially aligns the orientations of the hydroxyl groups perpendicular to the substrate as characterized by reflective absorption Fourier transform infrared spectroscopy (RA‐FTIR), in which the field‐induced surface dipoles at the pentacene/PVA interface trap charges and cause the hysteresis. Treating PVA with an anhydrous solvent eliminates the residual moisture in the dielectrics layer, allowing for more effective control of the induced dipoles by the applied gate bias. OFETs of dehydrated‐PVA dielectrics present a pronounced shift of the threshold voltage (ΔVTh) of 35.7 V in transfer characteristics, higher than that of 18.5 V for untreated devices and results in sufficient dynamic response for applications in memory elements. This work highlights the usage of non‐ferroelectric gate dielectrics to fabricate OFET memory elements by manipulating the molecular orientations in the dielectrics layer.

SymFET: A Proposed Symmetric Graphene Tunneling Field-Effect Transistor

In this work, an analytical model to calculate the channel potential and current-voltage characteristics in a Symmetric tunneling Field-Effect-Transistor (SymFET) is presented. The current in a SymFET flows by tunneling from an n-type graphene layer to a p-type graphene layer. A large current peak occurs when the Dirac points are aligned at a particular drain-to- source bias VDS . Our model shows that the current of the SymFET is very weakly dependent on temperature. The resonant current peak is controlled by chemical doping and applied gate bias. The on/off ratio increases with graphene coherence length and doping. The symmetric resonant peak is a good candidate for high-speed analog applications, and can enable digital logic similar to the BiSFET. Our analytical model also offers the benefit of permitting simple analysis of features such as the full-width-at-half-maximum (FWHM) of the resonant peak and higher order harmonics of the nonlinear current. The SymFET takes advantage of the perfect symmetry of the bandstructure of 2D graphene, a feature that is not present in conventional semiconductors.

High responsivity of amorphous indium gallium zinc oxide phototransistor with Ta2O5 gate dielectric

This study investigates the electrical performance of amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) with a Ta2O5 gate dielectric under monochromatic illumination. The relationship between the phototransistor performance and oxygen partial pressure is determined. The oxygen content of the a-IGZO channel significantly affects the electrical and optical characteristics of a-IGZO TFTs. At applied gate biases of 0, 0, and 0.25 V, oxygen partial pressures of 0%, 0.1%, and 0.2% yielded measured device responsivities of 0.23, 0.44, and 4.75 A/W, respectively. Oxygen content can be used to control the mobility of TFTs, which can amplify photocurrent and enhance the responsivity of a-IGZO TFTs with a Ta2O5 gate dielectric.

Charge pumping and DCIV currents in SOI FinFETs

Charge pumping (ACIV) and direct current–voltage (DCIV) measurements were performed on standard floating-body n-channel FinFETs. The resulting recombination currents are monitored directly at the drain and source contacts, and are found to depend strongly on frequency, gate voltage, and FinFET geometry. The DCIV current reaches a maximum when the body potential transitions from accumulation to inversion in response to the applied gate bias and the body-to-source and body-to-drain diodes become forward biased. The ACIV current is dominated by contributions from interface traps when the surface potential is swept from accumulation to inversion during the gate pulse. It is sensitive to recombination currents at the body-to-source and body-to-drain diodes at intermediate voltage levels. At the highest applied gate voltages, band-to-band tunneling is also observed. We demonstrate that the change in ACIV current with frequency before and after electrical stress allows charge-pumping estimates of stress-induced interface trap densities in standard SOI FinFETs without body contacts.

Does the low hole transport mass in 〈110〉 and 〈111〉 Si nanowires lead to mobility enhancements at high field and stress: A self-consistent tight-binding study

The hole surface roughness and phonon limited mobility in the silicon 〈100〉, 〈110〉, and 〈111〉 square nanowires under the technologically important conditions of applied gate bias and stress are studied with the self-consistent Poisson-sp3d5s*-SO tight-binding bandstructure method. Under an applied gate field, the hole carriers in a wire undergo a volume to surface inversion transition diminishing the positive effects of the high 〈110〉 and 〈111〉 valence band nonparabolicities, which are known to lead to the large gains of the phonon limited mobility at a zero field in narrow wires. Nonetheless, the hole mobility in the unstressed wires down to the 5 nm size remains competitive or shows an enhancement at high gate field over the large wire limit. Down to the studied 3 nm sizes, the hole mobility is degraded by strong surface roughness scattering in 〈100〉 and 〈110〉 wires. The 〈111〉 channels are shown to experience less surface scattering degradation. The physics of the surface roughness scattering dependence on wafer and channel orientations in a wire is discussed. The calculated uniaxial compressive channel stress gains of the hole mobility are found to reduce in the narrow wires and at the high field. This exacerbates the stressed mobility degradation with size. Nonetheless, stress gains of a factor of 2 are obtained for 〈110〉 wires down to 3 nm size at a 5×1012 cm–2 hole inversion density per gate area.

Re-Examination of Performance and Reliability Degradation in Metal–Oxide–Nitride–Oxide–Semiconductor Memory with Ultrathin SiN Charge Trap Layers

We demonstrated that the degradation of program characteristics in metal–oxide–nitride–oxide–semiconductor (MONOS) devices consisting of an ultrathin (∼2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.

Re-Examination of Performance and Reliability Degradation in Metal–Oxide–Nitride–Oxide–Semiconductor Memory with Ultrathin SiN Charge Trap Layers

We demonstrated that the degradation of program characteristics in metal–oxide–nitride–oxide–semiconductor (MONOS) devices consisting of an ultrathin (∼2 nm) SiN charge trap layer is due to a decrease in the electron capture efficiency, instead of a reduction in the number of available trap sites. From the data retention properties with applied gate bias voltage, we clarified that charge loss through the tunnel layer during data retention becomes more significant with decreasing SiN thickness. These results indicate that to improve the performance and reliability of MONOS devices with an ultrathin SiN charge trap layer, measures must be taken to enhance the capture cross section of the traps and to inhibit carrier motion in the SiN layer simultaneously.

Hole effective masses of p-type metal-oxide-semiconductor inversion layer in strained Si1-xGex alloys channel on (110) and (111) Si substrates

Valence subband properties and hole effective masses of PMOS inversion layer in strained Si1-xGex alloys channel on (110) and (111) Si substrates are studied theoretically based on the Luttinger-Kohn Hamiltonian. The subband structures under investigation are a result of the quantized levels produced by the triangular quantum well in the inversion layer created by the applied gate bias in the z-direction. Valence subband properties including constant-energy-contours, density-of-states, quantized effective mass in the z-direction mz, carrier concentration effective mass mcc, and conductivity effective mass mσ are calculated as functions of the Ge concentration at gate electric field of 1 MV/cm. An analytic expression for the Fermi level is derived in terms of mcc, the total hole concentration, and subband edges. Our results show that in general mσ in the (110) system is lower than that in the (111) substrate orientation, which implies that (110) Si substrate is more favorable for carrier transport. Furthermore, mσ in the [−110] direction of the (110) Si substrate system are the lightest among all other cases.

Charge transport in dual-gate organic field-effect transistors

The charge carrier distribution in dual-gate field-effect transistors is investigated as a function of semiconductor thickness. A good agreement with 2-dimensional numerically calculated transfer curves is obtained. For semiconductor thicknesses larger than the accumulation width, two spatially separated channels are formed. The cross-over from accumulation into depletion of the two channels in combination with a carrier density dependent mobility causes a shoulder in the transfer characteristics. A semiconducting monolayer has only a single channel. The charge carrier density, and consequently the mobility, are virtually constant and change monotonically with applied gate biases, leading to transfer curves without a shoulder.

Elimination of surface leakage in gate controlled type-II InAs/GaSb mid-infrared photodetectors

The electrical performance of mid-infrared type-II superlattice M-barrier photodetectors is shown to be limited by surface leakage. By applying gate bias on the mesa sidewall surface, leakage current is significantly reduced. Qualitatively IV modeling shows diffusion-dominated behavior of dark current at temperatures greater than 120 K. At 110 K, the dark current of gated device is reduced by more than 2 orders of magnitude, reaching the measurement system noise floor. With a quantum efficiency of 48% in front side illumination configuration, a 4.7μm cut-off gated device attains a specific detectivity of 2.5 × 1014 cmHz1/2/W at 110 K, which is 3.6 times higher than in ungated devices.

Nonlinear Spectroscopic Markers of Structural Change during Charge Accumulation in Organic Field-Effect Transistors

Vibrational sum frequency generation (VSFG) is used to characterize the buried polymer–dielectric interface in poly(triarylamine) (PTAA) organic field-effect transistors (oFETs) over a spectral range of more than 1100 cm–1. The FTIR and Raman spectra are presented for the neutral and chemically oxidized thin films of this polymer as a starting point for identifying the potential vibrational changes that are induced by doping. In the VSFG spectra collected as a function of applied gate bias, we find evidence for interfacial electric fields, polaronic absorbances, and a strong VSFG-active band that is a spectral signature of the interfacial molecules that are perturbed by electrical doping. In most cases, the unipolar electrical behavior of PTAA oFETs is directly correlated with intensity changes in this structural perturbation band regardless of the dielectric (SiO2) surface functionalization. However, in a few selected examples, the VSFG measurements demonstrate that accumulation of either holes or electrons can be achieved with this organic semiconductor, even in the absence of measurable source-drain currents. These results highlight the potential for PTAA to achieve ambipolar device operation and the power of nonlinear spectroscopy to provide the feedback needed to optimize this performance when electrical measurements cannot.

Influence of the semiconductor oxidation potential on the operational stability of organic field-effect transistors

During prolonged application of a gate bias, organic field-effect transistors show a gradual shift of the threshold voltage towards the applied gate bias voltage. The shift follows a stretched-exponential time dependence governed by a relaxation time. Here, we show that a thermodynamic analysis reproduces the observed exponential dependence of the relaxation time on the oxidation potential of the semiconductor. The good fit with the experimental data validates the underlying assumptions. It demonstrates that this operational instability is a straightforward thermodynamically driven process that can only be eliminated by eliminating water from the transistor.

Transport mechanism in ambipolar pentacene organic thin film transistors with lithium fluoride gate dielectric

The electrical properties of organic thin film transistors (OTFTs) based on pentacene as the active layer and lithium fluoride (LiF) as the gate dielectric layer were investigated. Fabricated devices exhibited ambipolar behavior that can be controlled by the applied source, drain and gate biases. It was found that at low source-drain biases, multistep hopping is the dominant conduction mechanism, whereas in high voltage regimes, I-V data fits in the Fowler-Nordheim (FN) tunneling model. The relationship between the applied gate bias and the field enhancement factor, which is the ratio of the local surface electric field to the applied electric field, were determined from the slope of the FN plots. The dependency between the transition points in conduction mechanism upon gate bias has also been extracted from the FN plots. The transition points show more dependency on gate voltage for negative biases compared to the positive biases.

Reduction of Charge Trapping Sites in Al<sub>2</sub>O<sub>3</sub>/SiO<sub>2</sub> Stacked Gate Dielectrics by Incorporating Nitrogen for Highly Reliable 4H-SiC MIS Devices

Superior flatband voltage (Vfb) stability of SiC-based metal-insulator-semiconductor (MIS) devices with aluminum oxynitride (AlON) gate dielectrics was demonstrated. MIS capacitors with gate insulators consisting of a thick pure aluminum oxide (Al2O3) and a thin underlying SiO2 layer fabricated on n-type 4H-SiC substrates showed a positive Vfb shift due to substrate electron injection depending on the applied gate bias and the thickness of the SiO2 interlayer. This large Vfb shift was greatly suppressed for devices with AlON/SiO2 stacked gate dielectrics, suggesting that electron trapping sites in Al2O3 film were mostly compensated for by nitrogen incorporation. This finding is helpful in realizing highly reliable SiC-based MIS field-effect-transistors (MISFETs) in terms of threshold voltage stability.