Applications In VLSI Design Research Articles

Tiling with Squares and Packing Dominos in Polynomial Time

A polyomino is a polygonal region with axis-parallel edges and corners of integral coordinates, which may have holes. In this paper, we consider planar tiling and packing problems with polyomino pieces and a polyomino container P . We give polynomial-time algorithms for deciding if P can be tiled with k × k squares for any fixed k which can be part of the input (that is, deciding if P is the union of a set of non-overlapping k × k squares) and for packing P with a maximum number of non-overlapping and axis-parallel 2 × 1 dominos, allowing rotations by 90°. As packing is more general than tiling, the latter algorithm can also be used to decide if P can be tiled by 2 × 1 dominos. These are classical problems with important applications in VLSI design, and the related problem of finding a maximum packing of 2 × 2 squares is known to be NP-hard [ 6 ]. For our three problems there are known pseudo-polynomial-time algorithms, that is, algorithms with running times polynomial in the area or perimeter of P . However, the standard, compact way to represent a polygon is by listing the coordinates of the corners in binary. We use this representation, and thus present the first polynomial-time algorithms for the problems. Concretely, we give a simple O(n log n )-time algorithm for tiling with squares, where n is the number of corners of P . We then give a more involved algorithm that reduces the problems of packing and tiling with dominos to finding a maximum and perfect matching in a graph with O ( n 3 ) vertices. This leads to algorithms with running times \(O(n^3 \frac{\log ^3 n}{\log ^2\log n})\) and \(O(n^3 \frac{\log ^2 n}{\log \log n})\) , respectively.

MEACCP: A membrane evolutionary algorithm for capacitated clustering problem

The Capacitated Clustering Problem (CCP) is a constrained clustering problem with a wide range of applications in VLSI design, vehicle routing, and mail delivery. In order to improve the performance of solving CCP, this paper proposes a membrane evolutionary algorithm MEACCP based on the Membrane Evolutionary Algorithm Framework (MEAF). First, the membrane structure of MEACCP and its object representation are designed. Second, six evolution operators are designed to evolve objects within the membrane and membrane structures. Third, the MEACCP and the method of membrane population initialization are discussed. Finally, MEACCP experiments were conducted on 100 instances of four different types of benchmark datasets, and the experimental results were compared with the results of the current state-of-the-art CCP algorithms. The experimental results show that the number of instances where MEACCP can find the optimal solution is 4.3 ∼ 9.1 times that of the algorithms in comparison, and the stability is better than all comparison algorithms.

The minimum degree Group Steiner problem

The DB-GST problem is given an undirected graph G(V,E), and a collection of groups S={Si}i=1q,Si⊆V, find a tree that contains at least one vertex from every group Si, so that the maximum degree is minimal. This problem was motivated by On-Line algorithms Hajiaghayi (2016), and has applications in VLSI design and fast Broadcasting. In the WDB-GST problem, every vertex v has individual degree bound dv, and every e∈E has a cost c(e)>0. The goal is, to find a tree that contains at least one terminal from every group, so that for every v, degT(v)≤dv, and among such trees, find the one with minimum cost. We give the first approximation for this problem, an (O(log2n),O(log2n)) bicriteria approximation ratio the WDB-GST problem on trees inputs. This implies an O(log2n) approximation for DB-GST on tree inputs. The previously best known ratio for the WDB-GST problem on trees was a bicriterion (O(log2n),O(log3n)) (the approximation for the degrees is O(log3n)) ratio which is folklore. Getting O(log2n) approximation requires careful case analysis and was not known.Our result for WDB-GST generalizes the classic result of Garg et al. (2016) that approximated the cost within O(log2n), but did not approximate the degree.Our main result is an O(log3n) approximation for BD-GST on Bounded Treewidth graphs.The DB-Steiner k-tree problem is given an undirected graph G(V,E), a collection of terminals S⊆V, and a number k, find a tree T(V′,E′) that contains at least k terminals, of minimum maximum degree. We prove that if the DB-GST problem admits a ρ ratio approximation, then the DB-Steiner k-tree problem, admits an O(log2k⋅ρ) expected approximation. We also show that if there are k groups, there exists an algorithm that is able to coverk/4 of the groups with minimum maximal degree, then there is a deterministic O(logn⋅ρ) approximation for DB-Steiner k-tree problem. Using the work of Guo et al. (2020) we derive an O(log3n) approximation for DB-Steiner k-tree problem on general graphs, that runs in quasi-polynomial time.

A local search method based on edge age strategy for minimum vertex cover problem in massive graphs

Minimum vertex cover problem (MVC) is a classic combinatorial optimization problem, which has many critical real-life applications in scheduling, VLSI design, artificial intelligence, and network security. For MVC, researchers have proposed many heuristic algorithms, especially local search algorithms. And recently, researchers have increased their interest in solving large real-world graphs which require algorithms with faster searching performance. In this work, we propose a new edge weighting method called EABMS. EABMS has a time complexity of O(1). Based on EABMS, we propose our MVC solver framework called EAVC in solving MVC for massive graphs. We conducted experiments and compared the results of EAVC solvers with state of the art solvers. The results show that EABMS is effective in weighing edges for large sparse graphs and EAVC solvers outperform state of the art solvers.

A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator

In low-power VLSI design applications non-linearity and harmonics are a major dominant factor which affects the performance of the ADC. To avoid this, the new architecture of voltage-controlled oscillator (VCO) was required to solve the non-linearity issues and harmonic distortion. In this work, a 12-bit, 200MS/s low power delta-sigma analog to digital converter (ADC) VCO based quantizer was designed using switched capacitor technique. The proposed technique uses frequency to current conversion technique as a linearization method to reduce the non-linearity issue. Simulation result show that the proposed 12-bit delta-sigma ADC consumes the power of 2.68 mW and a total area of 0.09 mm² in 90 nm CMOS process.

Hypergraph clustering by iteratively reweighted modularity maximization

Learning on graphs is a subject of great interest due to the abundance of relational data from real-world systems. Many of these systems involve higher-order interactions (super-dyadic) rather than mere pairwise (dyadic) relationships; examples of these are co-authorship, co-citation, and metabolic reaction networks. Such super-dyadic relations are more adequately modeled using hypergraphs rather than graphs. Learning on hypergraphs has thus been garnering increased attention with potential applications in network analysis, VLSI design, and computer vision, among others. Especially, hypergraph clustering is gaining attention because of its enormous applications such as component placement in VLSI, group discovery in bibliographic systems, image segmentation in CV, etc. For the problem of clustering on graphs, modularity maximization has been known to work well in the pairwise setting. Our primary contribution in this article is to provide a generalization of the modularity maximization framework for clustering on hypergraphs. In doing so, we introduce a null model for graphs generated by hypergraph reduction and prove its equivalence to the configuration model for undirected graphs. The proposed graph reduction technique preserves the node degree sequence from the original hypergraph. The modularity function can be defined on a thus reduced graph, which can be maximized using any standard modularity maximization method, such as the Louvain method. We additionally propose an iterative technique that provides refinement over the obtained clusters. We demonstrate both the efficacy and efficiency of our methods on several real-world datasets.

An efficient metaheuristic for the [formula omitted]-page crossing number minimization problem

Graph layout problems refer to a family of optimization problems with relevant applications in VLSI design, information retrieval, numerical analysis, computational biology, or graph theory. In this paper, we focus on a variant where the graph is mapped over a specific structure referred to as book, which consists of a spine and a number of pages. Vertices of the graph are allocated in the spine, which is usually represented as a line, and edges are assigned to pages of the book, which are represented as half-planes that have the spine as its boundary. The experience shows that one of the main quality desired for layout of graphs is the minimization of edge crossing. The K-page crossing number minimization problem (KPMP) aims to reduce as much as possible the number of crossings between edges belonging to the same page. We propose the application of the VNS metaheuristic to efficiently solve the KPMP. Experiments show a remarkable improvement over the state-of-the-art procedures for a large set of instances, leading the proposed VNS algorithm as a promising strategy to solve this family of book drawing problems.

A heuristic for the minimum cost chromatic partition problem

The graph coloring problem consists in coloring the vertices of a graphG=(V, E)with a minimum number of colors, such as that any two adjacent vertices receive different colors. The minimum cost chromatic partition problem (MCCPP) is an extension of the graph coloring problem in which there are costs associated with the colors and one seeks a vertex coloring minimizing the sum of the costs of the colors used in each vertex. The problem finds applications in VLSI design and in some scheduling problems modeled on interval graphs. We propose a trajectory search heuristic using local search, path-relinking, and perturbations for solving MCCPP and discuss computational results.

Polynomial Time Efficient Construction Heuristics for Vertex Separation Minimization Problem

Vertex Separation Minimization Problem (VSMP) consists of finding a layout of a graph G = (V, E) which minimizes the maximum vertex cut or separation of a layout. It is an NP-complete problem in general for which metaheuristic techniques can be applied to find near optimal solution. VSMP has applications in VLSI design, graph drawing and computer language compiler design. VSMP is polynomially solvable for grids, trees, permutation graphs and cographs. Construction heuristics play a very important role in the metaheuristic techniques as they are responsible for generating initial solutions which lead to fast convergence. In this paper, we have proposed three construction heuristics H1, H2 and H3 and performed experiments on Grids, Small graphs, Trees and Harwell Boeing graphs, totaling 248 instances of graphs. Experiments reveal that H1, H2 and H3 are able to achieve best results for 88.71%, 43.5% and 37.1% of the total instances respectively while the best construction heuristic in the literature achieves the best solution for 39.9% of the total instances. We have also compared the results with the state-of-the-art meta-heuristic GVNS and observed that the proposed construction heuristics improves the results for some of the input instances. It was found that GVNS obtained best results for 82.9% instances of all input instances and the heuristic H1 obtained best results for 82.3% of all input instances.

A Maximum Weight Clique Algorithm For Dense Circle Graphs With Many Shared Endpoints

Circle graphs are derived from the intersections of a set of chords. They have applications in VLSI design, bioinformatics, and chemistry. Some intractable problems on general graphs can be solved in polynomial time on circle graphs. As such, the study of circle graph algorithms has received attention. State-of-the-art algorithms for finding the maximum weight clique of a circle graph are very efficient when the graph is sparse. However, these algorithms require $\Theta(n^2)$ time when the graph is dense. We present an algorithm that is a factor of $\sqrt{n}$ faster for dense graphs in which many chord endpoints are shared. We also argue that these assumptions are practical.

Clustering problems in a multiobjective framework

We propose a new algorithm using tabu search to deal with biobjective clustering problems. A cluster is a collection of records that are similar to one other and dissimilar to records in other clusters. Clustering has applications in VLSI design, protein-protein interaction networks, data mining and many others areas. Clustering problems have been subject of numerous studies; however, most of the work has focused on single-objective problems. In the context of multiobjective optimization our aim is to find a good approximation to the Pareto front and provide a method to make decisions. As an application problem we present the zoning problem by allowing the optimization of two objectives.

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim

With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have been applied earlier in different engineering disciplines as potentially good optimization tools and for various applications in VLSI design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at-faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.

Virtex 4 FPGA Implementation of Viterbi Decoded 64-bit RISC for High Speed Application using Xilinx

modern era of electronics and communication decoding and encoding of any data(s) using VLSI technology requires low power, less area and high speed constrains. The viterbi decoder using survivor path with necessary parameters for wireless communication is an attempt to reduce the power and cost and at the same time increase the speed compared to normal decoder. This paper presents three objectives. Firstly, an orthodox viterbi decoder is designed and simulated. For faster process application, the Gate Diffused Input Logic (GDIL) based viterbi decoder is designed using Xilinx ISE, simulated and synthesized successfully. The new proposed GDIL viterbi provides very less path delay with low power simulation results. Secondly, the GDIL viterbi is again compared with our proposed technique, which comprises a Survivor Path Unit (SPU) implements a trace back method with DRAM. This proposed approach of incorporating DRAM stores the path information in a manner which allows fast read access without requiring physical partitioning of the DRAM. This leads to a comprehensive gain in speed with low power effects. Thirdly, all the viterbi decoders are compared, simulated, synthesized and the proposed approach shows the best simulation and synthesize results for low power and high speed application in VLSI design. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder(s) have been operated in deep pipelined manner to achieve high transmission rate. Although the register exchange based survivor unit has better throughput when compared to trace back unit, but in this paper by introducing the RAM cell between the ACS array and output register bank, a significant amount of reduction in path delay has been observed. All the designing of viterbi is done using Xilinx ISE 12.4 and synthesized successfully in the FPGA Virtex 4 target device operated at 64.516 MHz clock frequency, reduces almost 41% of total path delay. Keywordsdecoder, GDIL technique, SPU, DRAM, Add Compare Select (ASC), Trace Back (TB), Xilinx, FPGA.

Combining intensification and diversification strategies in VNS. An application to the Vertex Separation problem

The Vertex Separation problem (VSP) is an NP-hard problem with practical applications in VLSI design, graph drawing and computer language compiler design. VSP belongs to a family of optimization problems in which the objective is to find the best separator of vertices or edges in a generic graph. In this paper, we propose different heuristic methods and embed them into a Variable Neighborhood Search scheme to solve this problem. More precisely, we propose (i) a constructive algorithm, (ii) four shake procedures, (iii) two neighborhood structures, (iv) efficient algorithmic strategies to explore them, (v) an extended version of the objective function to facilitate the search process and finally, (vi) we embed these strategies in a Reduced Variable Neighborhood Search (RVNS), a Variable Neighborhood Descent (VND) and a General Variable Neighborhood Search (GVNS). Additionally, we provide an extensive experimental comparison among them and with the best previous method of the literature. We consider three different benchmarks, totalizing 162 representative instances. The experimentation reveals that our best procedure (GVNS) improves the state of the art in both quality and computing time. This fact is confirmed by non-parametric statistical tests. In addition, when considering only the largest instances, the other two proposed variants (RVNS and VND) also obtain statistically significant differences with respect to the best previous method identified in the state of the art.

A HIGH-PERFORMANCE AND LOW-POWER DELAY BUFFER

In this paper, presents circuit design of a low-power delay buffer. The proposed delay buffer uses several new techniques to reduce its power consumption. Since delay buffers are accessed sequentially, it adopts a ring-counter addressing scheme. In the ring counter, double-edge-triggered (DET) flip-flops are utilized to reduce the operating frequency by half and the C-element gated-clock strategy is proposed. Both total transistor count and the number of clocked transistors are significantly reduced to improve power consumption and speed in the flip-flop. The number of transistors is reduced by 56%-60% and the Area-Speed-Power product is reduced by 56%-63% compared to other double edge triggered flip-flops. This design is suitable for high-speed, low-power CMOS VLSI design applications.

A Variable Neighbourhood Search approach to the Cutwidth Minimization Problem

Abstract The Cutwidth Minimization Problem, also known as the Minimum Cut Linear Arrangement consists of finding an arrangement of the vertices of a graph on a line, in such a way that the maximum number of edges between each pair of consecutive vertices is minimized. This problem has practical applications in VLSI Design, Network Migration and Graph Drawing, among others. In this paper we propose several heuristics based on the Variable Neighbourhood Search methodology to tackle the problem and we compare them with other state-of-the-art methods.

Approximations for two variants of the Steiner tree problem in the Euclidean plane $${\mathbb{R}^2}$$

Given n terminals in the Euclidean plane and a positive constant l, find a Steiner tree T interconnecting all terminals with the minimum total cost of Steiner points and a specific material used to construct all edges in T such that the Euclidean length of each edge in T is no more than l. In this paper, according to the cost b of each Steiner point and the different costs of some specific materials with the different lengths, we study two variants of the Steiner tree problem in the Euclidean plane as follows: (1) If a specific material to construct all edges in such a Steiner tree has its infinite length and the cost of per unit length of such a specific material used is c1, the objective is to minimize the total cost of the Steiner points and such a specific material used to construct all edges in T, i.e., \({{\rm min} \{b \cdot k_1+ c_1 \cdot \sum_{e \in T} w(e)\}}\), where T is a Steiner tree constructed, k1 is the number of Steiner points and w(e) is the length of part cut from such a specific material to construct edge e in T, and we call this version as the minimum-cost Steiner points and edges problem (MCSPE, for short). (2) If a specific material to construct all edges in such a Steiner tree has its finite length L (l ≤ L) and the cost of per piece of such a specific material used is c2, the objective is to minimize the total cost of the Steiner points and the pieces of such a specific material used to construct all edges in T, i.e., \({{\rm min} \{b \cdot k_2+ c_2 \cdot k_3\}}\), where T is a Steiner tree constructed, k2 is the number of Steiner points in T and k3 is the number of pieces of such a specific material used, and we call this version as the minimum-cost Steiner points and pieces of specific material problem (MCSPPSM, for short). These two variants of the Steiner tree problem are NP-hard with some applications in VLSI design, WDM optical networks and wireless communications. In this paper, we first design an approximation algorithm with performance ratio 3 for the MCSPE problem, and then present two approximation algorithms with performance ratios 4 and 3.236 for the MCSPPSM problem, respectively.

On the Graph Bisection Cut Polytope

Given a graph $G=(V,E)$ with node weights $\varphi_v \in \mathbb{N}\cup\{0\}$, $v\in V$, and some number $F\in \mathbb{N}\cup\{0\}$, the convex hull of the incidence vectors of all cuts $\delta(S)$, $S\subseteq V$, with $\varphi(S)\le F$ and $\varphi(V\setminus S)\le F$ is called the bisection cut polytope. We study the facial structure of this polytope which shows up in many graph partitioning problems with applications in VLSI design or frequency assignment. We give necessary and in some cases sufficient conditions for the knapsack tree inequalities introduced in [C. E. Ferreira et al., Math. Programming, 74 (1996), pp. 247-267] to be facet-defining. We extend these inequalities to a richer class by exploiting the fact that each cut intersects each cycle in an even number of edges. Finally, we present a new class of inequalities that are based on nonconnected substructures yielding nonlinear right-hand sides. We show that the supporting hyperplanes of the convex envelope of this nonlinear function correspond to the faces of the so-called cluster weight polytope, for which we give a complete description under certain conditions.

EFFICIENTLY MAPPING LARGE COMBINATIONAL CIRCUITS ON K-LUT BASED FPGAS

Large combinational circuits need to be partitioned in order to manage scarce resources on k-LUT based FPGAs. Circuit partitioning has multiple applications in VLSI design. One of the most common is that of dividing combinational circuits (usually large ones) that will not fit on a single package among a number of packages. Partitioning is of practical importance for k-LUT based FPGA circuit implementation. In this work is presented a multilevel multi-resource partitioning algorithm for partitioning large combinational circuits using cone-clusters in order to efficiently map existing and commercially available k-LUT based FPGAs packages.

On greedy construction heuristics for the MAX-CUT problem

Given a graph with non-negative edge weights, the MAX CUT problem is to partition the set of vertices into two subsets so that the sum of the weights of edges with endpoints in different subsets is maximised. This classical NP-hard problem finds applications in VLSI design, statistical physics, and classification among other fields. This paper compares the performance of several greedy construction heuristics for MAX-CUT problem. In particular, a new 'worst-out' approach is studied and the proposed edge contraction heuristic is shown to have an approximation ratio of at least 1/3. The results of experimental comparison of the worst-out approach, the well-known best-in algorithm, and modifications for both are also included.