Pattern Matching Applications Research Articles

Study on chess game based on artificial intelligence

With the development of technology and the growth of humans needs, artificial intelligence appears to the sight of the public and wields apparent influence in this world piece by piece, especially under the scheme of automation. There are many applications of artificial intelligence, such as computer games, software design, remote controlling, online meeting and so forth. This research will base on chess and card games, and make corresponding research via pattern matching, Bayesian network and TD algorithm application, making certain analysis to mentality of human and intelligent system. A large quantity of findings has been discovered that many researchers at home and abroad are keenly interested in this field through searching for assortments of relative references, looking through previous research results and inciting part of them. Throughout the world, Alan Turing once discussed the relationship between the next stage and machine intelligence with the paper chess machine. And Arthur Samuel, one of the founders of artificial intelligence, initiated a powerful Checkers Program when he studied and worked in this field. A lot of evidence shows the fact that machine games are one of the most riveting and challenging researches in artificial intelligence. Lots of scholars make some researches for it through kinds of matches and then draw corresponding conclusions.

Design of Ultracompact Content Addressable Memory Exploiting 1T-1MTJ Cell

Content addressable memories (CAMs) are a promising category of computing-in-memory (CiM) elements that can perform highly parallel and efficient search operations for routers, pattern matching, and other data-intensive applications. Various magnetic tunnel junction (MTJ) based content addressable memory (CAM) designs have been proposed to realize zero standby power and high performance search. However, due to the relatively small tunnel magneto-resistance (TMR) ratio, MTJ based CAMs require extra transistors and differential MTJ branches to distinguish between the parallel and anti-parallel resistance states, resulting in significant area and energy overhead. In this paper, we propose a device-circuit co-design approach for an ultra-compact CAM design by only exploiting an 1T-1MTJ structure in each cell. We propose a 2-step search scheme to enable the parallel in-memory search operation across the proposed CAM array, and demonstrate the sufficient sensing margin of the array in a successful search operation. Evaluation results suggest that our proposed 1T-1MTJ based CAM design improves 179X/301X area efficiency compared with the state-of-the-art 15T-4MTJ/20T-6MTJ CAM design. Application benchmarking on hyperdimensional computing (HDC) inference shows a 54.6X/12.8X speedup compared with GPU/20T-6MTJ CAM based approaches.

Communicating Actor Automata - Modelling Erlang Processes as Communicating Machines

Brand and Zafiropulo's notion of Communicating Finite-State Machines (CFSMs) provides a succinct and powerful model of message-passing concurrency, based around channels. However, a major variant of message-passing concurrency is not readily captured by CFSMs: the actor model. In this work, we define a variant of CFSMs, called Communicating Actor Automata, to capture the actor model of concurrency as provided by Erlang: with mailboxes, from which messages are received according to repeated application of pattern matching. Furthermore, this variant of CFSMs supports dynamic process topologies, capturing common programming idioms in the context of actor-based message-passing concurrency. This gives a new basis for modelling, specifying, and verifying Erlang programs. We also consider a class of CAAs that give rise to freedom from race conditions.

An Ultracompact Single‐Ferroelectric Field‐Effect Transistor Binary and Multibit Associative Search Engine

Content addressable memory (CAM) is widely used in associative search tasks due to its parallel pattern matching capability. As more complex and data‐intensive tasks emerge, it is becoming increasingly important to enhance CAM density for improved performance and better area efficiency. To reduce the area overheads, various nonvolatile memory (NVM) devices, such as ferroelectric field‐effect transistors (FeFETs), are used in CAM design. Herein, a novel ultracompact 1FeFET CAM design that enables parallel associative search and in‐memory hamming distance calculation is used, as well as a multibit CAM for exact search using the same CAM cell. The proposed CAM design leverages the 1FeFET1R structure, and compact device designs that integrate the series resistor current limiter into the intrinsic FeFET structure are demonstrated to turn the 1FeFET1R structure into an effective 1FeFET cell. A two‐step search operation of the proposed binary and multibit 1FeFET CAM array through both experiments and simulations is proposed, showing a sufficient sensing margin despite unoptimized FeFET device variation. In genome pattern matching applications, using the hyperdimensional computing paradigm, the design results in a 89.9× speedup and 66.5× improvement in energy efficiency over the state‐of‐the‐art alignment tools on GPU.

Enabling Fast and Memory-Efficient Acceleration for Pattern Matching Workloads: The Lightweight Automata Processing Engine

Growing pattern matching applications are employing finite automata as their basic processing model. These applications match tens to thousands of patterns on a large amount of data, which brings a great challenge to conventional processors. Therefore hardware-based solutions have emerged frequently and achieved high throuphput automata processing. However, existing methods are generally difficult to achieve both processing speed and storage efficiency, and are often too heavy to be integrated into a small chip and have to rely on off-chip DRAMs or other high capacity memories even on some simple data sets, leading to the potential area and power consumption issues. In this paper, we focus on building a more lightweight automata processing engine, hoping to store the whole automata model into on-chip memory and run effectively and independently. We propose LAP, a lightweight automata processing engine. Powered with a novel automata model (A-DFA) and efficient packing algorithms, extremely high storage efficiency compared with traditional DFA is achieved in LAP. Meanwhile, we identify the key parallelization factors in the A-DFA model and then propose a specialized microarchitecture with novel instructions to further accelerate the state transition process. As a result, LAP can obtain more effective trade-off between processing speed and storage efficiency. Evaluation results show that LAP achieves extremely high storage efficiency on simple data sets, exceeding IBM's RegX by 8×, and achieves significant improvements in processing speed ranging from 1.32× to 1.91× compared with previous lightweight hardware implementations. Moreover, LAP has good scalability in hardware architecture. It is easy to build an acceleration system with higher throughput by increasing the number of cores. We prototype a 16-core system into Xilinx ZC702 FPGA and a 64-core system into Xilinx ZCU102 FPGA respectively. The prototype system on ZC702 on average achieves 3.5 GB/s throughput on simple data sets, and the prototype system on ZCU102 can obtain higher throughput and compute density values on part of large datasets in ANMLZoo compared with modern in-memory NFA-based solutions.

Streaming Accelerator Design for Regular Expression on CPU+FPGA Embedded System

A pattern matching application is one of the necessary tasks in streaming data processing. A hardware accelerator employing FPGA can be faster than a general-purpose processor in performing data pattern matching using regular expression methods. However, it is difficult and time-consuming to design the hardware on the FPGA for each regular expression pattern. We are researching a method for automatically designing hardware accelerators for higher efficiency and performance to improve user productivity. In this research, we propose rules and methods for translating regular expression patterns into supported hardware code as our contribution to providing an efficient design method for regular expression hardware accelerators and allowing the efficient utilization of FPGAs. The performance evaluation is compared with the regular expression algorithm on ARM processors, CPU servers, and FPGA data streaming applications. Our result shows that our FPGA accelerator enables speeding up data streaming applications on CPU processors. Our solution is 733 times faster than optimized C/C++ code. It is 70 times faster than using the Python library. It is twice as fast as PYNQ-Z2 and 1.5 faster than RE2C. Furthermore, our proposed accelerator Ultra-96 improves the performance 2 times with an 8[MB/J] high energy efficiency from the previous PYNQ-Z2 approach.

Application of Pattern Matching in Heating Furnace – Rough Rolling Process

Hot continuous rolling is a complex industrial process. Aiming at the problems of difficult optimization control, information island between process and strong coupling between parameters in 2250 mm rolling line of a steel plant, a parameter optimization method based on multi-level pattern matching is proposed, which is applied to the heating furnace – rough rolling link to adapt the best operation parameters in the current superior operational pattern library so as to improve the product quality of transfer bar. For the situation that the multi-level matching method cannot find the optimal operation mode, an input-output prediction model based on fuzzy neural network is established and particle swarm optimization algorithm is used until the output optimal operation parameters meet the requirements, and updates the new optimal mode to the superior operational pattern library to complete the expansion of the library. The simulation results show that the minimum relative error between the optimization results and the actual operation parameters is about 0.44%, which proves the feasibility of the pattern matching and evolution strategy, so as to achieve the purpose of improving the quality of hot rolling products and improving the enterprise efficiency.

Kikuchi pattern simulations of backscattered and transmitted electrons

We discuss a refined simulation approach which treats Kikuchi diffraction patterns in electron backscatter diffraction (EBSD) and transmission Kikuchi diffraction (TKD). The model considers the result of two combined mechanisms: (a) the dynamical diffraction of electrons emitted coherently from point sources in a crystal and (b) diffraction effects on incoherent diffuse intensity distributions. Using suitable parameter settings, the refined simulation model allows to reproduce various thickness- and energy-dependent features which are observed in experimental Kikuchi diffraction patterns. Excess-deficiency features are treated by the effect of gradients in the incoherent background intensity. Based on the analytical two-beam approximation to dynamical electron diffraction, a phenomenological model of excess-deficiency features is derived, which can be used for pattern matching applications. The model allows to approximate the effect of the incident beam geometry as a correction signal for template patterns which can be reprojected from pre-calculated reference data. As an application, we find that the accuracy of fitted projection centre coordinates in EBSD and TKD can be affected by changes in the order of - if excess-deficiency features are not considered in the theoretical model underlying a best-fit pattern matching approach. Correspondingly, the absolute accuracy of simulation-based EBSD strain determination can suffer from biases of a similar order of magnitude if excess-deficiency effects are neglected in the simulationmodel.

Two-Stage In-Storage Processing and Scheduling for Pattern Matching Applications

In-storage processing technology allows applications to run on embedded processors and accelerators inside solid-state drives (SSDs) for efficient computing distribution. Especially, in pattern matching applications, in-storage computing can be processed quickly due to low data access latency, and the number of I/Os can be reduced by returning only a small amount of results to the host system after processing. Previously proposed in-storage processing is separated into three phases: command decoding, data access, and data processing. In this case, data processing is strictly isolated from data access, and the isolation constraints the utilization of storage. Merging data access and data processing among the phases can enhance the utilization of storage. To efficiently merge them, we propose two-stage in-storage processing and scheduling, especially for the pattern matching application. The first stage processing during data access reduces the second stage processing latency. Also, leveraging the pattern matching results of the first stage processing, our scheduler prioritizes key requests that should return the results to the host system so that they are completed earlier than non-key requests. The proposed scheduling reduces the response time of in-storage processing requests by 52.6 % on average.

Approximate Memristive In-Memory Hamming Distance Circuit

Hamming Distance (HD) is a popular similarity measure that is used widely in pattern matching applications, DNA sequencing, and binary error-correcting codes. In this article, we extend our previous work to prove that our HD circuit is scalable, tolerant to memristor model variability, and tolerant to device-to-device variation. We showed that the operation of our circuit under non-ideal fabrication conditions changes slightly, decreasing the correct classification rates for the MNIST handwritten digits dataset by <1%. Our circuit’s operation is independent of the memristor model used, as long as the model allows a reverse current. Because we leverage in-memory parallel computing, our circuit is n × faster than other HD circuits, where n is the number of HDs to be computed, and it consumes ≈100× − 1,000× less power compared to other memristive and CMOS HD circuits. Used in a full HD Associative Content Addressable Memory (ACAM), the proposed HD circuit consumes only 2.2% of the total system power. Our state-of-the-art, low-power, and fast HD circuit is relevant for a wide range of applications.

Comparing connectivity metrics in cortico-cortical evoked potentials using synthetic cortical response patterns

BackgroundCortico-Cortical Evoked Potentials (CCEPs) are a novel low frequency stimulation method used for brain mapping during intracranial epilepsy investigations. Only a handful of metrics have been applied to CCEP data to infer connectivity, and no comparison as to which is best has been performed. New methodWe implement a novel method which involved superimposing synthetic cortical responses onto stereoelectroencephalographic (SEEG) data, and use this to compare several metric’s ability to detect the simulated patterns. In this we compare two commonly employed metrics currently used in CCEP analysis against eight time series similarity metrics (TSSMs), which have been widely used in machine learning and pattern matching applications. ResultsRoot Mean Square (RMS), a metric commonly employed in CCEP analysis, was sensitive to a wide variety of response patterns, but insensitive to simulated epileptiform patterns. Autoregressive (AR) coefficients calculated by Burg’s method were also sensitive to a wide range of patterns, but were extremely sensitive to epileptiform patterns. Other metrics which employed elastic warping techniques were less sensitive to the simulated response patterns. Comparison with existing methodsOur study is the first to compare CCEP connectivity metrics against one-another. Our results found that RMS, which has been used in many CCEP studies previously, was the most sensitive metric across a wide range of patterns. ConclusionsOur novel method showed that RMS is a robust and sensitive measure, validating much of the findings of the SEEG-CCEP literature to date. Autoregressive coefficients may also be a useful metric to investigate epileptic networks.

Portable Programming with RAPID

As the hardware found within data centers becomes more heterogeneous, it is important to allow for efficient execution of algorithms across architectures. We present RAPID, a high-level programming language and combined imperative and declarative model for functionally- and performance-portable execution of sequential pattern-matching applications across CPUs, GPUs, Field-Programmable Gate Arrays (FPGAs), and Micron’s D480 AP. RAPID is clear, maintainable, concise, and efficient both at compile and run time. Language features, such as code abstraction and parallel control structures, map well to pattern-matching problems, providing clarity and maintainability. For generation of efficient runtime code, we present algorithms to convert RAPID programs into finite automata. Our empirical evaluation of applications in the ANMLZoo benchmark suite demonstrates that the automata processing paradigm provides an abstraction that is portable across architectures. We evaluate RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated. We also find that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact.

Query-Sensitive Graph Partitioner for Pattern Matching Applications

Searching and mining in large graphs is critical to a variety of applications, at the core of which is the pattern matching activity. The scalable processing of large graphs requires careful distribution of graphs across clusters. Graph partitioning is the technique that divides a big graph into several non-overlapped subgraphs and assigns each subgraph to a compute node. Traditional workload agnostic partitioners aim to minimize the number of inter-partition edges using only graph topology, which, however, may not obtain the best solution if the workload exhibits skew. Some workload-aware partitioners choose to mine information from a specific workload and use it to minimize the number of inter-partition traversals during execution; however, their methods are not suitable for pattern matching applications. In this work, we propose a query-sensitive graph partitioner that aims to improve existing partitioning for a given pattern matching workload. The partitioner takes any initial partitioning as a starting point and iteratively adjusts it by exchanging chosen clusters across partitions, heuristically reducing the probability of inter-partition traversals. We determine a few implementation-irrelative factors that may increase the traversal probability of an edge and quantify them into a calculable indicator with information from query patterns and graph topology. Then, we propose an efficient algorithm to calculate the indicator and implement a graph repartitioner by combining the indicator with a greedy cluster-exchanging mechanism. Finally, we generate a large heterogeneous labeled graph with real-world data crawled from the Netease Music website and evaluate the partitioning quality of our repartitioner with a few meaningful query patterns of common topologies including line, loop and branching. Compared with a hash-based partitioning, our system can reduce the inter-partition traversals by at least 70%. Compared with the state-of-the-art graph partitioner Metis , our repartitioner can reduce the inter-partition traversals by at least 50%.

Solution-Processed Complementary Resistive Switching Arrays for Associative Memory

Complementary resistive switches (CRS) based on back-to-back nanofilamentary resistive RAM devices have been fabricated by an all-solution-processed method, employing inkjet-printed Ag and Au contacts and a spin-coated sol–gel zirconium oxide dielectric layer. The devices demonstrate electrical switching behavior below 3 V, stable on-state windows, reasonable cycle lifetimes, and can be implemented in $2\times 2$ memory arrays with no crosstalk during addressing. For reliable operation and high yields of the CRS devices, printing and annealing processes were carefully optimized to eliminate the coffeering effect on the bottom electrode, and produce a pin-hole free dielectric. The arrays are fully pulse programmable and are able to retain their state for > $10^{4}$ s. Additionally, the arrays can be operated as associative or content addressable, memory for pattern matching applications, which is demonstrated through a basic hamming distance mapping measurement for different stored data states.

APPLYING A Q-GRAM BASED MULTIPLE STRING MATCHING ALGORITHM FOR APPROXIMATE MATCHING

We consider the application of multiple pattern matching (Multi AOSO on q-Grams) algorithm for approximate pattern matching. We propose the on-line approach which translates the problem from approximate pattern matching into a multiple pattern one (called partitioning into exact search). Presented solution allows relatively fast search multiple patterns in text with given k-differences(or mismatches). This paper presents comparison of solution based on MAG algorithm, and [4]. Experiments on DNA, English, Proteins and XML texts with up to k errors show that the new proposed algorithm achieves relatively good results in practical use.

EPMA: Efficient pattern matching algorithm for DNA sequences

To solve, manage and analyze biological problems using computer technology is called bioinformatics. With the emergent evolution in computing era, the volume of biological data has increased significantly. These large amounts of data have increased the need to analyze it in reasonable space and time. DNA sequences contain basic information of species, and pattern matching between different species is an important and challenging issue to cope with. There exist generalized string matching and some specialized DNA pattern matching algorithms in the literature. There is still need to develop fast and space efficient pattern matching algorithms that consider new hardware development. In this paper, we present a novel DNA sequences pattern matching algorithm called EPMA. The proposed algorithm utilizes fixed length 2-bits binary encoding, segmentation and multi-threading. The idea is to find the pattern with multiple searcher agents concurrently. The proposed algorithm is validated with comparative experimental results. The results show that the new algorithm is a good candidate for DNA sequence pattern matching applications. The algorithm effectively utilizes modern hardware and will help researchers in the sequence alignment, short read error correction, phylogenetic inference etc. Furthermore, the proposed method can be extended to generalized string matching and their applications.

Design and optimizations for efficient regular expression matching in DPI systems

Efficient techniques for pattern matching are essential in a number of networked systems and services, such as intrusion detection systems, application identification and classification services, and traffic management. Most pattern matching applications describe patterns using regular expression and the support engine is Deterministic Finite Automaton (FA). Previous research studies address either performance or space requirements issues. From the original DFA formalism we design and evaluate optimizations to its representation and operation to meet Deep Packet Inspection (DPI) systems’ requirements for commodity platforms, such as (i) decreasing the original DFA memory consumption (high compression ratio) and (ii) performing pattern matching as fast as the original DFA. Our approach spans from designing the DFA to developing memory layouts to get the most of the underlying architecture. The contributions of this work are threefold: (i) a new and improved finite automaton model, called Ranged Compressed DFA (RCDFA), (ii) three RCDFA optimizations for achieving more compression and matching speed, and (iii) three advanced layouts for implementing the compressed automaton without memory and performance penalties. The experimental evaluation shows that RCDFA compresses DFA up to 99% without imposing additional memory lookups. The proposed advanced layouts reach memory compression of around 97%. RCDFA together with the advanced layouts outperforms the standard DFA by up to 32 times in terms of processing speed.

Efficient steerable circular harmonic functions

Two-dimensional (2D) filtering and pattern matching applications often involve processing of images using a set, Sf, which includes several transformed (e.g. rotated, scaled, warped) versions of the same 2D function, f. Depending on the application, f may correspond to a filter kernel or a pattern. In general, image processing using all functions in Sf poses a computational burden. Steerability offers a solution to the problem. Specifically, each function in Sf can be exactly expressed or closely approximated by a linear combination of a few basis or steering functions. In such cases, processing images by employing steering functions and obtaining linear combinations of the associated responses may be preferable over utilizing all functions in Sf. However, employing the steering functions is still a computationally expensive process. This paper presents a method to significantly improve the computational efficiency of circular harmonic functions, which are the steering functions when rotation is the transformation of interest. The method is presented mainly in the context of image filtering, yet 2D pattern matching is also discussed. The advantages of the proposed technique in relation to other techniques are presented, and its efficiency is demonstrated in terms of execution time and number of operations. An extension of the technique to more general cases where Sf includes rotated, but also otherwise transformed versions of f, is also discussed.

The structural border array

The border and parameterized border (p-border) arrays are data structures used in pattern matching applications for traditional strings from the constant alphabet Σ, and parameterized strings (p-strings) from the constant alphabet Σ and the parameter alphabet Π. In this work, we introduce the structural border array (s-border) as defined for an n-length structural string (s-string) T. The s-string is a p-string with the existence of symbol complements in some alphabet Γ. These different alphabets add to both the intricacies and capabilities of pattern matching. For example, the s-string can handle the Watson–Crick base pairings in biological sequences and thus, assists in applications that deal with efficient pattern matching between RNA strands that share similar secondary structures. Initially, we provide a construction that executes in O(n2) time to build the s-border array. The paper establishes theory to improve the result to O(n) by proving particular properties of the s-border data structure. This result is significant because of the generalization of the s-string, which is a step beyond the p-string. Using the same construction algorithm, we show how to modify the s-string alphabets to also construct the p-border and the traditional border arrays in linear time. The generality of the s-border construction algorithm motivates us to devise pattern matching algorithms for s-matching, p-matching, and traditional matching. Our pattern matching algorithms are ultimately used to address the p-match problem with run-length encoded strings.

Guest Editorial for “Group Testing: models and applications”

The search model known as group testing has recently seen a new raising interest in several areas of computer science with new applications in pattern matching, data structures for static membership, communication protocols and more. Group testing and group testing like models have also proved useful in furthering new fertile fields like streaming computation and compressed sensing. The use of randomness extraction structures for group testing has provided new stimulus in the field. The basic group testing problem is about identifying a set of positive elements in a given search space by means of tests or queries asking whether a certain subset includes at least one of the positive elements. In a broad sense we can rephrase group testing as the problem of determining some special substructure within a large structure. Due to its foundational characters it is not surprising that the basic structures for group testing are rediscovered in very different scenarios. In this respect, group testing also serves as a perfect ground for cross-fertilization among different fields of research. This special issue consists of 7 papers focussing on different aspects of group testing and the combinatorial structures at the basis of group testing models. In “Unbounded Contention Resolution in Multiple-Access Channels,” the authors study the problem of resolving the contention arising when a set of users try to use a shared resource which can only be accessed by one user at a time. They prove optimality of two protocols for content resolution in radio networks assuming that the