Application Of Field Programmable Gate Array Research Articles

High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array

The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power.

Low-Overhead FPGA Middleware for Application Portability and Productivity

Reconfigurable computing devices such as field-programmable gate arrays (FPGAs) offer advantages over fixed-logic CPU and GPU architectures, including improved performance, superior power efficiency, and reconfigurability. The challenge of FPGA application development, however, has limited their acceptance in high-performance computing and high-performance embedded computing applications. FPGA development carries similar difficulties to hardware design, requiring that developers iterate through register-transfer level designs with cycle-level accuracy. Furthermore, the lack of hardware and software standards between FPGA platforms limits productivity and application portability, and makes porting applications between heterogeneous platforms a time-consuming and often challenging process. Recent efforts to improve FPGA productivity using high-level synthesis tools and languages show promise, but platform support remains limited and typically is left as a challenge for developers. To address these issues, we present RC Middleware (RCMW), a novel middleware that improves productivity and enables application and tool portability by abstracting away platform-specific details. RCMW provides an application-centric development environment, exposing only the resources and standardized interfaces required by an application, independent of the underlying platform. We demonstrate the portability and productivity benefits of RCMW using four heterogeneous platforms from three vendors. Our results indicate that RCMW enables application productivity and improves developer productivity, and that these benefits are achieved with less than 7% performance and 3% area overhead on average.

Finite-State-Machine Overlay Architectures for Fast FPGA Compilation and Application Portability

Despite significant advantages, wider usage of field-programmable gate arrays (FPGAs) has been limited by lengthy compilation and a lack of portability. Virtual-architecture overlays have partially addressed these problems, but previous work focuses mainly on heavily pipelined applications with minimal control requirements. We expand previous work by enabling more flexible control via overlay architectures for finite-state machines. Although not appropriate for control-intensive circuits, the presented architectures reduced compilation times of control changes in a convolution case study from 7 hours to less than 1 second, with no performance overhead and an area overhead of 0.2%.

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology

Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 $\thinspace$000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore's Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed “Ages” in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.

Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs

Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications. However, unlike software design tools, the relatively immature state of FPGA tools significantly limits productivity and consequently prevents widespread adoption of the technology. For example, the lengthy design-translate-execute (DTE) process often must be iterated to meet the application requirements. Previous works have enabled model-based, design-space exploration to reduce DTE iterations but are limited by a lack of accurate model-based prediction of key design parameters, the most important of which is clock frequency. In this paper, we present a core-level modeling and design (CMD) methodology that enables modeling of FPGA applications at an abstract level and yet produces accurate predictions of parameters such as clock frequency, resource utilization (i.e., area), and latency. We evaluate CMD’s prediction methods using several high-performance DSP applications on various families of FPGAs and show an average clock-frequency prediction error of 3.6%, with a worst-case error of 20.4%, compared to the best of existing high-level prediction methods, 13.9% average error with 48.2% worst-case error. We also demonstrate how such prediction enables accurate design-space exploration without coding in a hardware-description language (HDL), significantly reducing the total design time.

Logic circuit design for high-speed computing of dynamic response in real-time hybrid simulation using FPGA-based system

One of the issues in extending the range of applicable problems of real-time hybrid simulation is the computation speed of the simulator when large-scale computational models with a large number of DOF are used. In this study, functionality of real-time dynamic simulation of MDOF systems is achieved by creating a logic circuit that performs the step-by-step numerical time integration of the equations of motion of the system. The designed logic circuit can be implemented to an FPGA-based system; FPGA (Field Programmable Gate Array) allows large-scale parallel computing by implementing a number of arithmetic operators within the device. The operator splitting method is used as the numerical time integration scheme. The logic circuit consists of blocks of circuits that perform numerical arithmetic operations that appear in the integration scheme, including addition and multiplication of floating-point numbers, registers to store the intermediate data, and data busses connecting these elements to transmit various information including the floating-point numerical data among them. Case study on several types of linear and nonlinear MDOF system models shows that use of resource sharing in logic synthesis is crucial for effective application of FPGA to real-time dynamic simulation of structural response with time step interval of 1 ms.

A rapid response 64-channel photomultiplier tube camera for high-speed flow velocimetry

In this technical design note, the development of a rapid response photomultiplier tube camera, leveraging field-programmable gate arrays (FPGA) for high-speed flow velocimetry at up to 10 MHz is described. Technically relevant flows, for example, supersonic inlets and exhaust jets, have time scales on the order of microseconds, and their experimental study requires resolution of these timescales for fundamental insight. The inherent rapid response time attributes of a 64-channel photomultiplier array were coupled with two-stage amplifiers on each anode, and were acquired using a FPGA-based system. Application of FPGA allows high data acquisition rates with many channels as well as on-the-fly preprocessing techniques. Results are presented for optical velocimetry in supersonic free jet flows, demonstrating the value of the technique in the chosen application example for determining supersonic shear layer velocity correlation maps.

The Application of FPGA in PWM Controlled Resonant Converter for an Ozone Generator

Pulse Width Modulation (PWM) is a very common technique used in many different applications. The Conventional method its generation is the heart of the inverter system. This paper present methodology to generate Sinusoidal PWM (SPWM) signal for three-phase inverter based on EP20K200EFC484-2x Altera Field Programmable Gate Array (FPGA). Designing a PWM inverter drive using FPGA has several advantages, such as: it's quick, very modifiable, and very suitable for prototyping. In this paper, the PWM signal is used control switching action conducted by MOSFET as part of power electronics devices in resonant power converter which has 24 volt DC input voltage. As the result, by using resonant oscillation controlled by FPGA the high sinusoidal voltage until 1.0 kV peak-to peak has been generated in the load side. DOI: http://dx.doi.org/10.11591/ijpeds.v3i3.4316

SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms

Reliability has become an increasingly important concern for SRAM-based field programmable gate arrays (FPGAs). Targeting SEU (single event upset) in SRAM-based FPGAs, this article first develops an SEU evaluation framework that can quantify the failure sensitivity for each configuration bit during design time. This framework considers detailed fault behavior and logic masking on a post-layout FPGA application and performs logic simulation on various circuit elements for fault evaluation. Applying this framework on MCNC benchmark circuits, we first characterize SEUs with respect to different FPGA circuits and architectures, for example, bidirectional routing and unidirectional routing. We show that in both routing architectures, interconnects not only contribute to the lion's share of the SEU-induced functional failures, but also present higher failure rates per configuration bits than LUTs. Particularly, local interconnect multiplexers in logic blocks have the highest failure rate per configuration bit. Then, we evaluate three recently proposed SEU mitigation algorithms, IPD, IPF, and IPV, which are all logic resynthesis-based with little or no overhead on placement and routing. Different fault mitigating capabilities at the chip level are revealed, and it demonstrates that algorithms with explicit consideration for interconnect significantly mitigate the SEU at the chip level, for example, IPV achieves 61% failure rate reduction on average against IPF with about 15%. In addition, the combination of the three algorithms delivers over 70% failure rate reduction on average at the chip level. The experiments also reveal that in order to improve fault tolerance at the chip level, it is necessary for future fault mitigation algorithms to concern not only LUT or interconnect faults, but also their interactions. We envision that our framework can be used to cast more useful insights for more robust FPGA circuits, architectures, and better synthesis algorithms.

From Simulation to FPGA Control Circuit Implementation for Wind Power with Battery Charging

While application of field-programmable gate array (FPGA) chip has been extensively investigated, the charging control is relatively unexplored. This paper proposes a flow chart of energy storage for wind power system with Lead-Acid battery whose charging control is constructed by Very High Speed Integrated Circuit Hardware Description Language (VHDL) code. This research focuses on the proposed digital control algorithm can be directly downloaded into field-programmable gate array (FPGA) chip after simulation finishing. This saves greatly time on hardware circuit design. A simulation is presented to illustrate the effectiveness of the proposed charging flow chart.

Development and application of application-specific FPGA-based processor for solving bioinformatics problems

An approach to solving large resource-consuming problems is proposed based on the application of field-programmable gate array (FPGA) microchips. This approach is demonstrated for application to the problems of searching for common motifs in genetic sequences of regulatory regions of various genes. Due to the high degree of parallelization and high transmission capacity of the internal memory in the employed FPGA crystal, a 60-fold increase in performance was achieved in solving this problem compared to a system based on the CUDA technology and about a 2000-fold increase compared to a personal computer.

Hardware Co-Simulation of the BPSK and QPSK Systems on FPGA

The application of FPGAs (Field Programmable Gate Array) became an important issue in designing electronic systems. Also, the flexibility and performance offered by reconfigurable computing shorts the development time required for implementing digital signal processing solutions using FPGAs. In this paper, we present original hardware designs of the BPSK and QPSK systems, using Matlab/Simulink environment, System Generator and Xilinx ISE, in order to verify the functionality of the systems in hardware which speeds up the simulations. The capabilities of the Spartan 3E board are also compared with previous reported results.

Intermediate Fabrics: Virtual Architectures for Near-Instant FPGA Compilation

Field-programmable gate arrays (FPGAs) suffer from lower application design productivity than other devices, which is largely due to compilation taking hours or even days. Making FPGA compilation comparable to software compilation is critical for continued FPGA usage due to competitive technologies, such as graphics-processing units, that use languages with runtime compilation models. In this letter, we evaluate virtual reconfigurable architectures, referred to as intermediate fabrics, which enable near-instant placement and routing of applications for commercial FPGAs.

FPGA automatic re-synchronisation for pipelined, floating point control systems applications

One of the main challenges in Systems designs is the ability to integrate real time high fidelity models on suitable and feasible hardware platforms. Because of its inherited parallelism, FPGA (Field Programmable Gate Arrays) technology achieves sample rates which are typically faster than real time. This can be seen as the last line of defence against the increasing requirements given by high fidelity models. But as most of the FPGA applications are specialised and the FPGA toolsets do not support basic control systems blocks, designs are constructed and optimised manually. This leads to significant effort required in finding feasible hardware FPGA implementations. Therefore, the work in this paper describes how to automatically optimise the most time consuming process found in generic FPGA implementations: the optimisation of the pipelining process. This is constructed on a rigorous mathematical model and achieved using drag and drop floating point HDL (Hardware Description Language) control systems blocks, under System Generator, in Simulink.

Guest Editors' Introduction: Special Section on Chips and Architectures for Emerging Technologies and Applications

IT is with great pleasure that we introduce this special section on Chips and Architectures for Emerging Technologies and Applications to the audience of the IEEE Transactions on Computers. We are currently witnessing a technology advancement which is making the gap between the present and future much narrower than it has ever been. The purpose of this special section is to showcase highly innovative, creative, and futuristic chip architectures and functionalities that can range from new paradigms in reconfigurable systems architectures, to adaptive, organic, ubiquitous, and biologically inspired computing, to new classes of chip implants, or any other highly innovative human-to-computer interface. This special section includes two papers, which we hope will offer an interesting perspective on the challenges involved in designing integrated circuits and architectures that leverage the capabilities of emerging technologies in novel applications. The first paper, ‘‘Exploring the Potential of Threshold Logic for Cryptography-Related Operations,’’ by Alessandro Cilardo, investigates the application of a non-Boolean computational paradigm to cryptographic applications. More specifically, the author demonstrates the power of linear Threshold Logic functions, which are enabled by new technologies such as Resonant Tunneling Diodes (RTDs), Single-Electron Tunneling (SET), Quantum Cellular Automata (QCA), and Tunneling Phase Logic (TPL), towards performing fundamental cryptographic operations. An architecture for implementing such operations, namely a Montgomery modular reduction and multiplication, is also introduced and its intrinsic superiority to traditional Boolean computational models in demonstrated. The second paper, ‘‘3D Integration of CMOL Structures for FPGA Applications,’’ by Z. Abid, Ming Liu, and Wei Wang, introduces a combination of hybrid CMOS/ nanoelectronic (CMOL) circuits and 3D integration, in order to develop a 3D CMOL technology with particular emphasis on designing Field-Programmable Gate-Array (FPGA) chips. The authors discuss the architecture, 3D integration, defect tolerance and performance aspects of this technology, as well as its breakthrough potential for developing the next generation of FPGAs. We would like to thank the previous editor-in-chief of the IEEE Transactions on Computers, Dr. Fabrizio Lombardi, for suggesting that we organize this special section, the current editor-in-chief Dr. Albert Y. Zomaya, for hosting this section, and all of the editorial staff for the support in the making of the issue. Additionally, we would like to thank the authors of the submitted papers and the numerous reviewers whose contributions made this special section possible.

A Survey on the Application of FPGAs for Network Infrastructure Security

Given the rapid evolution of attack methods and toolkits, software-based solutions to secure the network infrastructure have become overburdened. The performance gap between the execution speed of security software and the amount of data to be processed is ever widening. A common solution to close this performance gap is through hardware implementation of security functions. Possessing the flexibility of software and high parallelism of hardware, reconfigurable hardware devices, such as Field Programmable Gate Arrays (FPGAs), have become increasingly popular for this purpose. FPGAs support the performance demands of security operations as well as enable architectural and algorithm innovations in the future. This paper presents a survey of the state-of-art in FPGA-based implementations that have been used in the network infrastructure security area, categorizing currently existing diverse implementations. Combining brief descriptions with intensive case-studies, we hope this survey will inspire more active research in this area.

Reduction in the number of LUT elements for control units with code sharing

Reduction in the number of LUT elements for control units with code sharingTwo methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.

Strip packing with precedence constraints and strip packing with release times

The strip packing problem seeks to tightly pack a set of n rectangles into a strip of fixed width and arbitrary height. The rectangles model tasks and the height models time. This paper examines two variants of strip packing: when the rectangles to be placed have precedence constraints and when the rectangles have release times. Strip packing is used to model scheduling problems in which tasks require a contiguous subset of identical resources that are arranged in a linear topology. The variants studied here are motivated by scheduling tasks for dynamically reconfigurable Field-Programmable Gate Arrays (FPGAs) comprised of a linear arrangement of K homogeneous computing resources, where K is a fixed positive integer, and each task occupies a contiguous subset of these resources. For the case in which tasks have precedence constraints, we give an O ( log n ) approximation algorithm. We then consider the special case in which all the rectangles have uniform height, and reduce it to the resource constrained scheduling studied by Garey, Graham, Johnson and Yao, thereby extending their asymptotic results to our special case problem. We also give an absolute 3-approximation for this special case problem. For strip packing with release times, we provide an asymptotic polynomial time approximation scheme. We make the standard assumption that the rectangles have height at most 1 . In addition, we also require widths to be in [ 1 K , 1 ] . For the FPGA application, this would imply that the rectangles are at least as wide as a column. Our running time is polynomial in n and 1 / ϵ , but exponential in K .

Using FPGA for Real-Time Model for VHFIM Control of PMSM Position Drive

Abstract The paper deals with design of field-programmable gate array (FPGA) devices for model reference adaptive control of sensorless permanent magnet synchronous motor (PMSM) drive. The FPGA design comprises of solution of three difference equations of PMSM quantities, so far. The paper is focused on FPGA application part, since whole drive is controlled by DSP processor. The basic simulation experiments results and comparison of FPGA and DSP solution are given on the end of paper.

An Efficient SVPWM Algorithm With Low Computational Overhead for Three-Phase Inverters

A compact algorithm of space vector pulsewidth modulation (SVPWM) for three-phase inverters is proposed and developed in this paper. Simplified by the proposed method, the conventional SVPWM is decomposed into fast integer operations entirely by using an intermediate vector, which will properly counteract the redundant calculations of the remaining procedures. This concept can not only simplify a two-level scheme, but is also suited for multilevel implementation. Since it can be implemented without any multiplier or divider, the fast algorithm is especially suitable for field programmable gate array applications. Then, an area- and speed-efficient IP-core based on this algorithm is built and tested. It ensures lower hardware resource usage, and at the same time, operates several times faster than some reported examples. Finally, experimental results obtained from a dc-ac inverter prototype are presented to verify the viability and effectiveness of the proposed algorithm.