ASIC Research Articles

Design of a low-power Digital-to-Pulse Converter (DPC) for in-memory-computing applications

Data converters such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), digital-to-time converters (DTCs), time-to-digital converters (TDCs), among others, are considered some of the most essential blocks in the field of integrated circuit design. In this work, we introduce a novel type of data converter known as the Digital-to-Pulse converter (DPC) and present its novel analog flow circuit implementation. The DPC system is a critical component in emerging artificial neural network accelerators and in-memory computing systems. The DPC system presented in this study offers two distinct operating modes. The first mode is the generation of a single pulse with a width that is modulated by the digital input. The second mode is an n-bit digital to discrete pulse converter, where the number of generated pulses is directly related to the value of the digital input. The proposed DPC system offers designers a high level of flexibility in shaping the characteristics of the output pulses, including the number of pulses, pulse width, and pulse amplitude. This empowers designers to accommodate different application requirements and scenarios effectively. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulation and analysis. The results indicate a significant enhancement in average power consumption (∼12×), layout area (∼5×), and Latency (∼1.4×) with the proposed system compared to the digital Register Transfer Level (RTL) implementation under a power supply of 1.8V and a clock frequency of 1 GHz in the Application Specific Integrated Circuits (ASIC) flow. This demonstrates the suitability of the proposed system for low-power and high-speed applications.

Application of Multi-Input Multi-Output Brain-Computer Interface in Cognitive Assessment for Alzheimer’s Disease

This research aims to augment human cognitive abilities, particularly memory function, through the development of innovative prosthetics. The hippocampus, a crucial brain region involved in memory encoding and recall, has been the focal point of numerous studies seeking to develop prosthetics that can restore or enhance memory function in individuals with impairments such as Alzheimer’s disease. This review examines two studies that delve into the development and application of hippocampal neural prosthetics, highlighting the potential of these prosthetics to revolutionize the treatment of memory impairments. One study utilized static neural stimulation patterns to enhance memory for specific information content, while another developed a nonlinear Multiple Input Multiple Output (MIMO) dynamic model to predict and stimulate neural activity patterns during memory encoding. Both studies demonstrated significant improvements in memory performance. Additionally, this paper discusses the clinical significance and application prospects of hippocampal neural prosthetics, including the potential for implantable prosthetics and the widespread applicability of MIMO stimulation. Furthermore, the paper explores advanced modeling and classification techniques for neural ensembles and visual memory decoding, including Volterra-type hierarchical modeling, optimal multi-unit stimulation patterns, and a sparse classification model for decoding visual memories. Finally, the paper presents the implementation and evaluation of neural prosthesis systems, including an application-specific integrated circuit (ASIC) design for a hippocampal prosthesis and a high-performance, scalable system architecture for real-time estimation of neural activity. These advancements hold promise for future research and applications in neural prosthetics for memory enhancement.

Proof of Work with Random Selection (PoWR): An Energy Saving Consensus Algorithm with Proof of Work and the Random Selection Function

Bitcoin, which has been used for 13 years, has a role in transactions and investments as a major cryptocurrency. However, as the number of users increases, Bitcoin faces difficulties, such as scalability for transaction throughput and energy-consumption problems due to the concentration of the mining pool. When Bitcoin first started to come out, it began to develop gradually through the mining of individuals. Nevertheless, as the price of the cryptocurrency gradually climbed, large mining corporation groups entered the mining competition with integrated circuit (IC) chips. Consequently, the substantial increase in power consumption is raising concerns regarding energy expenditure. This paper confirms that the verifiable random selection consensus protocol based on proof of work facilitates a fair and efficient system, enabling the participation of numerous individual miners in the mining competition while counteracting the monopolization of the hash rate by large mining corporations, thereby preserving the decentralization of mining. The protocol demonstrates the potential to mitigate substantial energy consumption. Moreover, it embodies features that create barriers to the adoption of high-energy-consuming application-specific integrated circuit equipment, significantly diminishing the principal factors contributing to extensive power utilization.

A Wireless Miniature Injectable Device with Memory-Assisted Backscatter for Multimodal Animal Physiological Monitoring.

This paper introduces a wirelessly powered multimodal animal physiological monitoring application-specific integrated circuit (ASIC). Fabricated in the 180 nm process, the ASIC can be integrated into an injectable device to monitor subcutaneous body temperature, electrocardiography (ECG), and photoplethysmography (PPG). To minimize the device size, the ASIC employs a miniature receiver (Rx) coil for wireless power receiving and data communication through a single inductive link operating at 13.56 MHz. We propose a folded L-shape Rx coil with improved coupling to the transmitter (Tx) coil, even in the presence of misalignment, and enhanced quality factor. The ASIC functions alternatively between recording and sleeping modes, consuming 2.55 μW on average. For PPG measurements, a reflection-type PPG sensor illuminates an LED with tunable current pulses. A current-input analog frontend (AFE) amplifies the current of a photodiode (PD) with 30.8 pARMS current input-referred noise (IRN). The ECG AFE captures ECG signals with a configurable gain of 45-80 dB. The temperature AFE achieves 0.02 ̊C inaccuracy within a sensing range between 27-47 ̊C. The AFE outputs are sequentially digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with an effective number of bits (ENOB) of 8.79. To improve the reliability of data transmission, we propose a memory-assisted backscatter scheme that stores ADC data in an off-chip memory and transmits it when the coupling condition is stable. This scheme achieves a package loss rate (PLR) lower than 0.2% while allowing 24-hour data storage. The device's functionality has been evaluated by in vivo experiments.

RFSoC Softwarisation of a 2.45 GHz Doppler Microwave Radar Motion Sensor

Microwave Doppler sensors are used extensively in motion detection as they are energy-efficient, small-size and relatively low-cost sensors. Common applications of microwave Doppler sensors are for detecting intrusion behind a car roof liner inside an automotive vehicle and to detect moving objects. These applications require a millisecond response from the target for effective detection. A Doppler microwave sensor is ideally suited to the task, as we are only interested in movement of a large water-based mass (i.e., a person) (FMCW Radar also detect static objects). Although microwave components at 2.45 GHz are now relatively cheap due to mass production of other Industrial Scientific and Medical application (ISM) devices, they do require tuning for temperature compensation, dielectric, and manufacturing variability. A digital solution would be ideal, as chip solutions are known to be more repeatable, but Application-Specific Integrated Circuits (ASICs) are expensive to initially prototype. This paper presents the first completely digital Doppler motion sensor solution at 2.45 GHz, implemented on the new RFSoC from Xilinx without the need to up/downconvert the frequency externally. Our proposed system uses a completely digital approach bringing the benefits of product repeatability, better overtemperature performance and softwarisation, without compromising any performance metric associated with a comparable analogue motion sensor. The RFSoC shows to give superior distance versus false detection, as the Signal-to-Noise Ratio (SNR) is better than a typical analogue system. This is mainly due to the high gain amplification requirement of an analogue system, making it susceptible to electrical noise appearing in the intermediate-frequency (IF) baseband. The proposed RFSoC-based Doppler sensor shows how digital technology can replace traditional analogue radio frequency (RF). A case study is presented showing how we can use a novel method of using multiple Doppler channels to provide range discrimination, which can be performed in both analogue and in a digital implementation (RFSoC).

Recent advances in Machine Learning based Advanced Driver Assistance System applications

In recent years, the rise of traffic in modern cities has demanded novel technology to support the drivers and protect the passengers and other third parties involved in transportation. Thanks to rapid technological progress and innovations, many Advanced Driver Assistance Systems (A/DAS) based on Machine Learning (ML) algorithms have emerged to address the increasing demand for practical A/DAS applications. Fast and accurate execution of A/DAS algorithms is essential for preventing loss of life and property. High-speed hardware accelerators are vital for processing the high volume of data captured by increasingly sophisticated sensors and complex mathematical models’ execution of modern deep learning (DL) algorithms. One of the fundamental challenges in this new era is to design energy-efficient and portable ML-enabled platforms for vehicles to provide driver assistance and safety. This article presents recent progress in ML-driven A/DAS technology to offer new insights for researchers. We covered standard ML models and optimization approaches based on widely accepted open-source frameworks extensively used in A/DAS applications. We have also highlighted related articles on ML and its sub-branches, neural networks (NNs), and DL. We have also reported the implementation issues, bench-marking problems, and potential challenges for future research. Popular embedded hardware platforms such as Field Programmable Gate Arrays (FPGAs), central processing units (CPUs), Graphical Processing Units (GPUs), and Application Specific Integrated Circuits (ASICs) used to implement A/DAS applications are also compared concerning their performance and resource utilization. We have examined the hardware and software development environments used in implementing A/DAS applications and reported their advantages and disadvantages. We provided performance comparisons of usual A/DAS tasks such as traffic sign recognition, road and lane detection, vehicle and pedestrian detection, driver behavior, and multiple tasking. Considering the current research dynamics, A/DAS will remain one of the most popular application fields for vehicular transportation shortly.

CTC and CT5TEA: An advanced multi-channel digitizer and trigger ASIC for imaging atmospheric Cherenkov telescopes

We have developed a new set of Application-Specific Integrated Circuits (ASICs) of the TARGET family (CTC and CT5TEA), designed for the readout of signals from photosensors in cameras of Imaging Atmospheric Cherenkov Telescopes (IACTs) for ground-based gamma-ray astronomy. We present the performance and design details. Both ASICs feature 16 channels, with CTC being a Switched-Capacitor Array (SCA) sampler at 0.5 to 1GSa/s with a 16,384 sample deep storage buffer, including the functionality to digitize full waveforms at arbitrary times. CT5TEA is its companion trigger ASIC (though may be used on its own), which provides trigger information for the analog sum of four (and 16) adjacent channels. Since sampling and triggering takes place in two separate ASICs, the noise due to interference from the SCA is suppressed, and allows a minimal trigger threshold of ≤ 2.5 mV (0.74photo electrons (p.e.)) with a trigger noise of ≤ 0.5 mV (0.15p.e.). For CTC, a maximal input voltage range from −0.5V up to 1.7V is achieved with an effective bit range of > 11.6bits and a baseline noise of 0.7 mV. The cross-talk improved to ≤ 1% over the whole −3 dB bandwidth of 220MHz and even down to 0.2% for 1.5V pulses of 10 ns width. Not only is the performance presented, but a temperature-stable calibration routine for pulse mode operation is introduced and validated. The resolution is found to be ∼ 2.5% at 33.7 mV (10p.e.) and ≤ 0.3% at 337 mV (100p.e.) with an integrated non-linearity of < 1.6mV. Developed for the Small-Sized Telescope (SST) and Schwarzschild-Couder Telescope (SCT) cameras of the Cherenkov Telescope Array Observatory (CTAO), CTC and CT5TEA are deployed for both prototypes and shall be integrated into the final versions.

Remotely Powered Two-Wire Cooperative Sensors for Bioimpedance Imaging Wearables.

Bioimpedance imaging aims to generate a 3D map of the resistivity and permittivity of biological tissue from multiple impedance channels measured with electrodes applied to the skin. When the electrodes are distributed around the body (for example, by delineating a cross section of the chest or a limb), bioimpedance imaging is called electrical impedance tomography (EIT) and results in functional 2D images. Conventional EIT systems rely on individually cabling each electrode to master electronics in a star configuration. This approach works well for rack-mounted equipment; however, the bulkiness of the cabling is unsuitable for a wearable system. Previously presented cooperative sensors solve this cabling problem using active (dry) electrodes connected via a two-wire parallel bus. The bus can be implemented with two unshielded wires or even two conductive textile layers, thus replacing the cumbersome wiring of the conventional star arrangement. Prior research demonstrated cooperative sensors for measuring bioimpedances, successfully realizing a measurement reference signal, sensor synchronization, and data transfer though still relying on individual batteries to power the sensors. Subsequent research using cooperative sensors for biopotential measurements proposed a method to remove batteries from the sensors and have the central unit supply power over the two-wire bus. Building from our previous research, this paper presents the application of this method to the measurement of bioimpedances. Two different approaches are discussed, one using discrete, commercially available components, and the other with an application-specific integrated circuit (ASIC). The initial experimental results reveal that both approaches are feasible, but the ASIC approach offers advantages for medical safety, as well as lower power consumption and a smaller size.

The MIZAR ASIC: 64-channel zone-sampling based ASIC for Cherenkov light detection from sub-orbital and orbital altitudes

This work describes the implementation of a 64-channel Application Specific Integrated Circuit (ASIC) developed in a commercial 65 nm CMOS technology to readout the signals collected by a camera plane made of Silicon Photo-Multipliers. The aim of the application is the identification of Extensive Air Showers (EASs) by detecting optical Cherenkov light generated by Ultra-High Energy Cosmic Rays (UHECRs) and Neutrinos (UHENUs) from sub-orbital and orbital altitudes. In this context, the ASIC is designed to store each event into an analog memory based on 256 configurable cells per channel. Then the chip forms a hitmap sent to an Field Programmable Gate Array (FPGA) to recognize a pattern of interest. If the signal is externally validated, the digital conversion can occur on-board using an array of 12-bits Wilkinson analog-to-digital converters (ADCs) at 200 MHz of clock. The readout is realized with two serializers running at 400 MHz in double data rate (DDR). Both the number of cells and the resolution can be configured into partitions of 32, 64 or 256 cells and in the range 8–12 bits respectively, becoming a key feature of this ASIC. The chip submission and testing are planned for the forthcoming months.

A heterogenous integrated neural recording system with elastocapillary self-assembled Au-PDMS-PEG neural probe and customized ASIC

Abstract This study presents the design and implementation of a heterogenous integrated neural recording system consisting of a flexible Au-PDMS-PEG probe and customized complementary metal oxide semiconductor (CMOS) application-specific integrated circuit (ASIC) in a standard 0.18 μm process. The flexible Au-PDMS-PEG probe was prepared by an elastocapillary self-assembled process, achieving an electrode impedance of 250 kΩ (@1 kHz). The customized CMOS ASIC contains 36 modular digital pixels (MDP). It achieves 5.69 μVrms input referred noise, 10.29 effective number of bits, 49.5 μW power consumption, and 0.092 mm2 area for a single MDP unit. Spontaneous spikes were also recorded in the mouse cortex, with a peak-to-peak amplitude of 389.2 μVPP and a signal-to-noise ratio of 19.36. Benchtop and in-vivo experiments were conducted to validate the functionality and performance of the proposed neural recording system.

A novel cryogenic acoustic microscope to evaluate electronic components

Abstract Electronics to operate at cryogenic temperatures is key to many areas of science, including space exploration and in particle physics. Ensuring circuit functional reliability is mission critical. One system that will use tens of thousands of custom designed application specific integrated circuits (ASIC) is the Deep Underground Neutrino Experiment (DUNE), which will have sensor circuits operating in liquid argon (87 K) for decades. Both functional and nondestructive testing are being used to ensure circuit quality and reliability. Part of this work involves design, testing and data analysis using a cryogenic acoustic microscope operating at frequencies up to 50 MHz. Image analysis and correlations are used to compare differences seen before and after cryogenic cycling. Data are reported that were collected at room temperature (300 K) and when cooled using liquid nitrogen (77 K).

A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions.

R&D of a timing measurement ASIC for possible HL-LHC upgrade

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) at CERN will undergo a major upgrade for the High Luminosity phase of the LHC (HL-LHC), which is expected to start in 2029 [1]. In addition to improving the detector rate capabilities and performance at increased higher luminosity, precision timing measurements are added to mitigate pile-up effects. The timing detector currently under construction covers pseudo-rapidity up to η=3[2] . A possible pathway for further improvements is the extension of timing capabilities to cover the full tracker acceptance up to η=4. Low Gain Avalanche Detectors (LGAD) pixels have been shown to be a suitable candidate for replacing a part of the pixel detector end-caps during a future Long Shutdown or Year-End Technical Stop of the LHC. Here, we present preliminary results of our design efforts towards a readout Application-specific integrated circuit (ASIC) capable of operating with LGAD pixel sensors [3]. The first results of the modeling of a part of the ASIC are demonstrated.

Integrated package and calibration of high-g MEMS ASIC acceleration sensor

To achieve the intelligentization and miniaturization goals of high-g acceleration sensors, this paper proposes a super high-g accelerometer using ASIC (Application-Specific Integrated Circuit) and MEMS (Micro-Electro-Mechanical Systems) integrated packaging. The sensor structure is a membrane island structure and the ASIC interface is manufactured using 0.35 µm CMOS (Complementary Metal-Oxide-Semiconductor) technology. Two prototypes were calibrated and the sensitivities are 0.206 µV/g and 0.337 µV/g. The package frequency of sensors is 74.5 kHz. The sensor range is 200,000 g, with an overload resistance of up to 250,000 g, the enhancement of overload resistance of sensors with integrated ASIC chips has been achieved. The resolution of the prototype is 371.10 g, which is 71.95 % higher compared to the sensor without integrated ASIC. The signal-to-noise ratio (SNR) is 72.363 dB, which has been improved by 24.73 %, verifying the effective improvement of resolution and SNR of the sensors with the addition of ASIC chips.

Validation of Timepix4 energy calibration procedures with synchrotron X-ray beams

The Timepix4 is an application-specific integrated circuit developed by the Medipix4 collaboration. The chip is a 448 × 512 matrix that can be connected, via bump-bonding, to pixelated sensors of various materials and thicknesses, forming application specific detection systems. Among the Timepix4 operating modes, the data-driven Time-of-Arrival - Time-Over-Threshold is a particularly promising mode for spectral imaging applications: data packets are generated every time the charge created by the incoming radiation goes above a pre-defined threshold, allowing the count of the detected particles and their energy measurement. This article investigates the spectroscopic characteristics of a Timepix4 assembly equipped with a 300 μm Si sensor, using monochromatic X-ray beams in the energy range 8.5 keV–40 keV working at the SYRMEP beamline of the Elettra synchrotron. The accuracy and the energy resolution of the reconstructed energy spectra, together with an energy resolution model, will be presented.

Characterizing electron-collecting CdTe for use in a 77 ns burst-rate imager.

The Keck-PAD (pixel array detector) was developed at Cornell as a burst-rate imager capable of recording images from successive electron bunches (153 ns period) from the Advanced Photon Source (APS). Both Si and hole-collecting Schottky CdTe have been successfully bonded to this ASIC (application-specific integrated circuit) and used with this frame rate. The facility upgrades at the APS will lower the bunch period to 77 ns, which will require modifications to the Keck-PAD electronics to image properly at this reduced period. In addition, operation at high X-ray energies will require a different sensor material having a shorter charge collection time. For the target energy of 40 keV for this project, simulations have shown that electron-collecting CdTe should allow >90% charge collection within 35 ns. This collection time will be sufficient to sample the signal from one frame and prepare for the next. 750 µm-thick electron-collecting Schottky CdTe has been obtained from Acrorad and bonded to two different charge-integrating ASICs developed at Cornell, the Keck-PAD and the CU-APS-PAD. Carrier mobility has been investigated using the detector response to single X-ray bunches at the Cornell High Energy Synchrotron Source and to a pulsed optical laser. The tests indicate that the collection time will meet the requirements for 77 ns imaging.

A Wirelessly Powered Scattered Neural Recording Wearable System.

This paper introduces a wirelessly powered scattered neural recording wearable system that can facilitate continuous, untethered, and long-term electroencephalogram (EEG) recording. The proposed system, including 32 standalone EEG recording devices and a central controller, is incorporated in a wearable form factor. The standalone devices are sparsely distributed on the scalp, allowing for flexible placement and varying quantities to provide extensive spatial coverage and scalability. Each standalone device featuring a low-power EEG recording application-specific integrated circuit (ASIC) wirelessly receives power through a 60 MHz inductive link. The low-power ASIC design (84.6 μW) ensures sufficient wireless power reception through a small receiver (Rx) coil. The 60 MHz inductive link also serves as the data carrier for wireless communication between standalone devices and the central controller, eliminating the need for additional data antennas. All these efforts contribute to the miniaturization of standalone devices with dimensions of 12×12×5 mm3, enhancing device wearability. The central controller applies the pulse width modulation (PWM) scheme on the 60 MHz carrier, transmitting user commands at 4 Mbps to EEG recording ASICs. The ASIC employs a novel synchronized PWM demodulator to extract user commands, operating signal digitization and data transmission. The analog frontend (AFE) amplifies the EEG signal with a gain of 45 dB and applies band-pass filtering from 0.03 Hz to 400 Hz, with an input-referred noise (IRN) of 3.62 μVRMS. The amplified EEG signal is then digitized by a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) with a peak signal-to-noise and distortion ratio (SNDR) of 55.4 dB. The resulting EEG data is transmitted to an external software-defined radio (SDR) Rx through load-shift-keying (LSK) backscatter at 3.75 Mbps. The system's functionality is fully evaluated in human experiments.

Embedded FPGA developments in 130 nm and 28 nm CMOS for machine learning in particle detector readout

Embedded field programmable gate array (eFPGA) technology allows the implementation of reconfigurable logic within the design of an application-specific integrated circuit (ASIC). This approach offers the low power and efficiency of an ASIC along with the ease of FPGA configuration, particularly beneficial for the use case of machine learning in the data pipeline of next-generation collider experiments. An open-source framework called “FABulous” was used to design eFPGAs using 130 nm and 28 nm CMOS technology nodes, which were subsequently fabricated and verified through testing. The capability of an eFPGA to act as a front-end readout chip was assessed using simulation of high energy particles passing through a silicon pixel sensor. A machine learning-based classifier, designed for reduction of sensor data at the source, was synthesized and configured onto the eFPGA. A successful proof-of-concept was demonstrated through reproduction of the expected algorithm result on the eFPGA with perfect accuracy. Further development of the eFPGA technology and its application to collider detector readout is discussed.

Survey on Advances in Broadband Signal Generation and Processing of ASIC Semiconductors for Defense Satellites

To replace the field-programmable gate array semiconductors used in the defense satellite industry, we conducted a technical investigation of application-specific integrated circuit (ASIC) semiconductors. The analysis results show that ASIC semiconductors have the heat dissipation, reliability, and radiation resistance capabilities required in a space environment and excellent performance indicators related to the resolution of synthetic aperture radar payloads, such as operating frequency. Research and development of mission-customized ASIC semiconductors that fit the requirements for NSP(new-space paradigm) should be preceded to expanse bases of the space industry, national security capabilities for next-generation space deveolpment also to secure competitiveness of technology and domestic supply chain as space parts itselfs.

Development of Power-Delay Product Optimized ASIC-Based Computational Unit for Medical Image Compression

The proliferation of battery-operated end-user electronic devices due to technological advancements, especially in medical image processing applications, demands low power consumption, high-speed operation, and efficient coding. The design of these devices is centered on the Application-Specific Integrated Circuits (ASIC), General Purpose Processors (GPP), and Field Programmable Gate Array (FPGA) frameworks. The need for low-power functional blocks arises from the growing demand for high-performance computational units that are part of high-speed processors operating at high clock frequencies. The operational speed of the processor is determined by the computational unit, which is the workhorse of high-speed processors. A novel approach to integrating Very Large-Scale Integration (VLSI) ASIC design and the concepts of low-power VLSI compatible with medical image compression was embraced in this research. The focus of this study was the design, development, and implementation of a Power Delay Product (PDP) optimized computational unit targeted for medical image compression using ASIC design flow. This stimulates the research community’s quest to develop an ideal architecture, emphasizing on minimizing power consumption and enhancing device performance for medical image processing applications. The study uses area, delay, power, PDP, and Peak Signal-to-Noise Ratio (PSNR) as performance metrics. The research work takes inspiration from this and aims to enhance the efficiency of the computational unit through minor design modifications that significantly impact performance. This research proposes to explore the trade-off of high-performance adder and multiplier designs to design an ASIC-based computational unit using low-power techniques to enhance the efficiency in power and delay. The computational unit utilized for the digital image compression process was synthesized and implemented using gpdk 45 nm standard libraries with the Genus tool of Cadence. A reduced PDP of 46.87% was observed when the image compression was performed on a medical image, along with an improved PSNR of 5.89% for the reconstructed image.