Application Runtime Research Articles

Ytopt: Autotuning Scientific Applications for Energy Efficiency at Large Scales

ABSTRACTAs we enter the exascale computing era, efficiently utilizing power and optimizing the performance of scientific applications under power and energy constraints has become critical and challenging. We propose a low‐overhead autotuning framework to autotune performance and energy for various hybrid MPI/OpenMP scientific applications at large scales and to explore the tradeoffs between application runtime and power/energy for energy efficient application execution, then use this framework to autotune four ECP proxy applications—XSBench, AMG, SWFFT, and SW4lite. Our approach uses Bayesian optimization with a Random Forest surrogate model to effectively search parameter spaces with up to 6 million different configurations on two large‐scale HPC production systems, Theta at Argonne National Laboratory and Summit at Oak Ridge National Laboratory. The experimental results show that our autotuning framework at large scales has low overhead and achieves good scalability. Using the proposed autotuning framework to identify the best configurations, we achieve up to 91.59% performance improvement, up to 21.2% energy savings, and up to 37.84% EDP (energy delay product) improvement on up to 4096 nodes.

Run-time Application Migration using Checkpoint/Restore In Userspace

Run-time Application Migration using Checkpoint/Restore In Userspace

NxtSPR: A deadlock-free shortest path routing dedicated to relaying for Triplet-Based many-core Architecture

Deadlock-free routing is a significant challenge in Network-on-Chip (NoC) design as it affects the network’s latency, power consumption, and load balance, impacting the performance of multi-processor systems-on-chip. However, achieving deadlock-free routing will routinely result in expensive overhead as previous solutions either sacrifice performance or power efficiency to proactively avoid deadlocks or impose high hardware complexity to resolve deadlocks when they occur reactively. Utilizing the various characteristics of NoC to implement deadlock-free routing can be significantly more cost-effective with less impact on performance. This paper proposes a relay routing algorithm (NxtSPR) with a shortest path property and a deadlock prevention mechanism based on a synchronized Hamiltonian ring. The proposal is based on an in-depth study of the characteristics of a Triplet-Based many-core Architecture (TriBA) NoC. We establish various important topology-related theories and perform a formal verification (proof-based) for them. By utilizing the critical subgraph and apex of TriBA, NxtSPR can pre-calculate downstream nodes forwarding ports for packets by using a concise judgment strategy. This significantly reduces the computational overhead required for data transmission while optimizing the pipeline design of routers to decrease packet transmission latency and power consumption compared to other TriBA routing algorithms. We group the data transmissions according to the levels of maximum Hamiltonian edges a packet will traverse during its transmission life cycle. Independent data transmissions between groups can avoid mutual interference and resource competition, eliminating potential deadlocks. Gem5 simulation results show that, under the synthetic traffic patterns, compared to the representative (Table) and up-to-date (SPR4T) routing algorithms, NxtSPR achieves a 20.19%, 14.76%, and 5.54%, 4.66% reduction in average packet latency and per-packet power consumption, respectively. Moreover, it has an average of 18.50% and 4.34% improvement in throughput, as compared to them. PARSEC benchmark results show that NxtSPR reduces application runtime by up to a maximum of 22.30% and 12.82% compared to Table and SPR4T, and running the same applications with TriBA results in a maximum runtime reduction of 10.77% compared to 2D-Mesh.

2DMAC: A Sustainable and Efficient Medium Access Control Mechanism for Future Wireless NoCs

Wireless Network-on-Chip (WNoC) requires a Medium Access Control (MAC) mechanism for an interference-free sharing of the wireless channel. In traditional MAC, a token is circulated among the Wireless Interfaces (WIs) in a Round Robin manner. The WI with the token holds the channel for a fixed number of cycles. However, the channel requirement of the individual WIs dynamically changes over time due to the varying traffic density across the WNoC. Moreover, the conventional WNoCs give equal importance to all the traffic taking the wireless path and transmit it in an oldest-first manner. Nevertheless, the critical data can degrade the system performance to a large extent by delaying the application runtime if not served promptly. We propose 2DMAC, which can change the token arbitration pattern and tune the channel hold time of each WI based on its runtime traffic density and criticality status. Moreover, 2DMAC prioritizes the critical traffic over the non-critical traffic during the wireless data transfer. The proposed mechanism improves the wireless channel utilization by 15.67% and the network throughput by 29.83% and reduces the critical data latency by 29.77% over the traditional MAC.

Quantum monte carlo for economics: Stress testing and macroeconomic deep learning

Computational methods both open the frontiers of economic analysis and serve as a bottleneck in what can be achieved. We are the first to study whether Quantum Monte Carlo (QMC) algorithm can improve the runtime of economic applications and challenges in doing so. We provide a detailed introduction to quantum computing and especially the QMC algorithm. Then, we illustrate how to formulate and encode into quantum circuits (a) a bank stress testing model with credit shocks and fire sales, (b) a neoclassical investment model solved with deep learning, and (c) a realistic macro model solved with deep neural networks. We discuss potential computational gains of QMC versus classical computing systems and present a few innovations in benchmarking QMC.

A Blockchain Protocol for Real-Time Application Migration on the Edge.

The Internet of Things (IoT) is experiencing widespread adoption across industry sectors ranging from supply chain management to smart cities, buildings, and health monitoring. However, most software architectures for the IoT deployment rely on centralized cloud computing infrastructures to provide storage and computing power, as cloud providers have high economic incentives to organize their infrastructure into clusters. Despite these incentives, there has been a recent shift from centralized to decentralized architectures that harness the potential of edge devices, reduce network latency, and lower infrastructure costs to support IoT applications. This shift has resulted in new edge computing architectures, but many still rely on centralized solutions for managing applications. A truly decentralized approach would offer interesting properties required for IoT use cases. In this paper, we introduce a decentralized architecture tailored for large-scale deployments of peer-to-peer IoT sensor networks and capable of run-time application migration. We propose a leader election consensus protocol for permissioned distributed networks that only requires one series of messages in order to commit to a change. The solution combines a blockchain consensus protocol using Verifiable Delay Functions (VDF) to achieve decentralized randomness, fault tolerance, transparency, and no single point of failure. We validate our solution by testing and analyzing the performance of our reference implementation. Our results show that nodes are able to reach consensus consistently, and the VDF proofs can be used as an entropy pool for decentralized randomness. We show that our system can perform autonomous real-time application migrations. Finally, we conclude that the implementation is scalable by testing it on 100 consensus nodes running 200 applications.

A time-sensitive learning-to-rank approach for cloud simulation resource prediction

Predicting the computing resources required by simulation applications can provide a more reasonable resource-allocation scheme for efficient execution. Existing prediction methods based on machine learning, such as classification/regression, typically must accurately predict the runtime of simulation applications and select the optimal computing resource allocation scheme by sorting the length of the simulation runtime. However, the ranking results are easily affected by the simulation runtime prediction accuracy. This study proposes a time-sensitive learning-to-rank (LTR) approach for cloud simulations resource prediction. First, we use the Shapley additive explanation (SHAP) value from the field of explainable artificial intelligence (XAI) to analyze the impact of relevant factors on the simulation runtime and to extract the feature dimensions that significantly affect the simulation runtime. Second, by modifying the target loss function of the rankboost algorithm and training a time-sensitive LTR model based on simulation features, we can accurately predict the computing resource allocation scheme that maximizes the execution efficiency of simulation applications. Compared with the traditional machine learning prediction algorithm, the proposed method can improve the average sorting performance by 3%–48% and can accurately predict the computing resources required for the simulation applications to execute in the shortest amount of time.

The CTH Network: An NoC Platform for Scalable and Energy Efficient Application Mapping Solution

Multi-threaded design of the applications has given a new dimension to the execution concurrency. The Network-on-Chip (NoC) infrastructure has evolved as the communication backbone in multiprocessor System-on-Chips (MPSoCs) to exploit Thread-Level Parallelism (TLP). Mapping the threads of various applications on the processing cores is crucial in utilizing the resources of a many-core system. An application's performance depends primarily on the mapping strategy. However, the performance of an application gets influenced significantly by the underlying network architecture of the NoC. The present work proposes a run-time application mapping technique based on the Cube-Tree-Hybrid (CTH) topology focusing on the traffic load balancing across the network. The mapping overhead decreased significantly by exploiting the low network diameter of CTH with its high scalability and path diversity, projecting a 31% reduction in normalized execution time over the prevalent algorithms on the existing mapping platforms. Rigorous experimentation with varying application and network sizes is carried out across mesh, ZMesh, torus, and Mest-of-Tree (MoT) networks. The experimental observations project that the proposed algorithm results in sustainable application performance with 15%-21% gain in the overall energy consumption over the existing state-of-the-art techniques across various benchmark workloads.

WasmAndroid: A Cross-Platform Runtime for Native Programming Languages on Android

Open source hardware such as RISC-V has been gaining substantial momentum. Recently, they have begun to embrace Google’s Android operating system to leverage its software ecosystem. Despite the encouraging progress, a challenging issue arises: a majority of Android applications are written in native languages and need to be recompiled to target new hardware platforms. Unfortunately, this recompilation process is not scalable because of the explosion of new hardware platforms. To address this issue, we present WasmAndroid, a high-performance cross-platform runtime for native Android applications. With WasmAndroid, developers can compile their source code to WebAssembly, an efficient and portable bytecode format that can be executed everywhere without additional reconfiguration. Developers can also transpile existing application binaries to WebAssembly when source code is not available. WebAssembly’s language model is very different from other common languages. This mismatch leads to many unique implementation challenges. In this article, we provide workable solutions and conduct a thorough system evaluation. We show that WasmAndroid provides acceptable performance to execute native applications in a cross-platform manner.

Leveraging Computational Storage for Power-Efficient Distributed Data Analytics

This article presents a family of computational storage drives (CSDs) and demonstrates their performance and power improvements due to in-storage processing (ISP) when running big data analytics applications. CSDs are an emerging class of solid state drives that are capable of running user code while minimizing data transfer time and energy. Applications that can benefit from in situ processing include distributed training, distributed inferencing, and databases. To achieve the full advantage of the proposed ISP architecture, we propose software solutions for workload balancing before and at runtime for training and inferencing applications. Other applications such as sharding-based databases can readily take advantage of our ISP structure without additional tooling. Experimental results on different capacity and form factors of CSDs show up to 3.1× speedup in processing while reducing the energy consumption and data transfer by up to 67% and 68%, respectively, compared to regular enterprise solid state drives.

Reducing Minor Page Fault Overheads through Enhanced Page Walker

Application virtual memory footprints are growing rapidly in all systems from servers down to smartphones. To address this growing demand, system integrators are incorporating ever larger amounts of main memory, warranting rethinking of memory management. In current systems, applications produce page fault exceptions whenever they access virtual memory regions that are not backed by a physical page. As application memory footprints grow, they induce more and more minor page faults. Handling of each minor page fault can take a few thousands of CPU cycles and blocks the application till the OS kernel finds a free physical frame. These page faults can be detrimental to the performance when their frequency of occurrence is high and spread across application runtime. Specifically, lazy allocation-induced minor page faults are increasingly impacting application performance. Our evaluation of several workloads indicates an overhead due to minor page faults as high as 29% of execution time. In this article, we propose to mitigate this problem through a hardware, software co-design approach. Specifically, we first propose to parallelize portions of the kernel page allocation to run ahead of fault time in a separate thread. Then we propose the Minor Fault Offload Engine (MFOE), a per-core hardware accelerator for minor fault handling. MFOE is equipped with a pre-allocated page frame table that it uses to service a page fault. On a page fault, MFOE quickly picks a pre-allocated page frame from this table, makes an entry for it in the TLB, and updates the page table entry to satisfy the page fault. The pre-allocation frame tables are periodically refreshed by a background kernel thread, which also updates the data structures in the kernel to account for the handled page faults. We evaluate this system in the gem5 architectural simulator with a modified Linux kernel running on top of simulated hardware containing the MFOE accelerator. Our results show that MFOE improves the average critical path fault handling latency by 33× and tail critical path latency by 51×. Among the evaluated applications, we observed an improvement of runtime by an average of 6.6%.

Optimal load balancing and assessment of existing load balancing criteria

Parallel iterative applications often suffer from load imbalance, one of the most critical performance degradation factors. Hence, load balancing techniques are used to distribute the workload evenly to maximize performance. A key challenge is to know when to use load balancing techniques. In general, this is done through load balancing criteria, which trigger load balancing based on runtime application data and/or user-defined information. In the first part of this paper, we introduce a novel, automatic load balancing criterion derived from a simple mathematical model. In the second part, we propose a branch-and-bound algorithm to find the load balancing iterations that lead to the optimal application performance. This algorithm finds the optimal load balancing scenario in polynomial time while, to the best of our knowledge, it has never been addressed in less than an exponential time. Finally, we compare the performance of the scenarios produced by state-of-the-art load balancing criteria relative to the optimal load balancing scenario in synthetic benchmarks and parallel N-body simulations. In the synthetic benchmarks, we observe that the proposed criterion outperforms the other automatic criteria. In the numerical experiments, we show that our new criterion is, on average, 4.9% faster than state-of-the-art load balancing criteria and can outperform them by up to 17.6%. Moreover, we see in the numerical study that the state-of-the-art automatic criteria are at worst 26.43% slower than the optimum and at best 10% slower.

A Privacy Protection Approach Based on Android Application's Runtime Behavior Monitor and Control

This article proposes a system that focuses on Android application runtime behavior forensics. Using Linux processes, a dynamic injection and a Java function hook technology, the system is able to manipulate the runtime behavior of applications without modifying the Android framework and the application's source code. Based on this method, a privacy data protection policy that reflects users' intentions is proposed by extracting and recording the privacy data usage in applications. Moreover, an optimized random forest algorithm is proposed to reduce the policy training time. The result shows that the system realizes the functions of application runtime behavior monitor and control. An experiment on 134 widely used applications shows that the basic privacy policy could satisfy the majority of users' privacy intentions.

Online Application Guidance for Heterogeneous Memory Systems

As scaling of conventional memory devices has stalled, many high-end computing systems have begun to incorporate alternative memory technologies to meet performance goals. Since these technologies present distinct advantages and tradeoffs compared to conventional DDR* SDRAM, such as higher bandwidth with lower capacity or vice versa, they are typically packaged alongside conventional SDRAM in a heterogeneous memory architecture. To utilize the different types of memory efficiently, new data management strategies are needed to match application usage to the best available memory technology. However, current proposals for managing heterogeneous memories are limited, because they either (1) do not consider high-level application behavior when assigning data to different types of memory or (2) require separate program execution (with a representative input) to collect information about how the application uses memory resources. This work presents a new data management toolset to address the limitations of existing approaches for managing complex memories. It extends the application runtime layer with automated monitoring and management routines that assign application data to the best tier of memory based on previous usage, without any need for source code modification or a separate profiling run. It evaluates this approach on a state-of-the-art server platform with both conventional DDR4 SDRAM and non-volatile Intel Optane DC memory, using both memory-intensive high-performance computing (HPC) applications as well as standard benchmarks. Overall, the results show that this approach improves program performance significantly compared to a standard unguided approach across a variety of workloads and system configurations. The HPC applications exhibit the largest benefits, with speedups ranging from 1.4× to 7× in the best cases. Additionally, we show that this approach achieves similar performance as a comparable offline profiling-based approach after a short startup period, without requiring separate program execution or offline analysis steps.

Runtime Application Self Protection

This paper explains the fundamental concepts of Runtime Application Self-Protection Technology (RASP), a relatively new security method whose widespread use is envisaged in the near future. The ongoing focal point of this innovation is on Java and.NET stage weaknesses. In addition to typification, the paper discusses RASP's benefits and drawbacks. Despite its undeniable benefits, it is not an independent and comprehensive solution for software security. RASP provides an effective solution to avoid harmful actions when used in conjunction with tried and true traditional methods. In powerful web-based applications, script infusion weaknesses are exceptionally normal. To provide protection against distinct injection types, the necessary conditions for the production and exploitation of script injection vulnerabilities were examined. The statements were located with their types in the HTML statements using a combination of the host language and object language analysis. The information reliance connection subgraph with source and sink focuses was produced in light of the control stream diagram. For this sub-graph, a filter insertion technique is used to define multiple input data type filtering strategies. Then, using data flow analysis and intelligent filtering before important sink statements, a solution was built.

Rapid Evaluation and Response to Impacts on Critical End-Use Loads Following Natural Hazard-Driven Power Outages: A Modular and Responsive Geospatial Technology

The disparate nature of data for electric power utilities complicates the emergency recovery and response process. The reduced efficiency of response to natural hazards and disasters can extend the time that electrical service is not available for critical end-use loads, and in extreme events, leave the public without power for extended periods. This article presents a methodology for the development of a semantic data model for power systems and the integration of electrical grid topology, population, and electric distribution line reliability indices into a unified, cloud-based, serverless framework that supports power system operations in response to extreme events. An iterative and pragmatic approach to working with large and disparate datasets of different formats and types resulted in improved application runtime and efficiency, which is important to consider in real time decision-making processes during hurricanes and similar catastrophic events. This technology was developed initially for Puerto Rico, following extreme hurricane and earthquake events in 2017 and 2020, but is applicable to utilities around the world. Given the highly abstract and modular design approach, this technology is equally applicable to any geographic region and similar natural hazard events. In addition to a review of the requirements, development, and deployment of this framework, technical aspects related to application performance and response time are highlighted.

A Fast Heuristic for Improving the Energy Efficiency of Asymmetric VFI-Based Manycore Systems

Voltage/Frequency Islands (VFIs) are practically used in multicore systems. VFIs cluster cores that share the same Voltage/Frequency (V/F) level for the entire application runtime. Using VFIs, switching V/F levels has less overhead per-core while saving more energy in exchange for tolerable execution delay. This paper targets the well-known K-means algorithm for clustering cores, where each cluster contains cores with similar computational workloads across applications phases. K-means produces sub-optimal clusters when cores workloads do not have the same variation across all phases. Furthermore, the workload variations require running a VFI with a different V/F level per-phase. This paper presents a fast heuristic that facilitates clustering by sorting computational workloads per-phase before applying K-means. The VFIs V/F levels are dynamically adjusted to meet energy budget constraints. This framework provides a guideline for users to choose a number of clusters that satisfies system configurations and energy efficiency preferences. Three parameters are evaluated to represent the computational workloads: utilization, Instruction-Per-Cycle (IPC), and execution time. For an application with highly varying workload, execution time achieves 52 and 65% more energy efficiency compared to utilization and IPC, respectively. Results show that the degree of workload variations for different applications impacts changing or fixing VFIs V/F levels.

APE: Metrics for understanding application performance efficiency under power caps

As supercomputers continue to grow in size and power consumption, the ability to understand application run time performance and energy/power usage is of growing importance. In the future it may be necessary for systems to operate under power caps imposed by facilities due to external influences such as renewable power generation (e.g. solar) impacting energy availability at an affordable cost during certain times of day and more frequent natural disasters due to climate change causing power transmission disruptions. However, current energy consumption and power characterization metrics like energy-delay products do not express all of the characteristics of an application that are relevant to understanding the impact of power capping on performance.In this study, we (1) characterize the useful features of a metric that effectively captures time-to-solution and power performance dynamics; and (2) design and evaluate a novel set of application power efficiency (APE) metrics that accounts for time-to-completion, power utilization and power variability. Power utilization quantifies a system’s trapped capacity (unused power budget) and power variability quantifies an application’s variation of power consumption over time. We demonstrate how APE can be used to quantify application characteristics which, in turn, enables reasoning about the impacts of power capping on an application.

Toward systematic architectural design of near-term trapped ion quantum computers

Trapped ions (TIs) are a leading candidate for building Noisy Intermediate-Scale Quantum (NISQ) hardware. TI qubits have fundamental advantages over other technologies, featuring high qubit quality, coherence time, and qubit connectivity. However, current TI systems are small in size and typically use a single trap architecture, which has fundamental scalability limitations. To progress toward the next major milestone of 50--100 qubit TI devices, a modular architecture termed the Quantum Charge Coupled Device (QCCD) has been proposed. In a QCCD-based TI device, small traps are connected through ion shuttling. While the basic hardware components for such devices have been demonstrated, building a 50--100 qubit system is challenging because of a wide range of design possibilities for trap sizing, communication topology, and gate implementations and the need to match diverse application resource requirements. Toward realizing QCCD-based TI systems with 50--100 qubits, we perform an extensive application-driven architectural study evaluating the key design choices of trap sizing, communication topology, and operation implementation methods. To enable our study, we built a design toolflow, which takes a QCCD architecture's parameters as input, along with a set of applications and realistic hardware performance models. Our toolflow maps the applications onto the target device and simulates their execution to compute metrics such as application run time, reliability, and device noise rates. Using six applications and several hardware design points, we show that trap sizing and communication topology choices can impact application reliability by up to three orders of magnitude. Microarchitectural gate implementation choices influence reliability by another order of magnitude. From these studies, we provide concrete recommendations to tune these choices to achieve highly reliable and performant application executions. With industry and academic efforts underway to build TI devices with 50-100 qubits, our insights have the potential to influence QC hardware in the near future and accelerate the progress toward practical QC systems.

Hybrid Energy Efficiency Friendly Frequency Domain TR Algorithm Based on PSO Algorithm Evaluated by Novel Maximizing HPA Efficiency Evaluation Criteria

Smart Grids (SGs) expedite secure, large-scale and efficient two-way communication between the power supply and management, but under a sophisticated 5G communication infrastructure, the multi carrier system is the principle system. The high peak-to-average power ratio (PAPR) is one of the significant limitations of the 5G multi carrier (MC) system, as it impedes the efficient design of the 5G analogue front end. Tone reservation (TR) is a highly efficient scheme without signal distortion, which is designed by increasing the freedom in the frequency domain for PAPR reduction. In this paper, a particle swarm optimization (PSO) based TR (PSO-TR) scheme proceeding with an optimal input power back off-modulation error ratio (IBO-MER) convergence criterion is proposed to improve high power amplifier (HPA) efficiency for OFDM systems. A probabilistic analysis of TR predistribution and freedom in the frequency domain, in relationship with the amplitude of its constituent samples, is carried out. This yields the theoretical framework employed in design of the proposed high computing-enhanced solutions. The proposed PSO-TR essentially make the frequency domain distribution and operation itself adaptive, that is, it adjusts to comply with the changing HPA efficiency and redundant cost during application runtime.