Application Of Field Programmable Gate Array Research Articles

FPGA acceleration of convolutional neural networks: Current applications and future prospects

In the contemporary era of big data, the utilization of deep learning technology has become widespread in the extraction of valuable analytical insights from the data under consideration. This technology finds extensive applications in various domains, including image information recognition, speech processing, and text language analysis. When it comes to accelerating convolutional neural networks (CNNs), the utilization of Field-Programmable Gate Arrays (FPGAs) offers distinct advantages over other hardware accelerators. Nevertheless, it is important to acknowledge that FPGA-based acceleration also comes with its own structural limitations. This article places its focus on two main aspects: firstly, it delves into the present-day application landscape and the latest developmental trajectories of convolutional neural networks. Secondly, it elucidates the inherent characteristics of FPGA implementations of CNNs. Furthermore, the article conducts a comprehensive examination of the pertinent constraints associated with FPGA-accelerated deep learning algorithms. The discussion extends beyond the present moment and ventures into the future, offering insights into the potential advancements in the field of deep learning. Importantly, it also brings into focus the prospective avenues for further research regarding the application of FPGAs in the domain of convolutional neural networks.

FPGA-Based Optimization of Industrial Numerical Machine Tool Servo Drives

This paper presents an analysis of the advantages stemming from the application of field-programmable gate arrays (FPGAs) in servo drives used within the control systems of industrial numerical machine tools. The method of improving the control system that allows for increasing the precision of machining, as well as incorporating new functionalities and streamlining diagnostic processes, is described. As demonstrated, the utilization of digital controllers with robust computational power and high-performance real-time communication interfaces is essential for achieving these objectives. This study underscores the limitations of commonly employed digital controllers in servo drives, which are constructed based on microcontrollers or signal processors collaborating with application-specific integrated circuits (ASICs). In contrast, the proposed FPGA-based solution offers substantial computational power and significantly reduced latencies in the real-time communication interface compared to other examined alternatives. This enables the realization of the planned objectives, specifically the enhancement of technical parameters and diagnostic capabilities of machine tools. Furthermore, the research indicates that FPGA-based digital controllers exhibit relatively low power consumption and a simplified design of the electronic printed circuit board in comparison to other analyzed digital platforms. These features can contribute to heightened reliability and diminished production costs of such controllers. Additional conclusions drawn from the study indicate that FPGA-based controllers provide greater developmental possibilities and their production is marked by potential resilience to challenges associated with the availability of electronic components in the market.

An FPGA application of home security code using verilog

Traditional entrance keys performed a number of drawbacks, including the ease with which they can be stolen, duplicated, or misplaced, allowing unauthorized people to gain access to cash, valuables, and other important documents. As known, most digital electronic entrance locks use application specific integrated circuits (ASICs) as based, which have the disadvantage of being unable to be reconfigured, as opposed to field programmable gate arrays (FPGA). This project proposed a home security code lock using verilog hardware descriptive language (HDL) with two unlocking modes, using a button or a keypad which can be changed using a switch. The 7-segment on the Altera DE2-115 trainer board is used to display the passcode press by the keypad. The result of simulation on the keypad using finite state machine (FSM) technique was fulfill the theoretical concept in which it will go to the next state each time the correct input or passcode was entered. When the wrong input or passcode was entered, it will be entered to reset mode. As the conclusion, a fully comply output according to the theoretical FSM concept is fully achieved in this project.

An Optimized Pipeline Based Blind Source Separation Architecture for FPGA Applications

This work proposes an optimized blind source separation (BSS) architecture utilizing accumulator-based radix 4 multipliers incorporating an independent component analysis (ICA) approach. The signal observed in distinct environmental conditions degraded from its original form. ICA-based filtering is a suitable choice for recovering the desired signal components. Field Programmable Gate Array (FPGA) implementation makes the design much more attractive in high-performance. The proposed BSS-ICA architecture consists of three Random Access Memory (RAM) units and a pipeline-based accumulator radix-4 multiplier. In this work, different source signals such as sinusoidal and speech signals are considered for the analysis. The sources signals are combined with the mixing signal and the resultant signals are processed using the proposed architecture. The pipeline utilized accumulator radix-4 multiplier structure in the proposed design provides good performance in terms of speed and area. The performance of the proposed architecture is analysed using Simulink and FPGA and the results are reported. The speed of the proposed structure is improved by about 19.33% when compared with the conventional design. Likewise, the area (slices) optimization of about 27.27% is achieved for the proposed structure when examined with the existing approach. Hence, the proposed architecture separates the designed signal component with a lesser area and high speed.

A sliced architecture using novel configurable logic modules in quantum dot cellular automata for application of field-programmable gate arrays

A sliced architecture using novel configurable logic modules in quantum dot cellular automata for application of field-programmable gate arrays

The Impact of Terrestrial Radiation on FPGAs in Data Centers

Field programmable gate arrays (FPGAs) are used in large numbers in data centers around the world. They are used for cloud computing and computer networking. The most common type of FPGA used in data centers are re-programmable SRAM-based FPGAs. These devices offer potential performance and power consumption savings. A single device also carries a small susceptibility to radiation-induced soft errors, which can lead to unexpected behavior. This article examines the impact of terrestrial radiation on FPGAs in data centers. Results from artificial fault injection and accelerated radiation testing on several data-center-like FPGA applications are compared. A new fault injection scheme provides results that are more similar to radiation testing. Silent data corruption (SDC) is the most commonly observed failure mode followed by FPGA unavailable and host unresponsive. A hypothetical deployment of 100,000 FPGAs in Denver, Colorado, will experience upsets in configuration memory every half-hour on average and SDC failures every 0.5–11 days on average.

NOP-DH – Evaluation Over Bitonic Sort Algorithm

The growing use of Field Programmable Gate Array (FPGA) to increase application performance requires tools that simplify the digital circuit development process. Traditional approaches of Hardware Description Languages (HDLs) are complex and require specialized knowledge at a low-level abstraction. In turn, different approaches called High-Level Synthesis (HLS) aim at facilitating the development of FPGA applications, making this development process closer to those of software using programming languages such as C or C++. However, these alternatives do not properly exploit the parallelism capability of FPGAs as they are based on usual sequential approaches and, moreover, continue to depend on developer technical knowledge about the target hardware. The Notification Oriented Paradigm (NOP) emerges as an alternative to develop and execute applications. The NOP brings a new inference concept based on precise notifying collaborative entities. This type of inference allows presenting an innovative way of implicitly achieving decoupled and decentralized solutions, thereby enabling parallelism and distribution in a level of granularity as fine as possible in the envisaged computational platform. In this context, researches on NOP have proposed the design of digital circuits based on the NOP model, called NOP Digital Hardware (DH). In this paper, it is proposed to evaluate the use of the NOP-DH to develop the well-known Bitonic Sort, which is a sort algorithm useful as benchmark. This algorithm has particular properties that are advantageous for parallel execution, especially in FPGAs. Experiments were performed to compare the performance, amount of logic elements, and maximum frequency of NOP-DH against the traditional VHDL approach. These experiments demonstrated that even with a higher abstraction level of development, NOP-DH circuits achieve similar results when compared to the traditional development in VHDL.

Application of FPGA in Process Tomography Systems

This paper will provide some insights on the application of Field Programmable Gate Array (FPGA) in process tomography. The focus of this paper will be to investigate the performance of the technology with respect to various tomography systems and comparison to other similar technologies including the Application Specific Integrated Circuit (ASIC), Graphics Processing Unit (GPU) and the microcontroller. Fundamentally, the FPGA is primarily used in the Data Acquisition System (DAQ) due to its better performance and better trade-off as compared to competitor technologies. However, the drawback of using FPGA is that it is relatively more expensive.

XUAVs: Towards Efficient Approximate Computing for UAVs—Low Power Approximate Adders With Single LUT Delay for FPGA-Based Aerial Imaging Optimization

High Definition (HD) image processing and real-time analytics over live video feeds have always been the key requirements for Intelligence, Surveillance and Reconnaissance (ISR) applications. With the evolution of optics and image enhancement techniques, computational loads of HD ISR systems are also rising exponentially. On the contrary, the slow-down of Moore's Law has recently posed challenging bounds over the level of achievable miniaturization for emerging processing and storage units. Field Programmable Gate Arrays (FPGAs) offer a popular choice of implementing ISR algorithms over resource-constrained platforms, such as Unmanned Aerial Vehicles (UAVs), due to favorable features of reconfigurability and rapid prototyping. A promising solution to bridge the gap between resource-constrained host platforms and computation-intensive FPGA applications is the paradigm of Approximate Computing. It compromises on the accuracy of processed results to offer significant performance gains for error-tolerant applications, such as video and image processing. In this paper, we present a novel approximate adder design methodology, for FPGA-based systems with improved SWaP performance, besides preserving the accuracy requirements within acceptable thresholds. The design methodology proposed in this paper focuses on the FPGA-specific Look-Up Table (LUT) architecture to introduce approximations while splitting the carry chain into LUT-based sub-adders, with flexible overlap to tune the adder's accuracy and achieve the overall latency of a single LUT. The paper presents several variants of the proposed design and offers application-oriented flexibility to adjust for optimal SWaP vs accuracy trade-off. We have further devised a comprehensive assessment approach to verify functional viability of the proposed atomic arithmetic blocks at system level, through their implementation into dense computational imaging applications, such as 2-dimensional Discrete Cosine Transform (DCT), airborne self-localization and moving object tracking algorithms, in comparison with other state-of-the-art adders. Our most accurate design performs at least 9.9% better in power consumption when compared with existing approximate adders, which proves that the proposed methodology holds promising potential to improve SWaP-index for computation-intensive UAV applications.

New Mathblocks-Based Feistel-Like Ciphers for Creating Clone-Resistant FPGA Devices

The Secret Unknown Cipher (SUC) concept was introduced a decade ago as a promising technique for creating pure digital clone-resistant electronic units as alternatives to the traditional non-consistent Physical Unclonable Functions (PUFs). In this work, a very special unconventional cipher design is presented. The design uses hard-core FPGA (Field Programmable Gate Arrays) -Mathblocks available in modern system-on-chip (SoC) FPGAs. Such Mathblocks are often not completely used in many FPGA applications; therefore, it seems wise to make use of such dead (unused) modules to fabricate usable physical security functions for free. Standard cipher designs usually avoid deploying multipliers in the cipher mapping functions due to their high complexity. The main target of this work is to design large cipher classes (e.g., cipher class size >2600) by mainly deploying the FPGA specific mathematical cores. The proposed cipher designs are novel hardware-oriented and new in the public literature, using fully new unusual mapping functions. If a random unknown selection of one cipher out of 2600 ciphers is self-configured in a device, then a Secret Unknown Cipher module is created within a device, making it physically hard to clone. We consider the cipher module for free (for zero cost) if the major elements in the cipher module are making use of unused reanimated Mathblocks. Such ciphers are usable in many future mass products for protecting vehicular units against cloning and modeling attacks. The required self-reconfigurable devices for that concept are not available now; however, they are expected to emerge in the near future.

Application-Dependent Testing of FPGA Interconnect Network

The extensive application of field-programmable gate array (FPGA) devices in industrial environments makes FPGA testing a significant area of exploration. The application-dependent testing approach ensures better manufacturing yield compared to the manufacturing testing process since it can bypass the faulty parts without disturbing a given user-defined design. The interconnection resources occupy a large area in the FPGA die, and it is highly error-prone due to the presence of a huge number of transistors. Interconnection resources testing play a major role in the reconfigurable hardware testing area. This paper presents an application-dependent testing technique to generate test configurations for interconnects in static RAM (SRAM)-based FPGAs. To generate a test pattern for interconnects, logic block configurations have been modified. This paper addresses stuck-at faults, different types of dominant bridging faults, and feedback bridging faults. Appropriate constraints have been designed using Boolean satisfiability to test the above faults in the interconnects. Simulations performed on ISCAS’89, MCNC, and ITC’99 benchmark circuits mapped on different FPGA architectures show that the proposed approach can obtain a minimum number of test configurations with 100% fault coverage for the above-mentioned faults and is technology independent which enables it to address new emerging architectures in FPGAs.

A Network Analysis Modeling Method of the Power Electronic Converter for Hardware-in-the-Loop Application

The application of field-programmable gate array (FPGA) in the hardware-in-the-loop simulation (HiLs) has enabled the time step reaching the range of hundreds of nanoseconds. However, the time performance of FPGA-based real-time simulation remains to be improved. In this article, a network analysis modeling method for FPGA-based real-time simulation of the power electronic converter is proposed. An ideal switching network unit, without requiring a large amount of memory, is used to determine the topology of the circuit and solve interface voltages/currents from the torn circuit. A parallel integration method is then implemented to obtain the status of the circuit element. At last, a diode-clamped three-level voltage source converter is used as a case study to demonstrate the effectiveness of the method. A 40-ns simulation step is finally achieved on the National Instruments (NI) FlexRIO PXIe-7975 platform. The accuracy of the proposed method is also verified against the results from MATLAB/Simulink.

FPGA-Based Real-Time Simulation of High-Power Electronic System With Nonlinear IGBT Characteristics

The hardware-in-the-loop simulation plays a vital role in the test of high-power electronic system. Although the application of field-programmable gate array (FPGA) embedded system has enabled the real-time system simulating below 500 ns, the transient characteristic of high-voltage insulated-gate bipolar transistor (HVIGBT) is largely compromised. In this paper, a new piecewise HVIGBT model, considering its driver circuit effect and parasite parameter, is proposed for FPGA-based real-time simulation applications. With the attempt to reduce the simulation latency, we propose an FPGA solver with a parallel structural to divide the system into several layers. The model could not only provide accurate system-level performance of the power electronic converter but also give an insight into the transient behavior effect of high-power electronic system. Finally, a case study about emulation of traction system of high-speed train is also presented. Implementations are made on an FPGA Kintex-7 embedded in National Instruments FlexRIO PXIe-7975. The obtained results show that the proposed modeling algorithm can achieve both accuracy and efficiency within a fixed real-time simulation time step of 25 ns.

Low Latency Event-Based Filtering and Feature Extraction for Dynamic Vision Sensors in Real-Time FPGA Applications

Dynamic Vision Sensor (DVS) pixels produce an asynchronous variable-rate address-event output that represents brightness changes at the pixel. Since these sensors produce frame-free output, they are ideal for real-time dynamic vision applications with real-time latency and power system constraints. Event-based filtering algorithms have been proposed to post-process the asynchronous event output to reduce sensor noise, extract low level features, and track objects, among others. These postprocessing algorithms help to increase the performance and accuracy of further processing for tasks such as classification using spike-based learning (ie. ConvNets), stereo vision, and visually-servoed robots, etc. This paper presents an FPGA-based library of these postprocessing event-based algorithms with implementation details; specifically background activity (noise) filtering, pixel masking, object motion detection and object tracking. The latencies of these filters on the Field Programmable Gate Array (FPGA) platform are below 300ns with an average latency reduction of 188% (maximum of 570%) over the software versions running on a desktop PC CPU. This open-source event-based filter IP library for FPGA has been tested on two different platforms and scenarios using different synthesis and implementation tools for Lattice and Xilinx vendors.

Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are used for a wide variety of computations in low-cost embedded systems. Although these systems often have modest performance constraints, their energy consumption must typically be limited. Many FPGA applications employ repetitive loops that cannot be straightforwardly split into parallel computations. Performing a loop sequentially generally requires high-speed clocks that consume considerable clock power and sometimes require clock generation using a phase-locked loop (PLL). Loop unrolling addresses the high-speed clock issue, but its use often leads to significant combinational glitch power. In this work, a computer-aided design (CAD) approach that unrolls loops for designs targeted to low-cost FPGAs is described. Our approach considers latency constraints in an effort to minimize energy consumption for loop-based computation. To reduce glitch power, a glitch-filtering approach is introduced that provides a balance between glitch reduction and design performance. Glitch-filter enable signals are generated and routed to the filters using resources best suited to the target FPGA. Our approach automatically inserts glitch filters and associated control logic into a design prior to processing with FPGA synthesis, place, and route tools. Our energy-saving loop-unrolling approach has been evaluated using five benchmarks often used in low-cost FPGAs. The energy-saving capabilities of the approach have been evaluated for an Intel Cyclone IV and a Xilinx Artix-7 FPGA using board-level power measurement. The use of unrolling and glitch filtering is shown to reduce energy by at least 65% for an Artix-7 device and 50% for a Cyclone IV device while meeting design latency constraints.

Design of Pocket Development Board Based on FPGA

With the development of programmable technology, the application of FPGA (field programmable gate array) technology is also more and more widely. In order to facilitate the students in the school to learn more about the FPGA development process and improve the practical ability of the students, a FPGA chip based on practicality is designed and suitable Experimental teaching pocket development board, can be convenient for students to carry, and low cost; this small development board to achieve some simple experiments, as a tool for students to learn hardware, rapid development of students’ good experimental ability.

(Invited) 3D Monolithic Integration

3D monolithic integration, also named 3D sequential integration, consists in stacking active device layers on top of each other in a sequential manner. It differs from 3D Packaging where the tiers are fabricated in parallel and then stacked together using a bonding step bonding step (copper to copper or hybrid bonding for example). The monolithic flow offers unique 3D connectivity opportunities: indeed, as the top active patterning is defined by lithography and can be aligned with respect to bottom tiers (alignment marks being seen by transparency), the alignment accuracy and feature size of stacked tiers and inter-tier interconnections are only limited by stepper resolution and not by bonding alignment accuracy like 3D packaging. This allows ultra-high density of 3D vias: state-of-the-art 3D packaging achieves a maximum density of 105 vias/mm2 while 3DSI demonstration using conservative 65nm design rules already achieves a maximum density of 2.107 via/mm2 [1]. However it comes at the cost of thermal budget constraints for top layer processing, as it will be necessary to realize the top tiers without degrading electrical and morphological performances of bottom tiers. In this paper we will review the different fields of application of 3D monolithic integration and describe the related processing options. Furthering Moore’s law for high-performance applications was the original driver for 3D sequential integration. It can be seen at the gate granularity scale, meaning optimizing NMOSfets and PMOSfets independently in two separate layers. This case would offer very fine tuning options on each level (e.g: channel material, strain boosters, substrate orientation, etc.) and avoid costly and complex co-integration steps [2,3]. It can also be seen at the circuit granularity scale by stacking CMOS over CMOS to boost IC speed performance. It can be obtained by reducing the wire length and then the interconnection delay. Performance Power Area (PPA) evaluations have been carried out with various outcomes depending on the application case study, technology node and place and route methodologies [4]. For FPGA (field programmable gate arrays) applications for example, it has been evidenced that 3D sequential integration enables one to reach the PPA of nodes n+1 by stacking 2 n tiers, enabling one to keep following Moore’s law without resorting to straight device scaling [5-7]. Is also important to note that new approaches for “big data” processing such as in-memory and neuromorphic computing require large amounts of on-chip memory with a high density of interconnects between core and memory and 3D Monolithic appears to be an adequate candidate [8]. Maximum thermal budget and technology solutions to realize such integration will be presented. 3D Monolithic can also be very interesting in a Moore than Moore scheme like 3D smart sensors. Lower parasitic capacitance in 3D vias obtained with a monolithic configuration compared to 3D packaging with TSVs could increase data transfer bandwidth. For these sensing applications, analog devices will be needed and depending on their positioning in the 3D stack, may have to be realized with a limited thermal budget. If another tier is realized above they will also need to be resistant to additional thermal budgets. This stability as well as their feasibility with a limited thermal budget must be evaluated. For this latter, technological knowledge on silicides which is usually the first limiting element in thermal budget stability will be presented [9,10]. References : [1] L. Brunet et al., VLSI 2016, [2] P. Batude et al., IEDM 09, [3] P. Batude et al, VLSI 09, [4] M. Jung et al., TCPMT 2015, S. Panth et al., Journal of Information and Communication Convergence Engineering 2014, , [5] O. Turkyilmaz et al., DATE 2014, [6] ITRS 2013, “System driver summary”. http://public.itrs.net, [7] ITRS 2013, “ORTC”. http://public.itrs.net, [8] M. M. Sabry Aly et al., Computer, vol. 48, no. 12 2015, [9] C. Fenouillet-Beranger et al., ESSDERC 2014, [10] C. Fenouillet-Beranger et al., IEDM 2014

Three Ages of FPGAs: A Retrospective on the First Thirty Years of FPGA Technology: This Paper Reflects on How Moore's Law Has Driven the Design of FPGAs Through Three Epochs: the Age of Invention, the Age of Expansion, and the Age of Accumulation

Since their introduction, field programmable gate arrays (FPGAs) have grown in capacity by more than a factor of 10 000 and in performance by a factor of 100. Cost and energy per operation have both decreased by more than a factor of 1000. These advances have been fueled by process technology scaling, but the FPGA story is much more complex than simple technology scaling. Quantitative effects of Moore?s Law have driven qualitative changes in FPGA architecture, applications and tools. As a consequence, FPGAs have passed through several distinct phases of development. These phases, termed Ages in this paper, are The Age of Invention, The Age of Expansion and The Age of Accumulation. This paper summarizes each and discusses their driving pressures and fundamental characteristics. The paper concludes with a vision of the upcoming Age of FPGAs.

The Application of FPGA Based Real-Time Processing ESN in Pattern Recognition and Waveform Generation

In this paper, a real-time hardware-based Field Programmable Gate Array (FPGA) architecture Echo state network (ESN) of recurrent neural network (RNN), which real-timely gets the output weights of Reservoir Computing (RC) in FPGA, was used for pattern recognition and waveform generation. It is designed in strict accordance with the RC theory. The four parts of RC, which is input layer, reservoir layer, output layer, and weight training block, were all built in FPGA. The training of the RC was finished in real-time. We have verified its performance through implemented and verification in Altera FPGA. Experimental results showed that the real-time hardware RC can remember the ratio and recognize different period after it was trained as it was trained.

High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array

The huge area overhead of the interconnect is one of the critical issues in static random access memory (SRAM)-based field-programmable gate arrays (FPGAs), resulting in high power consumption and slow operation speed. Another critical issue is the volatile feature of the SRAM, which leads to high standby leakage current and long power-ON time. Resistive random access memory (RRAM) with a high resistance ratio and zero standby power possesses great potential in the FPGA applications. The conventional RRAM-based nonvolatile FPGAs (NVFPGAs) may use one-transistor 2-RRAM (1T2R) storage element to replace the SRAM or the one RRAM (1R) cell to replace both nMOS switch and SRAM. However, those NVFPGA schemes may suffer from the issues of low reliability, high configuration power, and high active leakage power. In this paper, we propose a novel element [one-diode two-RRAM (1D2R) cells] to replace the nMOS switch and 6 Transistors (6T) SRAM. Meanwhile, the novel block structures of the logic block, connection block, switch block, and the FPGA architecture based on the 1D2R element are proposed. Compared with the conventional 1T2R-based NVFPGA, our novel structure could improve the operation speed by 53% with a 40.5% lower operation power. Compared with the conventional 1R-based NVFPGA, the proposed scheme could greatly reduce the write error rate by eight orders with more than 20 times lower write power.