Application Mapping Problem Research Articles

NoC Application Mapping Optimization Using Reinforcement Learning

Application mapping is one of the early stage design processes aimed to improve the performance of Network-on-Chip. Mapping is an NP-hard problem. A massive amount of high-quality supervised data is required to solve the application mapping problem using traditional neural networks. In this article, a reinforcement learning–based neural framework is proposed to learn the heuristics of the application mapping problem. The proposed reinforcement learning–based mapping algorithm (RL-MAP) has actor and critic networks. The actor is a policy network, which provides mapping sequences. The critic network estimates the communication cost of these mapping sequences. The actor network updates the policy distribution in the direction suggested by the critic. The proposed RL-MAP is trained with unsupervised data to predict the permutations of the cores to minimize the overall communication cost. Further, the solutions are improved using the 2-opt local search algorithm. The performance of RL-MAP is compared with a few well-known heuristic algorithms, the Neural Mapping Algorithm (NMA) and message-passing neural network-pointer network-based genetic algorithm (MPN-GA). Results show that the communication cost and runtime of the RL-MAP improved considerably in comparison with the heuristic algorithms. The communication cost of the solutions generated by RL-MAP is nearly equal to MPN-GA and improved by 4.2% over NMA, while consuming less runtime.

Network‐on‐chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation

With the development of network-on-chip (NoC) theory, lots of mapping algorithm have been proposed to solve the application mapping problem which is an NP-hard (non-polynomial hard) problem. Most algorithms are based on a heuristic algorithm. They are trapped by iterations limited, not by the distance between iterations, because of the isomorphism of mapping sequence. In this study, the authors define and analyse the isomorphism with the genetic algorithm (GA) which is a heuristic algorithm. Then, they proposed an approach called density direction transform algorithm to eliminate the isomorphism of mapping sequence and accelerate the convergence of population. To verify this approach, they developed a density-direction-based genetic mapping algorithm (DDGMAP) and make a comparison with genetic mapping algorithm (GMA). The experiment demonstrates that compared to the random algorithm, their algorithm (DDGMAP) can achieve on an average 23.48% delay reduction and 7.15% power reduction. And DDGMAP gets better performance than GA in searching the optimal solution.

An Effective Optimization Algorithm for Application Mapping in Network-on-Chip Designs

The application mapping problem is an NP-hard combinatorial optimization problem in network-on-chip (NoC) design. Applications of size (n > 30) cannot be solved optimally by an exact algorithm in reasonable time, and the evolutionary algorithms have drawn the attention of NoC researchers. In this paper, we propose a new effective optimization method based on the discrete particle swarm optimization framework, which includes the novel principles for representation, velocity computing, and position-updating of the particles. In our proposed method, particles are allowed to swing between elite and regular pools, and a simple local search procedure is applied on elite particles to exploit the promising solutions. Extensive computational studies using standard benchmark instances and task graphs for free (TGFF) random instances reveal that the proposed optimization algorithm is able to attain the best results, and thus competes very favorably with the previously proposed heuristic approaches. A stability analysis and the two-sided Wilcoxon rank sum tests are also presented to shed light on the robust behavior of the algorithm.

Multi-objective algorithms for the application mapping problem in heterogeneous multiprocessor embedded system design

Design at the Electronic System-Level tackles the increasing complexity of embedded systems by raising the level of abstraction in system specification and modeling. Two important steps in this process are evaluation of a single design configuration and design space exploration. The exponential size of the design space, along with the complex task of simulating a single design point, makes it impossible to explore the design space efficiently in almost all MPSoC design situations. In order to overcome this problem, one or both of the main steps of the design process (i.e., simulation and exploration) must be accelerated. In this paper, for the first part of the design process, high-level analytical models for application mapping and evaluation are presented in order to accelerate the evaluation of a single design configuration. In the second part of the design process, two multi-objective optimization algorithms that are based on particle swarm optimization and simulated annealing have been proposed for performing design space exploration. Considering multimedia applications as case studies, each of these methods produces a set of near-optimal points. Simulation results show that the proposed methods can lead to near-optimal design configurations with acceptable accuracy in a reasonable time.

Fault-Tolerant Dynamic Task Mapping and Scheduling for Network-on-Chip-Based Multicore Platform

In Network-on-Chip (NoC)-based multicore systems, task allocation and scheduling are known to be important problems, as they affect the performance of applications in terms of energy consumption and timing. Advancement of deep submicron technology has made it possible to scale the transistor feature size to the nanometer range, which has enabled multiple processing elements to be integrated onto a single chip. On the flipside, it has made the integrated entities on the chip more susceptible to different faults. Although a significant amount of work has been done in the domain of fault-tolerant mapping and scheduling, existing algorithms either precompute reconfigured mapping solutions at design time while anticipating fault(s) scenarios or adopt a hybrid approach wherein a part of the fault mitigation strategy relies on the design-time solution. The complexity of the problem rises further for real-time dynamic systems where new applications can arrive in the multicore platform at any time instant. For real-time systems, the validity of computation depends both on the correctness of results and on temporal constraint satisfaction. This article presents an improved fault-tolerant dynamic solution to the integrated problem of application mapping and scheduling for NoC-based multicore platforms. The developed algorithm provides a unified mapping and scheduling method for real-time systems focusing on meeting application deadlines and minimizing communication energy. A predictive model has been used to determine the failure-prone cores in the system for which a fault-tolerant resource allocation with task redundancy has been performed. By selectively using a task replication policy, the reliability of the application, executing on a given NoC platform, is improved. A detailed evaluation of the performance of the proposed algorithm has been conducted for both real and synthetic applications. When compared with other fault-tolerant algorithms reported in the literature, performance of the proposed algorithm shows an average reduction of 56.95% in task re-execution time overhead and an average improvement of 31% in communication energy. Further, for time-constrained tasks, deadline satisfaction has also been achieved for most of the test cases by the developed algorithm, whereas the techniques reported in the literature failed to meet deadline in about 45% test cases.

Energy-efficient contention-aware application mapping and scheduling on NoC-based MPSoCs

We consider the problem of energy-efficient contention-aware application mapping and scheduling on Network-on-Chip (NoC) based multiprocessors. For an application represented by a directed acyclic graph, we present a model where voltage scaling techniques for processors can be combined with frequency tuning techniques for NoC links to save overall system energy consumption. We employ a two-step approach to solve the overall mapping and scheduling problem. First, the application mapping problem is formulated as a quadratic binary programming problem, which aims to minimize the communication energy; we apply a relaxation-based iterative rounding algorithm to solve it. With the mapping achieved, we further consider the application scheduling problem, which aims to find the optimal voltage level for each task of the application and optimal frequency level for each communication of the application to minimize the overall system energy consumption, given the application deadline. To attack the second problem, we first design an algorithm based on the earliest time first scheduling to determine the application’s finish time if a voltage and frequency assignment is given; then, we develop a genetic algorithm to search the solution space for the voltage and frequency assignment that minimizes the overall system energy consumption and meets the application’s deadline. Through these two steps, we produce a mapping and scheduling that meets the application’s deadline, and significantly reduces the overall system energy consumption. Experiments are conducted for a number of randomly generated application graphs, as well as several real application graphs to verify the energy reduction and applicability of the proposed model and algorithms.

A novel heuristic algorithm for IP block mapping onto mesh-based networks-on-chip

With advancement in the nanometer era, more and more intellectual property (IP) blocks can be integrated on a single die. Network-on-chip (NoC) has emerged as a viable alternative to unplug the communication bottleneck in system-on-chip. In the NoC synthesis flow, IP block mapping problem is one of the holistic research problems, which aims to minimize the overall communication cost or power consumption of the network. Since mesh is a well-accepted topology, we focus on IP mapping problem onto mesh-based NoCs in this paper. The IP mapping problem is proven to be NP-hard. No exact algorithm is expected to solve it in the polynomial time, and considerable computation time is required for even small-scale instances. In this paper, we analyze the symmetry character in mesh and propose an adaptive memetic algorithm (AMA) to solve the application mapping problem. The novel AMA method integrates both global and local optimization techniques, which contributes to the effectiveness and efficiency of the algorithm. Experiments have been carried out under both real application and synthetic benchmarks. Experimental results indicate that the proposed AMA outperforms the existing heuristics (CastNet and genetic algorithm) in the aspects of solution quality and power consumption. Within acceptable time limit, AMA could obtain optimal or suboptimal solutions when compared with the exact algorithm.

Application Mapping onto Butterfly-Fat-Tree based Network-on-Chip using Discrete Particle Swarm Optimization

paper addresses the problem of application mapping onto Butterfly-Fat-Tree (BFT) based Network-on-Chip design. It proposes a new mapping technique based on discrete Particle Swarm Optimization (PSO) to map the cores of the core graph to the routers. The basic PSO has been augmented by running multiple PSO and deterministically generating a part of the initial population for PSO. The mapping results have been compared with well-known techniques reported in the literature for a number of benchmark applications. The reported strategy produces results superior to those obtained via existing approaches within a reasonable CPU time. Keywordsmapping, Network-on-Chip, System-on-Chip, Butterfly-Fat-Tree, Discrete Particle Swarm Optimization

Evaluation of energy and buffer aware application mapping for networks-on-chip

Networks-on-Chip (NoC) is a communication paradigm for Systems-on-Chip (SoC). NoC design flow contains many problems, one of which is called as application mapping problem, which is generally solved in the literature by considering minimization of the communication energy consumption only. Energy and Buffer Aware Application Mapping (EBAM) is a recently proposed method, which handles the application mapping issue as a joint optimization problem for minimizing the energy consumption and buffer utilization simultaneously. EBAM avoids possible high input loads on router buffers at the early mapping stage by using a priori traffic characteristics of the application. Self similarity is already an accepted model in local and wide area networks and many on-chip applications have also been proven to have self similar characteristics. EBAM therefore employs self similar traffic in its joint optimization process and a genetic algorithm is already proposed for its solution.This paper presents a simulation study that evaluates EBAM in terms of network parameters such as buffer utilization and end-to-end delay. For this, a self-similar traffic generator module is implemented first on a well known NoC simulator and then buffer utilization of routers and end-to-end delay under self similar traffic are observed. Simulation results show that the method enhances buffer utilization and end-to-end delay against a reasonable energy trade off.A routing protocol selection task follows the mapping stage in a typical NoC design flow hence our paper also presents a computational study that evaluates the effect of EBAM use on commonly encountered on-chip routing algorithms. Results reveal that simple XY routing protocol, compared to others, performs better on mappings obtained by EBAM, which indicates that the need for complicated routing protocols may be eliminated.

Energy and buffer aware application mapping for networks-on-chip with self similar traffic

Networks-on-chip (NoC) is a promising on-chip communication paradigm that improves scalability and performance of System-on-Chips. NoC design flow contains many problems from different areas, such as networking, embedded design and computer architecture. Application mapping is one of these problems, which is generally considered in the form of a communication energy minimization problem. Self similarity is a traffic model that is used to characterize Ethernet and/or wide area network traffic, as well as on-chip network traffic. The present paper tackles the application mapping problem from a networking point of view using self similar traffic assumption and aims to find a mapping solution that improves network performance in terms of buffer utilization while simultaneously minimizing the total communication energy consumption. In this study, by using a self similar on-chip traffic characterization, an application mapping problem definition, which contains both energy and buffer utilization concerns is proposed. In order to solve this intractable problem, a genetic algorithm based solution is derived and implemented. Execution of the algorithm on different test cases has proven that such a mapping formulation avoids high buffer over utilizations while keeping the communication energy requirement still low.

Developing Domain-Knowledge Evolutionary Algorithms for Network-on-Chip Application Mapping

This paper addresses the Network-on-Chip (NoC) application mapping problem. This is an NP-hard problem that deals with the optimal topological placement of Intellectual Property cores onto the NoC tiles. Network-on-Chip application mapping Evolutionary Algorithms are developed, evaluated and optimized for minimizing the NoC communication energy. Two crossover and one mutation operators are proposed. It is analyzed how each optimization algorithm performs with every genetic operator, in terms of solution quality and convergence speed. Our proposed operators are compared with state-of-the-art genetic operators for permutation problems. Finally, the problem is approached in a multi-objective way. Besides energy minimization, it is also aimed to map the cores such that a thermally balanced Network-on-Chip design is obtained. It is shown, through simulations on real applications, that by using domain-knowledge, our developed genetic operators increase the algorithms’ performance. By comparing these Evolutionary Algorithms with an Optimized Simulated Annealing, it is shown that they perform better. In the case of two contradictory objectives, our genetic operators can still help at providing the mappings with the lowest communication energy.

A3MAP

In this article, we propose novel and global Architecture-Aware Analytic MAPping (A3MAP) algorithms applied to Networks-on-Chip (NoCs) not only with homogeneous Processing Elements (PEs) on a regular mesh network as done by most previous application mapping algorithms but also with heterogeneous PEs on an irregular mesh or custom network. As the main contributions, we develop a simple yet efficient interconnection matrix that can easily model any core graph and network. Then, an application mapping problem is exactly formulated to Mixed Integer Quadratic Programming (MIQP). Since MIQP is NP-hard, we propose two effective heuristics, a successive relaxation algorithm achieving short runtime, called A3MAP-SR and a genetic algorithm achieving high mapping quality, called A3MAP-GA. We also propose a partition-based application mapping approach for large-scale NoCs, which provides better trade-off between performance and runtime. Experimental results show that A3MAP algorithms reduce total hop count, compared to the previous application mapping algorithms optimized for a regular mesh network, called NMAP [Murali and Micheli 2004] and for an irregular mesh and custom network, called CMAP [Tornero et al. 2008]. Furthermore, A3MAP algorithms make packets travel shorter distance than CMAP, which is related to energy consumption.

Multiobjective optimization and evolutionary algorithms for the application mapping problem in multiprocessor system-on-chip design

Sesame is a software framework that aims at developing a modeling and simulation environment for the efficient design space exploration of heterogeneous embedded systems. Since Sesame recognizes separate application and architecture models within a single system simulation, it needs an explicit mapping step to relate these models for cosimulation. The design tradeoffs during the mapping stage, namely, the processing time, power consumption, and architecture cost, are captured by a multiobjective nonlinear mixed integer program. This paper aims at investigating the performance of multiobjective evolutionary algorithms (MOEAs) on solving large instances of the mapping problem. With two comparative case studies, it is shown that MOEAs provide the designer with a highly accurate set of solutions in a reasonable amount of time. Additionally, analyses for different crossover types, mutation usage, and repair strategies for the purpose of constraints handling are carried out. Finally, a number of multiobjective optimization results are simulated for verification.