ANPC Inverter Research Articles

A novel eight-switch nine-level modified ANPC inverter topology and its optimal modulation strategy

An eight-switch nine-level modified ANPC inverter (8S-9L-MANPC) is designed and simulated in this paper. With this topology, only one DC voltage source and eight active semiconductor switches are required, significantly reducing system size, weight, and cost. The structure consists of a five-level ANPC inverter cascaded with a two-level leg converter. This arrangement extends the 5L-ANPC structure to a 9L configuration without requiring the use of additional capacitors. To maintain the balancing of the flying capacitor (FC), a modulation strategy using a switching state redundancy-based control method is employed. Recent 9L inverters incorporating flying capacitors and based on a hybrid structure have been compared with the proposed structure. By conducting this comparison, we can highlight the potential improvements offered by the proposed structure over the recent 9L inverters in terms of reduced component count, simplified design, and cost savings. The proposed 8S-9L-MANPC inverter is tested under various operating situations in MATLAB/Simulink simulation.

Weighting Factors Autotuning of FCS-MPC for Hybrid ANPC Inverter in PMSM Drives Based on Deep Residual Networks

Weighting Factors Autotuning of FCS-MPC for Hybrid ANPC Inverter in PMSM Drives Based on Deep Residual Networks

Digital Twin Modeling and Multiparameter Monitoring Schemes of Three-Level ANPC Inverters

Digital Twin Modeling and Multiparameter Monitoring Schemes of Three-Level ANPC Inverters

Hybrid SVM for Enhanced Efficiency of 3L ANPC Inverter With Full ZVS Range

Hybrid SVM for Enhanced Efficiency of 3L ANPC Inverter With Full ZVS Range

A normalized compensation method for voltage nonlinearity of three-level ANPC inverter

A normalized compensation method for voltage nonlinearity of three-level ANPC inverter

Online Open-Circuit Fault Diagnosis for ANPC Inverters Using Edge-Based Lightweight Two-Dimensional CNN

Online Open-Circuit Fault Diagnosis for ANPC Inverters Using Edge-Based Lightweight Two-Dimensional CNN

Multi-Objective Cascaded Control Strategy for Grid-Connected Photovoltaic Energy Conversion System Using a Five-Level ANPC Inverter

Multi-Objective Cascaded Control Strategy for Grid-Connected Photovoltaic Energy Conversion System Using a Five-Level ANPC Inverter

Fractional-Order Extremum Seeking Based MPPT for Wind Energy Conversion System with PMSG and ANPC Inverter Using Model Predictive Control

In this paper, a real-time optimization-based extremum seeking (ES) approach is applied to a grid-connected PMSG-based wind energy conversion system (WECS) for maximum power point tracking (MPPT). The proposed model-free approach aims harness the output power of the WECS by controlling the system from the DC side, eliminating the need for speed sensor. Moreover, using fractional order calculus in ES improves the convergence speed and robustness compared with the conventional integer-order ES methods. Additionally, an MPC controller for the inner loop is designed to maintains fast transient response through ANPC inverter. Finally, the effectiveness of the proposed method is verified by simulating the WECS in MATLAB/Simulink environment. It was shown that the proposed method is feasible and robust under different weather conditions.

Design and Characterization of Bus Bars for 1MVA Three-level ANPC Inverters in Aerospace Applications

Design and Characterization of Bus Bars for 1MVA Three-level ANPC Inverters in Aerospace Applications

Power Layout Design of a GaN HEMTs-Based High Power High-Efficiency Three Level ANPC Inverter for 800 V DC Bus System

Power Layout Design of a GaN HEMTs-Based High Power High-Efficiency Three Level ANPC Inverter for 800 V DC Bus System

Switching Modes for Reduction of Peak Voltage Transients in GaN-Based Three Level ANPC Inverter

Switching Modes for Reduction of Peak Voltage Transients in GaN-Based Three Level ANPC Inverter

Investigation of a Low-Speed Commutation Voltage Shock Problem in Three-Level ANPC Inverter with Hybrid Modulation Mode

With the development of the photovoltaic industry; there will be an increasing demand for efficient, high-power density, and low-cost grid interface converters. Compared with two-level inverters, multilevel inverters have the following advantages: (1) lower device voltage ratings; (2) better output filtering spectrum; (3) lower electromagnetic interference (EMI) noise; and (4) higher switching speed capability. However, the complex switching circuit of the multilevel inverter will bring more parasitic inductance, resulting in severe switching overvoltage (ringing). Especially in order to reduce the cost of the inverter, using the long-loop modulation mode, the commutation loop will introduce more parasitic inductance, which will make the overvoltage more serious. Consider that commonly used overvoltage absorption schemes are effective only for overvoltage or suppression of oscillations. Therefore, a new overvoltage absorption circuit is proposed in this paper, which can not only alleviate the overvoltage and ringing phenomena but also suppress the effect of voltage jumps during low-frequency switching on high-frequency input voltage. This overvoltage absorption circuit is characterized by low overvoltage, fast ringing damping, and minimum capacitance. Experiments and simulations are conducted to verify the effectiveness of this overvoltage absorption circuit using a three-level ANPC inverter as a prototype. The results show that the proposed overvoltage absorption circuit can significantly reduce the overvoltage level, shorten the oscillation time, and reduce the voltage difference between the upper and lower DC bus capacitors.

Open-Circuit Fault Diagnosis for Three-Level ANPC Inverter Based on Predictive Current Vector Residual

Open-Circuit Fault Diagnosis for Three-Level ANPC Inverter Based on Predictive Current Vector Residual

Weighting-Factor-Less Model Predictive Control With Multiobjectives for Three-Level Hybrid ANPC Inverter Drives

Weighting-Factor-Less Model Predictive Control With Multiobjectives for Three-Level Hybrid ANPC Inverter Drives

Reliability analysis and reliable operation of three-level ANPC inverter

The three-level active neutral-point-clamped (3L-ANPC) inverters have been widely used in medium-voltage high-power electrical drives. The purpose of this paper is to achieve the reliable operation for 3L-ANPC inverters by reliability analysis and optimal switching and control strategies, while the performance of output waveforms of inverters is maintained. This paper starts by analyzing the power loss and the reliability of power semiconductor devices. On this basis, a mathematical model is derived for online condition monitoring of semiconductor devices. Then, the modulation strategies of the passive commutation mode and the active commutation mode are designed for the 3L-ANPC inverter, and the power loss distributions are analyzed among different semiconductor devices accordingly. Finally, three optimized strategies are designed to improve the reliability of the 3L-ANPC inverter under different load conditions based on different commutation modes and the developed reliability model. Both the simulation using MATLAB Simulink as well as PLECS have been conducted to verify the validity of analysis and control for improving reliability of 3L-ANPC inverters in this paper.

Five-Level Switched-Capacitor ANPC Inverter With Output Voltage Boosting Capability

This article proposes a three-phase five-level switched-capacitor active neutral point clamped converter, which can be characterized by voltage boost ability, low-voltage stress across semiconductor devices, and balance of floating capacitor voltage without any auxiliary circuits and/or sensors. Operating principles and modulation scheme of the proposed converter, as well as a comparative analysis with similar topologies are included. Simulation and experimental results for a three-phase prototype are given to demonstrate the feasibility of the proposed five-level converter.

Lifetime-based fault tolerant strategy for three-level hybrid ANPC inverters

Lifetime-based fault tolerant strategy for three-level hybrid ANPC inverters

Precise Electro-thermal Power Loss Model of a Three-level ANPC Inverter with Hybrid Si/SiC Switches

Hybrid Si/SiC switches constituting a parallel connection of a lower current rated SiC MOSFET and a higher current rated Si IGBT are becoming very attractive solution for designing high frequency and high-power density power electronic converters. Due to the complementary nature of Si IGBT devices (smaller inverter cost and smaller conduction loss) and SiC devices (smaller switching loss and higher junction temperature capability), these novel switch device configurations enable a good tradeoff between cost and efficiency for high power converter applications. One such recent application of hybrid Si/SiC switches for efficiency-cost optimization is an Si/SiC hybrid switch based ANPC inverter proposed in Ref. [30]. In Ref. [30] the topology structure, modulation strategy and the efficiency-cost benefits of the proposed ANPC inverter is presented. In this paper a precise electro-thermal power loss model for this ANPC inverter topology will be presented based on the modulation strategy of the inverter and the operating characteristics of the Si/SiC hybrid switches. The power loss model development takes into account how the current sharing between the two internal devices of the Si/SiC hybrid switches and their corresponding gate control method affects their power loss. A brief introduction to the topology structure and operation principle of the Si/SiC based ANPC inverter is first highlighted to provide context for readers and then a detailed description of the proposed electro-thermal power loss model is presented. The precision of the electro-thermal power loss model introduced in this paper is then validated using experimentally measured energy loss, device temperature and inverter efficiency data.

Reduced Vector Model Predictive Control of ANPC Inverter for PMSM Drives With Optimized Commutation

In this work, a new reduced vector model predictive control (RV-MPC) method is proposed for full silicon-carbide (SiC)-MOSFET modules-based three-level active neutral-point-clamped (3L-ANPC) inverter fed permanent magnet synchronous motor (PMSM) drives. The main purpose of this approach is to reduce the computational burden of conventional MPC for ANPC inverters while optimizing the current commutation paths. To reduce the computational burden, the proposed algorithm is implemented by two steps. In the first step, the expected <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dq</i> -axis voltages are predicted, and then, the positive and negative half cycles are determined through a hysteresis sign calculation algorithm. In the second step, only eight switching states need to be enumerated under the defined half period, which is remarkably reduced from 27 to 8. The neutral point potential balance and switching effort penalization are also considered in the proposed method. Moreover, the ANPC inverter can achieve more even loss distribution and better thermal characteristics with the optimized commutation, which is profitable for the high-power drive applications. The effectiveness of the proposed approach is evaluated by simulations and experimentally verified on a platform of 11-kW PMSM drives.

A new seven‐level ANPC inverter structure with semiconductor device reduction

AbstractAn active neutral point clamped‐type multilevel inverter (ANPC‐MLI) with self‐voltage balancing capability is being suggested for this study. A new switched capacitor cell with eight switches is used for seven‐level generation in the proposed topology. The topology proposed has decreased the power element count with the ability to self‐balancing of capacitor voltages and boosting ability. The distinguishing characteristics of the proposed topology are emphasized and compared with other recent 7L‐SCMLI topologies. Experimental testing on a prototype hardware is conducted to validate the feasibility of the proposed topology.