Ancient Vedic Mathematics Research Articles

Review of Vedic Mathematics Yavadunam Tavadunikritya Varganicha Yojayet Sutra for Cubing a Number

This paper discloses secrets and logics of the short formula of ancient Vedic Mathematics Yavadunam Tavadunikritya Varganicha Yojayet Sutra in finding the cube of a positive number. Through the formalization process, we have aimed to bridge the gap between ancient mathematical wisdom and modern theoretical foundations, showcasing the timeless utility of Vedic techniques in mathematical calculations. The sutra has been reviewed using the algebraic explanation in terms of decimal number system of the multiplication process by applying Binomial theorem for the positive integral exponent 3. Some more short-cut techniques have been discussed to explain the sutra and it has been found that they are producing the same result. There are shortcomings that have been found in applying the sutra, which has been solved using some other techniques as a special rule. Later the sutra has been discussed for negative integers also with a note. Before coming to the conclusion, we have discussed some limitations of the sutra, although that has been solved in the paper but with a different process. We have discussed the implications of the sutra for modern computational methods and educational practices, suggesting potential areas for further research.

Design and FPGA Implementation of 4×4 Vedic Multiplier using Different Architectures

The need of high speed multiplier is increasing as the need of high speed processors are increasing. A Multiplier is one of the key hardware blocks in most of the fast processing systems which is not only a high delay block but also a major source of power dissipation. A conventional processor requires substantially more hardware resources and processing time in the multiplication operation, rather than addition and subtraction. This Project describes about the design of 4-bit, 8-bit and 32-bit Vedic multiplier using ancient Vedic mathematics which helps in delay and power reduction. Simulation is done in Xilinx VIVADO software using VHDL and display on LCD. The results for Vedic multiplier using various architecture and their delay comparison are done. Key Words: FPGA (Artix-7), adders, 4x4 Array Multiplier, Vedic Mathematics

Implementation of Efficient Vedic Multiplier and Its Performance Evaluation

The ancient Vedic mathematics is well known for quicker handy multiplications but its recognition as an integrated circuit core against existing hardware multipliers is not established. As optimized hardware implementation of binary multiplier is one of the prominent unsolved problems in computer architecture, this paper proposes efficient Urdhava Tiryakbhyam Vedic multiplier architecture and compares it with the set of hierarchical multiplication algorithms which generate multiplication result in a single clock cycle. Two innovative algorithms are proposed here, one with a compact structure and another for faster execution. Also, its optimized transistor level layout is designed and implemented. To maintain homogeneity for comparison, all the algorithms are programmed on a common HDL language platform and analyzed with the same tool and technology. Final results indicate that the proposed architecture delivers 15.5% less power delay product (PDP) compared to closest competitor algorithm.

Design and Implementation of Vedic Multiplier

The ancient vedic mathematics has a set of 16 sutras and 13 subsutras. These sutras give suitable method for arithmetic calculations. The vedic formulas requires less time than the regular formulas or method of calculations [1]. Multiplier is an important block in many digital systems. This paper presents a 32-bit vedic multiplier using Urdhva Tiryagbhyam sutra of ancient vedic mathematics. The 32-bit vedic multiplier is implemented using 16-bit multipliers and adders. The 16-bit multipliers are basic blocks in the design by which the input bits are multiplied and their result are added by using the adders. The vedic multiplier can be used in many fast computing processors because of their less time delay and less number of slice LUTs. The result discusses the delay and number of slice LUTs for the implemented 32-bit multiplier. The paper also discusses the methodology of implementation.

Design of ASIC Square Calculator Using AncientVedic Mathematics

This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightforward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra ‘Urdhva Tiryagbyham’ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture.

VLSI Implementation of High Speed Energy-Efficient Truncated Multiplier

In this brief, we present the design and evaluation of a high speed and energy-efficient truncated multiplier for unsigned multiplication, such that the average absolute error due to truncation and rounding is kept minimal. The proposed algorithm eliminates a few least significant Partial Product (PP) bits and adds correction bias at appropriate PP bit positions to minimize the total error. From the literatures reviewed, it is clear that there is scope for reducing delay in multiplication using sutras of ancient vedic mathematics. This work uses a simple “crosswise and vertical sutra” of Vedic mathematics to generate PP bits. The proposed methodology groups the input into [Formula: see text]/2 bits, eliminates least subgroup multiplication ([Formula: see text]) and deletes few least significant bits in other subgroup multiplications to reduce area and power dissipation. In addition, correction biase are added at appropriate bit positions to reduce the overall absolute error due to the elimination of few PP bits and rounding of final product. Experimental evaluation of the proposed truncated design is carried out through structural level VHDL modeling and simulations using Synopsys design compiler. Performance analysis revealed Chip-Area Ratio (CAR%) to be 33.81% and Power-Delay Product (PDP) of 14.84[Formula: see text]pJ of proposed truncated design for an [Formula: see text] multiplication.

English

In this paper, we have designed an energy efficient Vedic Divider using an ancient Vedic mathematics technique known as Paravart- yaYojayet. ParavartyaYojayet is a Sanskrit name which means transpose and adjust. Vedic mathematical formulas are used to solve tedious and cum- bersome arithmetic operations. Today's world demands implementation of techniques which take lesser time and are energy efficient so we have de- signed a Vedic divider to solve long divisions in seconds. Our design con- sists of 2 inputs for dividend and divisor and 2 outputs that are remainder and quotient. Many researchers have done research work on Vedic mathe- matics to solve DSP operations using Urdhava-Triyagbhayam multiplica- tion sutra, to design asynchronous Vedic DSP processor core and lots more. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform. We have done power analysis by varying frequencies and capacitance to make our Vedic divider energy efficient. Analysis results that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capac- itance maximum power is consumed at 100pF and minimum power is con- sumed at 20pF.

DESIGN OF 64-BIT SQUARER BASED ON VEDIC MATHEMATICS

"Vedic mathematics" is the ancient methodology of mathematics which has a unique technique of calculations based on 16 "sutras" (formulae). A Vedic squarer design (ASIC) using such ancient mathematics is presented in this paper. By employing the Vedic mathematics, an (N × N) bit squarer implementation was transformed into just one small squarer (bit length ≪ N) and one adder which reduces the handling of the partial products significantly, owing to high speed operation. Propagation delay and dynamic power consumption of a squarer were minimized significantly through the reduction of partial products. The functionality of these circuits was checked and performance parameters like propagation delay and dynamic power consumption were calculated by spice spectre using 90-nm CMOS technology. The propagation delay of the proposed 64-bit squarer was ~ 16 ns and consumed ~ 6.79 mW power for a layout area of ~ 5.39 mm2. By combining Boolean logic with ancient Vedic mathematics, substantial amount of partial products were eliminated that resulted in ~ 12% speed improvement (propagation delay) and ~ 22% reduction in power compared with the mostly used Vedic multiplier (Nikhilam Navatascaramam Dasatah) architecture.

Vedic division methodology for high‐speed very large scale integration applications

Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ‘Dhvajanka (on top of the flag)’ formula was adopted from Vedic mathematics to implement such type of divider for practical very large scale integration applications. The division methodology was implemented through half of the divisor bit instead of the actual divisor, subtraction and little multiplication. Propagation delay and dynamic power consumption of divider circuitry were minimised significantly by stage reduction through Vedic division methodology. The functionality of the division algorithm was checked and performance parameters like propagation delay and dynamic power consumption were calculated through spice spectre with 90 nm complementary metal oxide semiconductor technology. The propagation delay of the resulted (32 ÷ 16) bit divider circuitry was only ∼300 ns and consumed ∼32.5 mW power for a layout area of 17.39 mm2. Combination of Boolean arithmetic along with ancient Vedic mathematics, substantial amount of iterations were reduced resulted as ∼47, ∼38, 34% reduction in delay and ∼34, ∼21, ∼18% reduction in power were investigated compared with the mostly used (e.g. digit-recurrence, Newton–Raphson, Goldschmidt) architectures.

ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like ‘Urdhva-tiryakbyham’ (UT) and ‘Nikhilam Navatascaramam Dasatah’ (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only ∼42.13ns while the power consumption of the same was ∼58.82mW for a layout area of ∼6mm2. Improvement in speed was found to be ∼33% and ∼24% while corresponding reduction of power consumption in ∼34.48% and ∼24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.