Abstract
Transistor level implementation of division methodology using ancient Vedic mathematics is reported in this Letter. The potentiality of the ‘Dhvajanka (on top of the flag)’ formula was adopted from Vedic mathematics to implement such type of divider for practical very large scale integration applications. The division methodology was implemented through half of the divisor bit instead of the actual divisor, subtraction and little multiplication. Propagation delay and dynamic power consumption of divider circuitry were minimised significantly by stage reduction through Vedic division methodology. The functionality of the division algorithm was checked and performance parameters like propagation delay and dynamic power consumption were calculated through spice spectre with 90 nm complementary metal oxide semiconductor technology. The propagation delay of the resulted (32 ÷ 16) bit divider circuitry was only ∼300 ns and consumed ∼32.5 mW power for a layout area of 17.39 mm2. Combination of Boolean arithmetic along with ancient Vedic mathematics, substantial amount of iterations were reduced resulted as ∼47, ∼38, 34% reduction in delay and ∼34, ∼21, ∼18% reduction in power were investigated compared with the mostly used (e.g. digit-recurrence, Newton–Raphson, Goldschmidt) architectures.
Highlights
Division is a fundamental operation in many scientific and engineering applications, like arithmetic computation, signal processing, artificial intelligence, computer graphics etc. [1,2,3]
In this Letter, we report on a division technique and its transistor level implementation of such circuitry based on such ancient mathematics
Divider implementation was transformed into just small division instead of actual divisor, subtraction and few multiplication, thereby reduces the iterations, owing to the substantial reduction in propagation delay
Summary
Division is a fundamental operation in many scientific and engineering applications, like arithmetic computation, signal processing, artificial intelligence, computer graphics etc. [1,2,3]. Some other attractive ideas are based on functional iterations, like N–R [10,11,12] and G–S [13,14,15] algorithm, utilises multiplication techniques along-with the series expansion, where the amount of quotient bits obtained in each of the iterations is doubled These methods converge quadratically towards the quotient when the number of iterations is increased, thereby latency becomes high. ‘Dhvajanka’ is a Sanskrit term indicating ‘on top of the flag’, is adopted from Vedas; formula is encountered to implement the division circuitry In this approach, divider implementation was transformed into just small division instead of actual divisor, subtraction and few multiplication, thereby reduces the iterations, owing to the substantial reduction in propagation delay.
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