Integer division technique for signal processing applications

Abstract

Algorithmic implementation of integer division technique based on ancient Vedic mathematics is reported in this paper. The potentiality of the 'Nikhilam Navatascaramam Dasatah (NND)' (all from 9 and last from 10)' sutra of Vedic mathematics was adopted to implement the high speed integer division. Optimized 4221 BCD encoding technique was incorporated with Vedic mathematics, to implement such divider for practical signal processing applications. Propagation delay and dynamic switching power consumption of division circuitry were minimized significantly through stage reduction techniques of such sutra (formulae). The functionality of the division circuitry was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx tool (VHDL language). The propagation delay of the resulting 6÷3 digit divisor circuitry was only ~41ns and consumed ~93mW power. Amalgam-nation of BCD arithmetic with ancient Vedic mathematics, substantial amount of iterations were eliminated owing to ~20% reduction in delay and ~12% reduction in power from its counterpart.