Analytical Drain Current Model Research Articles

Comprehensive empirical modeling of ScAlN/AlGaN/GaN ferroelectric HEMT

This correspondence introduces a concise depiction of a high electron mobility transistor (HEMT) utilizing a model that incorporates the effect of ferroelectric (FE) polarization on the empirical expression for drain current. This is accomplished by modifying the basic Shockley equation (S.E) for MESFET. The model employed in this investigation is particularly geared towards investigating the impact of the counterclockwise hysteresis effect due to the use of dielectric ScAlN on the transfer characteristics ( Id−Vgs ), which is mainly attributed to trapping and de-trapping of charge carriers at the dielectric/semiconductor interface. Modifying the S.E. made it possible to replicate the behavior observed in experimental HEMT accurately. We reported the modified drain current empirical expressions for the ScAlN/AlGaN/GaN HEMT that considers the FE polarization. The results of this study showed good agreement between the Id−Vgs characteristics obtained from the analytical and experimental data, with a root mean square deviation (RMSD) error of 0.97% and a mean squared error error of 0.94%. This analytical drain current model, presented herein for the first time, incorporates a limited number of fitting parameters. Therefore, enhancing the computational efficiency to assess the performance of FE GaN HEMTs for usage in wide-area electronics.

Low‐frequency noise model development of MoS2 field effect transistor and its analysis with respect to different traps

AbstractIn this paper, an analytical drain current model of double gate MoS2 FET Transistor for low‐frequency noise (LFN) power spectral density is developed, and compared its response with the device simulation of the proposed device structure. The developed low‐frequency noise power spectral density (PSD) model is analyzed with respect to different Trap densities, Oxide thicknesses, and high K‐dielectric materials using the TCAD Device simulation tool. Low‐frequency noise is one of the most important noises in any device since it degrades the device's performance. So, in this paper, we used a unique charge‐control model for analyzing the low‐frequency noise by considering the mobility degradation, trapping, and de‐trapping effects caused by trap densities and device lattice structure. Usually, all the previous studies on drain currents with low frequency are based on fluctuations caused by mobility and carrier variations. In our paper, we even considered the charge density fluctuation to analyze the drain current equation. Using a Charge Control Model, we can compute the parameters like gate capacitance (Cgs, Cgd), channel length modulation, and body effect. While other LFN models like the DC model, small signal model, and hybrid model will focus mainly on the static characteristics of the device such as its DC current–voltage (I‐V) relationship, terminal resistances, and input/output conductance of the devices. All the analytical model results were calibrated with the device simulation and it is observed that both are matches each other. Further, it is observed that with an increase in Trap density, the low‐frequency noise increases and low‐frequency noise is dominant at lower frequencies only (1–10 Hz), and after this frequency range the thermal noise will be the dominant noise factor.

Physics based numerical model of a nanoscale dielectric modulated step graded germanium source biotube FET sensor: modelling and simulation

This paper proposes a novel dielectric modulated step-graded germanium source biotube FET for label-free biosensing applications. Its integrated structure and unique design combine the benefits of the gate stack, germanium source, triple-gate architecture, and a step-graded biotube channel, resulting in superior performance over existing biosensors. A compact two-dimensional analytical model for channel potential, drain current, threshold voltage, and subthreshold swing has been formulated and agrees well with the simulated results. The comprehensive investigation of different device parameters, including doping and bias, offers valuable insights into optimizing the biosensor’s performance. The proposed biosensor exhibits remarkable sensitivity, achieving up to 263 mV and 1495.52 nA for certain biomolecules, which has been validated by a compact analytical model and simulations performed on the SILVACO TCAD simulator. Several parameters are employed to assess the biosensor’s effectiveness: threshold voltage, ION/IOFF ratio, subthreshold swing, off-current, peak trans-conductance, and on-current. Furthermore, the biotube channel design enables lightweight and cost-efficient biosensors, enhancing the biosensor’s practicality. This work also includes an analysis of the effect of temperature on the biosensor’s performance and characteristics, providing insights into practical applications. High sensitivity of the biosensor signifies a significant advancement in biosensing technology, suggesting a wide range of potential applications in biomedical field.

Surface potential and mobile charge based drain current modeling of double gate junctionless accumulation mode negative capacitance field effect transistor

AbstractAn analytical drain current model for double gate junctionless accumulation mode negative capacitance field effect transistor (DG‐JAM‐NC‐FET) has been developed, combining the merits of junctionless accumulation mode and negative capacitance effect such as fabrication feasibility, low power dissipation, and reduced degradation in mobility. The novelty manifested in our work is because of the incorporation of the JAM structure in ferroelectric‐based negative capacitance FET. The benefit of JAM over existing FETs is that it combines the benefits of the junctionless transistor (JLT) and conventional FETs. It avoids excessive parasitic resistance due to stronger doping in the source and drain areas, resulting in higher conductivity and better characteristics than JLT. An analytical surface potential and threshold voltage have been developed using Poisson's equation and Landau Khalatnikov's (L‐K) equation. The drain current is then determined by integrating the mobile charge using the Pao–Sah integral. Various critical parameters such as surface potential, gain, capacitance, mobile charge density, drain current, threshold voltage, subthreshold swing, transconductance, and the switching ratio have been assessed extensively by varying ferroelectric layer and channel layer thicknesses, respectively. The ON current increases with the increase in ferroelectric thickness due to the voltage amplification given by the ferroelectric layer, and the switching curve gets steeper. The analytical modeling is done in MATLAB, and its comparison is made with the TCAD numerical simulation. The obtained analytical results and the numerical simulation results correspond well.

Analytical drain current model development of twin gate TFET in subthreshold and super threshold regions

In this work, an analytical model for a twin gate Tunnel Field Effect Transistor's drain current operating in the subthreshold and superthreshold regions is proposed. Using this drain current model, the ratio of transconductance to drain current, a crucial metric for the integrated analog circuit design technique, has been retrieved. Due to the simplicity of this approach, it may be quickly implemented for any type of dual gate TFETs by adjusting a few parameters. Comparing the drain current calculated by this analytical model to the drain current simulated by the 2D-Sentaurus TCAD software demonstrates the Tunnel FET's authenticity. The proposed analytical method can be used to achieve the appropriate transconductance for operating Tunnel FETs in the gigahertz region with very low milliwatt power consumption.

An Analytical Drain Current Model of ZnO-Based Amorphous Oxide Semiconductor Thin-Film Transistors

An analytical one-piece drain current model of ZnO-based amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) is presented in this article. This model is able to solve the main obstacle in a lack of analytical and physics-based nonregional device modeling for AOSTFTs and is suitable to be implemented into circuit simulators. Based on the effective-charge-density approach, free carrier density and localized carrier density, including tail and deep states, are unified into total carrier density. Then, one-piece surface potential is derived analytically from equivalent 1-D Poisson’s equation described in an effective-charge-density approach. It is also possible that channel carrier mobility is calculated from the ratio between free carrier and effective total carrier densities. Furthermore, drain current expression is derived analytically and validated by experimental data. Good agreements of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}$ </tex-math></inline-formula> – <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}$ </tex-math></inline-formula> characteristics prove that the proposed model could serve as a useful simulation tool implemented into circuit simulators.

A comprehensive physics based surface potential and drain current model for SiGe channel dual programmable FETs

In the present work, a comprehensive analytical model for surface potential and drain current has been developed for double gate silicon-germanium channel dual programmable FETs (SiGe-DP-FET) which is capable to conduct both in n- as well as p-modes. The developed model accurately predicts the impact of mole fraction (m) variation in Si(1 − m)Ge m channel on various device characteristics such as energy band, surface potential, electric field, drain current, and transconductance. While deriving the surface potential expression, the active SiGe channel is bifurcated in three regions such that regions I and III denote the two gated regions while region II denotes the ungated region. Further, in order to compute the expression for surface potential, 2D Poisson’s equation has been solved in gated regions while linear approximation has been applied in ungated region and subsequently, the drain current expression has been obtained by integrating the band-to-band generation rate of charge carriers across the source side Schottky junctions. Moreover, in order to validate the proposed model, the analytical results are compared and verified with 2D TCAD ATLAS simulated results and it has been observed that the results obtained using proposed model match well with the simulated results.

An analytical drain current model of Germanium source vertical tunnel field effect transistor

This paper presents an analytical modeling of the drain current for a Germanium source vertical tunnel field effect transistor. Both one dimensional (1D) and two dimensional (2D) Poisson's equation are used for solving the potential distribution as the device structure possess both vertical and lateral band-to-band tunneling components. The 2D band-to-band tunneling model is employed for solving the lateral tunneling while the 1D band-to-band tunneling model is implemented on solving the vertical tunneling which consist of the source region and the overlap channel region. The length of the maximum and minimum tunneling widths are calculated by measuring the distance from the edge of the valence band to conduction band of the energy band profile. Kane's band-to-band tunneling generation rate is used to model the drain current by superimposing two current components. In addition, the impact of bandgap narrowing as well as quantum correction on the drain current are also factored into the model. The analytical models are checked and matched against the results obtained from the TCAD simulations to ensure its accuracy.

Analytical Modeling of Short-Channel TMD TFET Considering Effect of Fringing Field and 2-D Junctions Depletion Regions

An analytical drain current model is developed for a short-channel, dual-gate, monolayer 2-D transition metal dichalcogenide (TMD), lateral tunnel field-effect transistor (TFET) by considering 2-D <inline-formula> <tex-math notation="LaTeX">${p}^{+}-{n}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">${n}-{n}^{+}$ </tex-math></inline-formula> junction at source&#x2013;channel and channel&#x2013;drain junction, respectively. This work includes the effect of both front- and back-gate dielectric fringing field effects and 2-D source and drain depletion charges. A unified piecewise surface potential model is developed by capturing the fringing field effects in the channel and 2-D junction behavior at the source&#x2013;channel and channel&#x2013;drain junction by ensuring continuity of electric field at the junction regions. A tangent-line approximation method is employed for accurate numerical evaluation of the tunneling current. The proposed model is validated with simulation results obtained using nonequilibrium Green&#x2019;s function (NEGF)-based simulator for different 2-D layered materials and a close agreement is observed. The veracity of the proposed model is tested with data in reported studies for different bias conditions and excellent matching is observed. The applicability of the model is demonstrated for any 2-D layered material-based TFET from ultrashort channel to a channel length of 50 nm. The proposed model will be extremely useful for further exploration of 2-D TMD material TFET-based very large-scale integration (VLSI) circuits.

Analytical model of subthreshold drain current for nanoscale negative capacitance junctionless FinFET

In this article, an analytical Subthreshold Drain Current model has been developed for Negative Capacitance Junctionless FinFET (NC-JL FinFET). To obtain the subthreshold current model for NC-JL FinFET the drift-diffusion equation is solved by including negative capacitance effect through LK equation and further utilized to attain the expression of subthreshold slope (SS). The influence of the fringing field due to source/drain spacer on the subthreshold current has been included in the model. The model predictions turn out to be in fair agreement with numerical simulation results. The performance of NC-JL FinFET is also examined for different technology nodes. Also, the influence of physical parameters like ferroelectric thickness, gate dielectric constant, fin thickness, spacer length etc. has also been analyzed. Further, the SS is also examined for variations in several device design parameters. It has been revealed that the NC-JL FinFET improves subthreshold current and SS by almost 80% and 16.7%, respectively as compared to JL FinFET.

Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

Analytical Drain-Current Model and Surface-Potential Calculation for Junctionless Cylindrical Surrounding-Gate MOSFETs

In this paper, we propose an analytical drain-current model for long-channel junctionless (JL) cylindrical surrounding-gate MOSFET (SRG MOSFET). It is based on surface-potential solutions obtained from Poisson’s equation using some approximations and separate conditions. Furthermore, analytical compact expressions of the drain-current have been derived for deep depletion, partial depletion, and accumulation mode. The confrontation of the model with TCAD simulation results, performed with Silvaco Software, proves the validity and the accuracy of the developed model

Analytical Modeling of Line-Tunneling TFETs Based on Low-Bandgap Semiconductors

The combination of two techniques: low-bandgap semiconductor and line-tunneling structure is an effective way to achieve the highest on-current in TFETs. In this paper, design of low-bandgap line-tunneling TEFT and its analytical modeling of drain current equation is proposed. The previously suggested drain current equation for the low-bandgap line-tunneling TEFT has been explained in a relatively complex form based on the minimum tunnel path that is an effective factor in determining band-to-band tunneling (BTBT). It has been simplified in this paper and reformulated based on gate-to-source voltage. Important design factors such as source doping concentration, material and thickness of the gate-insulator were examined by simulation and numerical calculations based on the minimum tunnel path for two low-bandgap In0.88Ga0.12As and relatively high-bandgap GaSb semiconductors. The comparison of the results obtained from simulations with the proposed analytical drain current model show a good agreement. Drain doping concentration, is an effective factor on the off-state current of low-bandgap TFET. This factor was examined in order to reduce the off-current.

Drain current characterization of dielectric modulated split gate TFET for bio-sensing application

This paper presents an analytical surface potential and drain current model of split gate (SG) Tunnel Field Effect Transistor (TFET) for label free detection of biomolecules e.g. protein, biotine, DNA, etc., utilizing the concept of underlap and dielectric modulation approach. A portion of the device channel is left open in between the splitted gates with a thin layer of silicon dioxide as adhesive layer. This open cavity acts as the binding site for the biomolecules to be detected which alters the effective capacitance of the region and hence modulates the device characteristic trend. The device electrostatics are developed by solving two dimensional Poisson’s equation and Young’s parabolic approximation and consequent drain current is then formulated applying Kane’s model. To assess the sensing ability of the device, both neutral and charged biomolecules with different dielectric values are immobilized within the cavity and the impact of variation in dielectric constant, charge density and height of biomolecules on device characteristics is analyzed. In addition to this, drain current sensitivity of the device is also investigated by varying the permittivity, charge density (both positive and negative) and height of the bio-species. All the analytical results are evaluated with corresponding Sentaurus TCAD simulated data to corroborate the accuracy of the derived model.

Modeling of Both Arrhenius and Non-Arrhenius Temperature-Dependent Drain Current for Organic Thin-Film Transistors

To describe both Arrhenius and non-Arrhenius temperature-dependent drain currents for the organic thin-film transistors, the effective trapped carrier concentration expression is presented. Based on the expression, following the Shur and Hack's trap limited carrier conduction theory, the analytical drain current model is developed. The temperature-dependent trap states' density is presented to explain the origin of the effective trapped carrier concentration expression.

Analytical drain current model of strained junctionless nanowire tunnel field‐effect transistor fabricated on virtual substrate

This study proposes an analytical drain model of the strained junctionless nanowire tunnel field-effect transistor fabricated on the S i 1 − x G e x virtual substrate. The surface potential is derived by solving Poisson's equation in the channel region. Effects of the strained silicon on the potential profile can be expressed as a function of the Ge concentration in the S i 1 − x G e x virtual substrate. An analytical expression for the drain current is derived by using the tangent line approximation method. The strain induced in the device could reduce the effective tunnelling barrier significantly, resulting in a larger band-to-band tunnelling generation rate and, therefore, higher drive current compared with the unstrained device. Impacts of device parameters such as the channel diameter, gate oxide thickness and gate dielectric constant on the device performance are investigated. Results of the proposed model are verified by comparing with the device simulator.

Analytical Drain Current and Capacitance Model for Amorphous InGaZnO TFTs Considering Temperature Characteristics

Analytical drain current and capacitance model is developed for the amorphous InGaZnO (a-IGZO) thin-film transistor (TFT). The numerical Pao-Sah model is presented to describe the temperature characteristics considering the deep and tail trap states in the energy gap of the a-IGZO thin film. The numerical model is successful for the TFT in both the subthreshold regime and the above-threshold regime. In the subthreshold regime, considering that the trapped electron concentration in the deep trap states dominates the Poisson's equation, the surface-potential-based analytical model is presented. In the above-threshold regime, the threshold-voltage-based analytical model is presented. Applying the smooth function to connect the subthreshold model and the above-threshold model, the analytical compact model is obtained. The compact model is verified by the numerical Pao-Sah model and the available experimental data from 253 to 393 K. Furthermore, the temperature characteristics of the field-effect mobility are discussed.

Experimental Observation and Modeling of the Impact of Traps on Static and Analog/HF Performance of Graphene Transistors

The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-reduced experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the trap effects on the channel potential within the device. High-frequency (HF) figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and HF applications.

Analytical Drain Current Model for Source Pocket Engineered Stacked Oxide SiO2/HfO2 Cylindrical Gate TFETs

In this work, an analytical model for current-voltage characteristics of a source pocket engineered stacked gate oxide SiO2/HfO2 cylindrical gate all-around tunnel field effect transistor (CG TFET) has been developed. Source pocket length has been optimized in order to get higher ON-current and minimum subthreshold swing (SS). To model the surface potential in different regions, 2D Poisson’s equation has been elucidated with adopting parabolic approximation formulation in cylindrical coordinates with appropriate boundary conditions. Tunneling current is calculated analytically by integrating the tunneling generation rate. The effect of source/channel and channel/drain depletion regions has been taken into consideration in proposed model for better accuracy. The modeled results have been verified with the numerical data from ATLAS™ 3D TCAD simulator.

Analytical Drain Current Model for a-SiGe:H Thin Film Transistors Considering Density of States

Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including deposition at low temperatures and low pressures, and higher carrier mobilities. Due to these advantages, the a-SiGe:H films can be used in the fabrication of TFTs. In this work, we present an analytical drain current model for a-SiGe:H TFTs considering density of states and free charges, which describes the current behavior at sub-and above- threshold region. In addition, 2D numerical simulations of a-SiGe:H TFTs are developed. The results of the analytical drain current model agree well with those of the 2D numerical simulations. For all characteristics of the drain current curves, the average absolute error of the analytical model is close to 5.3%. This analytical drain current model can be useful to estimate the performance of a-SiGe:H TFTs for applications in large area electronics.