Analysis Of Substrate Coupling Research Articles

Substrate cross‐talk analysis flow for submicron CMOS system‐on‐chip

A substrate coupling analysis flow is presented. The proposed method is fully compatible with the industry analogue/radio-frequency design methodology, seamlessly integrates into the design environment, provides accurate estimation of the coupling effects and can model adequately all the mask design level isolation performance trends. Its accuracy is confirmed by correlating simulation results against on-wafer silicon measurements in a 28 nm CMOS set of ring oscillators with a carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV, whereas the error sigma is 765 μV.

Behavioral Modeling and Simulation Techniques for Substrate Coupling Analysis in Phase Locked Loop

Behavioral Modeling and Simulation Techniques for Substrate Coupling Analysis in Phase Locked Loop

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to evaluation of device-level isolation structures against substrate coupling is now developed into chip-level substrate noise analysis. A time-series divided parasitic capacitance (TSDPC) model is equivalent to a transition controllable noise source (TCNS) circuit that captures noise generation in a CMOS digital circuit. A reference structure incorporating TCNS circuits and an array of on-chip high precision substrate noise monitors provides a basis for the verification of chip-level analysis of substrate coupling in a given technology. Test chips fabricated in two different wafer processings of 0.30-μm and 0.18-μm CMOS technologies demonstrate the universal availability of the proposed analysis techniques. Substrate noise simulation achieves no more than 3 dB discrepancy in peak amplitude compared to measurements with 100-ps/100-μV resolution, enabling precise evaluation of the impacts of the distant placements of sensitive devices from sources of noise as well as application of guard ring/band structures.

Synthesized Compact Models and Experimental Verifications for Substrate Noise Coupling in Mixed-Signal ICs

A synthesized compact modeling (SCM) approach for substrate coupling analysis is presented. The SCM is formulated using a scalable <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$Z$</tex> matrix approach for heavily doped substrates with a lightly doped epitaxial layer and using a nodal lumped resistance approach for lightly doped substrates. The SCM models require a set of process-dependent fitting coefficients and incorporate geometrical parameters of the substrate ports in a compact form that includes size, perimeter, and separation defined using the geometric mean distance to accommodate both far-field and near-field effects. The SCM approach is verified based on measurement data from two test chips, one in a custom lightly doped process and the other one using a 0.18- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$muhbox m$</tex> BiCMOS lightly doped foundry process. The model accuracy is shown to be within 15% compared to measured data extracted from the test patterns. The SCM is exploited with application examples to show substrate model generation efficiency and accuracy at different levels of complexity, including a full chip substrate noise distribution analysis for a 2 mm by 2 mm chip with 319 substrate contacts.

Improved approach to analysis of substrate coupling based on multilayered Green's function

This article presents an improvement on the evaluation of a Green's function method proposed by Niknejad 7 for modeling and analysis of substrate coupling in integrated circuits. By careful combination, the 64-term summation can be approximated by a four-term one. Therefore, the computational cost can be reduced. The approximation is effective for contact pairs small compared to their separations. This article also studies quantitatively how small the contact should be in order for approximation to be applicable. Numerical results show that a speed-up of over 6× could be achieved by adopting the new approach. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.

On the numerical stability of Green's function for substrate coupling in integrated circuits

This paper presents an analysis of the numerical stability for the formulation of the Green's function method of Niknejad et al. (1998) for modeling and analysis of substrate coupling in integrated circuits. It is shown that the formulation has numerical overflow problems. A new stable formulation is presented.

Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time /spl Sigma//spl Delta/ ADC

This paper describes a highly digitized direct conversion receiver of a single-chip quadruple-band RF transceiver that meets GSM/GPRS and EDGE requirements. The chip uses an advanced 0.25-/spl mu/m BiCMOS technology. The I and Q on-chip fifth-order single-bit continuous-time sigma-delta (/spl Sigma//spl Delta/) ADC has 84-dB dynamic range over a total bandwidth of /spl plusmn/135 kHz for an active area of 0.4 mm/sup 2/. Hence, most of the channel filtering is realized in a CMOS IC where digital processing is achieved at a lower cost. The systematic analysis of dc offset at each stage of the design enables to perform the dc offset cancellation loop in the digital domain as well. The receiver operates at 2.7 V with a current consumption of 75 mA. A first-order substrate coupling analysis enables to optimize the floor plan strategy. As a result, the receiver has an area of 1.8 mm/sup 2/.

Analysis of substrate coupling by means of a stochastic method

The paper addresses the problem of modeling the coupling effects that take place in resistive IC substrates for accurate and efficient circuit analysis. The proposed method is based on a suited extension of the floating random walk algorithm that can deal with mixed Dirichlet and Neumann boundary conditions.

Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits

The Green function over a multilayer substrate is derived by solving Poisson's equation analytically in the coordinate and numerically in the z and y coordinates. The x and y functional dependence is transformed into a discrete cosine transform (DCT) representation for rapid evaluation. The Green function is further transformed into a numerically stable form appropriate for finite-precision machine evaluation. This Green function is used to solve for the impedance matrix for an arbitrary three-dimensional arrangement of conductors placed anywhere in the substrate. Using this technique, the substrate coupling and loss in IC circuits can be analyzed. A spiral inductor is presented as an example. Experimental measurement results verify the accuracy of the technique.

Modeling and analysis of substrate coupling in integrated circuits

This paper describes a fast and accurate simulator for characterizing the effects of substrate coupling on integrated-circuit performance. The technique uses the electrostatic Green function of the substrate medium and the fast Fourier transform algorithm. It is demonstrated that this technique is suitable for optimization of layout for minimization of substrate coupling. Analysis of substrate coupling in different types of substrates and the utility of guard rings in different types of substrates is also discussed. Experimental verification of the models is presented.

Analysis and modelling of parasitic substrate coupling in CMOS circuits

Analysis of the substrate coupling in integrated circuits is done taking into account technology and layout parameters for different types and location of transistors using a device-level simulator. The noise coupling tendencies of IC scaling are analysed, following interest in advanced technologies. The potential for permanent errors is shown in the case of a RAM cell. A circuit-level model for the coupling mechanism is proposed. The implementation of an IC for experimentation, and the measurements obtained, are discussed.