Analysis Of Large Circuits Research Articles

Analysis of Error Masking and Restoring Properties of Sequential Circuits

Scaling of CMOS technology into nanometric feature sizes has raised concerns for the reliable operation of logic circuits, such as in the presence of soft errors. This paper deals with the analysis of the operation of sequential circuits. As the feedback signals in a sequential circuit can be logically masked by specific combinations of primary inputs, the cumulative effects of soft errors can be eliminated. This phenomenon, referred to as error masking, is related to the presence of so-called restoring inputs and/or the consecutive presence of specific inputs in multiple clock cycles (equivalent to a synchronizing sequence in switching theory). In this paper, error masking is extensively analyzed using the operations of state transition matrices (STMs) and binary decision diagrams (BDDs) of a finite state machine (FSM) model. The characteristics of state transitions with respect to correlations between the restoring inputs and time sequence are mathematically established using STMs; although the applicability of the STM analysis is restricted due to its complexity, the BDD approach is more efficient and scalable for use in the analysis of large circuits. These results are supported by simulations of benchmark circuits and may provide a basis for further devising efficient and robust implementations when designing FSMs.

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks

We propose a logic gate leakage model based on transistor stacks, which includes local transistor level process variation parameters along with global process variation parameters and supply and temperature. The stack models include both subthreshold as well as gate leakage and consider the input vector state. We examine cells from an industrial standard cell library and find that most cells can be modeled with simple stacks, which have a linear chain of transistors. However some gates like XOR, Majority or Muxes need complex stacks and we show how these can be modeled. Our experiments show that only 18 different stack models are needed to predict the leakage of all gates in this industrial library. Re-use of the same models for pass transistor logic circuits and multi-finger transistors is also demonstrated. We explicitly include voltage and temperature into the models to support joint estimation of power supply IR drops and leakage currents, as well as enable analysis for dynamic voltage scaling applications. We use artificial neural networks to create unified models which include global and local process variations, supply voltage in the range of V DD /2- V DD and temperature in the range 0-100 °C. These models are very useful for performing statistical leakage analysis of large circuits. Results from the ISCAS'85 benchmark circuits show that neural network based stack models can predict the PDF of leakage current of large circuits across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 7% when compared to SPICE. Further gate level validation has been done for both an industrial 130 nm and 45 nm PTM model files.

Reachability analysis of large circuits using disjunctive partitioning and partial iterative squaring

Abstract Reachability analysis is an orthogonal, state-of-the-art technique for the verification and validation of finite state machines (FSMs). Due to the state space explosion problem, it is currently limited to medium-small circuits, and extending its applicability is still a key issue. Among the factors that limit reachability analysis, let us list: the peak binary decision diagrams (BDD) size during image computation, the BDD size to represent state sets, and very high sequential depth. Following the promising trend of partitioning, we decompose a finite state machine into “functioning-modes”. We operate on a disjunctive partitioned transition relation. Decomposition is obtained heuristically based on complexity, i.e., BDD size, or functionality, i.e., dividing memory elements into “active” and “idle” ones. We use an improved iterative squaring algorithm to traverse high-depth subcomponents. The resulting methodology attacks the above problems, lowering intermediate peak BDD size, and dealing with high-depth subcomponents. Experiments on a few industrial circuits and on some large benchmarks show the feasibility of the approach.

The transition matrix for linear circuits

The state transition matrix /spl Phi/(t)=e/sup At/ plays an important role in the state variable analysis of linear time-invariant circuits. In this paper, we give a method to compute the equivalent matrix for a set of differential-algebraic equations. Specifically, the algorithm is illustrated for the modified nodal analysis (MNA). A benefit of using MNA formulation is that equation formulation is straightforward and computer-aided analysis of large circuits is simplified. Another benefit is that inconsistent initial conditions in the analysis of switched circuits is automatically and correctly handled by the algorithm. Comparison with the state variable approach is made, and application to the simulation of linear circuits is given. The method is based on circuit theory concepts accessible to all electrical engineers. In addition to the transition matrix, a numerical method to compute the zero state response of linear circuits for a restricted set of inputs is given. The transition matrix along with the zero state response results in a special algorithm that is used to compute the time response of lumped linear time-invariant circuits at equally spaced intervals of time. This method is compared with the solution of linear circuits by SPICE-like simulators.

Hierarchical techniques for symbolic analysis of electronic circuits

A hierarchical symbolic analyser (SAGA2) is presented for the analysis of electronic circuits. SAGA2 analyses lumped, linear, or linearised (small-signal) circuits in the S- and Z-domain. For the analysis of large circuits, a hierarchical two-port (multiport) method is proposed that is two to three orders faster than that without using the hierarchical method. A bandpass filter or a 12-stage RC ladder circuit can be analysed in symbolic form within 1 CPU second. Also, the memory used is dramatically reduced.

Diakoptic and large change sensitivity analysis

An approach to the analysis of large circuits based on the use of the large change sensitivity technique applied to decomposed networks is presented. As a result of this approach a simple, compact notation for the solution vector is derived. The method is applicable to nonlinear analogue networks with hierarchical decomposition simulated by inserted ideal switches. A simple illustrative example is given.

An analytic model for the design and optimization of ion-implanted I/sup 2/L devices

A set of simple analytic equations have been derived that model the transient characteristics of an I/SUP 2/L gate fabricated with ion implantation. The model equations are cast in terms of easily measured or calculated device parameters and are applicable at all current levels. Separate models for regions dominated by depletion and diffusion capacitance, respectively, are unnecessary. The model has been checked with a large circuit analysis program (SPICE). The gate delay model is combined with calculations from process and intrinsic device simulators, and measurements from specially designed test structures to explain the physical mechanisms that control the gate switching time. A method of scaling I/SUP 2/L structures is described in which process and geometry variations are possible. This scaling procedure is combined with the analytic gate model to predict the gate performance that might be expected from processing techniques such as X-ray and electron beam lithography.