An analytic model for the design and optimization of ion-implanted I/sup 2/L devices

Abstract

A set of simple analytic equations have been derived that model the transient characteristics of an I/SUP 2/L gate fabricated with ion implantation. The model equations are cast in terms of easily measured or calculated device parameters and are applicable at all current levels. Separate models for regions dominated by depletion and diffusion capacitance, respectively, are unnecessary. The model has been checked with a large circuit analysis program (SPICE). The gate delay model is combined with calculations from process and intrinsic device simulators, and measurements from specially designed test structures to explain the physical mechanisms that control the gate switching time. A method of scaling I/SUP 2/L structures is described in which process and geometry variations are possible. This scaling procedure is combined with the analytic gate model to predict the gate performance that might be expected from processing techniques such as X-ray and electron beam lithography.