Analysis Of Analog Circuits Research Articles

Extended “A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits”

The objective here is to expand and complete the development of a recently published article “A Comprehensive and Unified Procedure for Symbolic Analysis of Linear Analog Circuits”. This expansion is in three areas. 1) Here, the element values are not limited to admittances. Both admittances and impedances are used. 2) The linear active devises are not limited to VCCSs, but the other controlled sources, VCVSs, CCVSs, and CCCSs are also valid components. 3) The I/O ports are expanded and now all four types of I/O ports, namely, current source inputs and voltage outputs, current source inputs and current outputs, voltage source inputs and voltage outputs, and voltage source inputs and current outputs are included in the process. The method consists of two main processes. In the first process a circuit with active devices and I/O ports is converted into a nullor circuit. The nullor circuit is then partitioned into two parts, a passive circuit and an all-nullor circuit. It is shown that the magnitude of the determinant comes from the passive part and the sign (0, 1, or -1) results from the all-nullor circuit.

Analog and mixed circuit analysis of nanosheet FET at elevated temperatures

In this paper, for the first time, the performance of 3D Nanosheet FETs (NSFETs) is reported in the inversion (INV), accumulation (ACC), and junctionless (JL) modes at elevated temperatures. It is observed that, as the temperature increases from 25 °C to 200 °C, a decrement of 68% in mobility is observed for INV mode. In contrast, an increment of around 29% in mobility is observed for ACC and JL modes owing to the less scattering effects. Various crucial DC and analog/RF figures of merit (FOMs), such as SS, DIBL, gm, f T, etc, are assessed for different temperatures in all three modes. Further, the impact of temperature on circuit performance is demonstrated. From the circuit analyses, at 25 °C, an increment of around 12% in propagation delay is noticed for the JL and ACC mode inverter compared to the INV mode inverter due to higher I ON for INV mode. However, at 200 °C, JL inverter outperforms INV and ACC modes because of an increment in mobility. Moreover, for ring oscillator (RO), an oscillation frequency of 43.39 GHz, 38.9 GHz and 38.8 GHz for INV, ACC and JL mode ROs at 25 °C, whereas oscillation frequencies of 27.08 GHz, 39.2 GHz and 42.88 GHz are noticed for INV, ACC and JL mode ROs at 200 °C respectively. Though JL NSFET offers less intrinsic capacitances, at 25 °C, the frequency of oscillations (f osc) is high for INV mode because of higher I ON. Whereas, at 200 °C, the JL mode outperforms due to the absence of mobility degradation with temperature. These results will give an understanding of this future generation device at both device and circuit levels.

Mathematical Circuit Root Simplification Using an Ensemble Heuristic–Metaheuristic Algorithm

Symbolic pole/zero analysis is a crucial step in designing an analog operational amplifier. Generally, a simplified symbolic analysis of analog circuits suffers from NP-hardness, i.e., an exponential growth of the number of symbolic terms of the transfer function with the circuit size. This study presents a mathematical model combined with a heuristic–metaheuristic solution method for symbolic pole/zero simplification in operational transconductance amplifiers. First, the circuit is symbolically solved and an improved root splitting method is applied to extract symbolic poles/zeroes from the exact expanded transfer function. Then, a hybrid algorithm based on heuristic information and a metaheuristic technique using simulated annealing is used for the simplification of the derived symbolic roots. The developed method is tested on three operational transconductance amplifiers. The obtained results show the effectiveness of the proposed method in achieving accurate simplified symbolic pole/zero expressions with the least complexity.

A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits

The objective here is to develop a uniform and comprehensive procedure for symbolic analysis of linear circuits using the Sum of the Tree Products (STP) of the circuit. We achieve this goal in two stages. In the first stage a circuit with active devices, such as VCCSs and I/O ports, is changed to a nullor circuit, i.e., to a circuit with only passive components and nullors. The nullor circuit is also partitioned into two parts, a passive circuit and an all-nullor circuit. It is shown that the magnitude of the STP, i.e., the determinant of the NAM, of the circuit is equal to the STP of the passive portion of the circuit, and the sign (0, 1, or −1) of the STP comes from its all-nullor part. Another significant development in this presentation is the replacement of the regular STP methodology with a rather new Admittance Method ( <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">AM</i> ). It is shown that by doing this the entire two-graph theory for active circuits as well as the use of 2-tree procedures for I/O ports analysis are eliminated. It is these new developments that substantially simplifies the circuit analysis and makes it quite efficient for symbolic representation of transfer functions.

Normalized Dynamic Characterization and Application of Multiple Heat Storage Materials Based on Standard Thermal Resistance

Based on the standard thermal resistance and the heat current method, the transient heat transfer thermal resistance between the heat storage material and the heat transfer fluid is deduced. Through analog circuit analysis method, the transient heat current model and dynamic response time constant of heat storage-heat exchange processes are obtained. Based on this model, the node temperature is introduced for refining the heat transfer thermal resistance, and the transient heat current model of the third-order circuit coupled with the heat storage and heat transfer processes is obtained. Through numerical simulation verification and application comparison analysis, it is found that the normalized dynamic model based on multiple time constants is feasible to characterize the dynamic characteristics of heat storage materials, and can directly compare and analyze different heat exchange and heat storage materials. The case study found that when exchanging heat with solid heat storage materials, the dynamic heat exchange capacity of liquid metal is better than that of molten salt, while the heat exchange between air and ceramic materials reaches a steady state faster than that of water vapor and CO₂.

Simulation based dynamic laser stimulation for failure analysis of analog and mixed-signal circuits

With the increasing complexity of circuits, it is difficult to carry out fault isolation in a short time. This is particularly true for mixed-signal circuits when using only standard fault isolation techniques (e.g. EMMI or TLS). It is often complicated to tell whether a spot is a consequence of a failure or points out the location of the defect itself. In this scenario, circuit simulators are a solution to resolve this ambiguity and ease this task. This work proposes a simulation method for circuits inspected using thermal laser stimulation techniques. Furthermore, simulations for the dynamic laser stimulation technique are proposed with encouraging results for failure analysis.

An analog circuit analysis method by node elimination

An analog circuit analysis method by node elimination

Analysis of power supply noise in AMS circuits including the effects of interconnects using estimation by inspection method

This paper presents the analysis of on-chip analog and mixed signal (AMS) circuits in the presence of supply noise, on- and off-chip interconnect effects. The estimation-by-inspection method is extended to analyze the performance metrics of the AMS circuits. For the purpose of validation, two different examples are considered, designed in UMC 130 nm and Lfoundry 180 nm technology-nodes. The mean percentage error (MPE) between electronic design automation (EDA) simulations and analytical results using the proposed method is less than 10% for various performance metrics of an AMS system. A speed-up factor of 9 has been achieved using the proposed method as compared to the EDA simulations.

Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision

Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template-based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template-based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U-net while requiring 13× shorter training/validation time. To further improve the pixel-wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning-based TCMD-PL model. The proposed TCMD-PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling.

Systematic circuit design and analysis using generalised g m / I D functions of MOS devices

The conventional approach to implementing analogue integrated circuits in nano-scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon area. Analytical-based design procedures can assist the designer in confronting the sizing challenge of the metal oxide semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For this purpose, the behaviour of short-channel MOS devices is characterised in various process and temperature corners using an updated matrix representation of different device scales, bias conditions, and small-signal parameters. The details to effectively extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design and analysis of the circuits. The design examples include a 0.39 V – 28 µA reference circuit, and a 7.50 µA/V operational-transconductance amplifier with 1.0 V voltage supply in 90-nm CMOS.

A Novel Method for Detecting Parametric Faults in Analog Circuits using Fuzzy Logic

The demand for testability analysis of analog circuits has been increased in recent years. The fault detection and fault classification method is important in detecting the parametric faults of the circuit. In this paper, Simulation Before Test (SBT) is considered as a basic mechanism for detecting the parametric faults.. The circuit Under Test (CUT) used is Sallen-Key bandpass filter. Transfer function of the CUT is used for fault detection by locating the poles and Zeros of the transfer function. Fuzzy logic is used for fault classification.

Modeling Analysis and Diagnosis of Analog Circuits in z-Domain

The paper is dedicated to the linear time-invariant analog electronic circuits. It deals with the problem of modeling of the circuits in the [Formula: see text]-domain. The model put forward in this paper enables solving different issues with the analysis of linear dynamic circuits. The model’s usefulness to fault diagnosis is emphasized in the paper, especially its application to multiple soft fault diagnosis of linear circuits. To make such diagnosis possible, the node equations with unknown node voltages and the diagnosed parameters are used. The set of actual values of the verified parameters is achieved by solving an appropriate system of algebraic nonlinear equations associated to the node equations. It can be determined using the Newton algorithm with adaptive choice of damping parameter. The diagnosis method is adjusted to real conditions by considering the deviations of the healthy parameters inside their tolerance scopes. Two real-life electronic circuits are considered to illustrate the method.

Time-efficient fault detection and diagnosis system for analog circuits

Time-efficient fault analysis and diagnosis of analog circuits are the most important prerequisites to achieve online health monitoring of electronic equipments, which are involving continuing challenges of ultra-large-scale integration, component tolerance, limited test points but multiple faults. This work reports an FPGA (field programmable gate array)-based analog fault diagnostic system by applying two-dimensional information fusion, two-port network analysis and interval math theory. The proposed system has three advantages over traditional ones. First, it possesses high processing speed and smart circuit size as the embedded algorithms execute parallel on FPGA. Second, the hardware structure has a good compatibility with other diagnostic algorithms. Third, the equipped Ethernet interface enhances its flexibility for remote monitoring and controlling. The experimental results obtained from two realistic example circuits indicate that the proposed methodology had yielded competitive performance in both diagnosis accuracy and time-effectiveness, with about 96% accuracy while within 60 ms computational time.

Simulation-Based Diagnostic Model for Automatic Testability Analysis of Analog Circuits

A novel data-driven simulation-based diagnostic model is proposed to realize automatic and practical testability analysis (TA) of analog circuits. With this model and the corresponding methods, sufficient faults can be handily injected into the circuit under test and then be simulated to construct the sample data. Using these data, a kernel density estimation on ${K}$ -nearest neighbors classification algorithm and its leave-one-out cross-validation method are studied to evaluate the testability metrics. To handle the possible high false alarm caused by the faults that have similar samples with the fault-free case, two strategies are carried out by ignoring the faults in the ambiguity groups or/and using the posterior weights to determine the final classification results. Furthermore, a sample compression approach is proposed to reduce the computational cost. Experimental results show that more accurate and reasonable TA and verification can be achieved by comparing with the traditional testability models and the state-of-the-art classification methods. And the diagnostic application against a real circuit based on the simulation data can also reach a satisfactory level.

Microelectronic Circuits: Analysis and Design, Third Edition [Book News

The third edition of Microelectronic Circuits: Analysis and Design is a completely reorganized book using a top-down approach followed by the usual bottom-up approach. The objectives are twofold: 1) to study semiconductor devices, and 2) to develop students' skills in the analysis and design of analog and digital electronic circuits.

Simplified symbolic transfer function factorization using combined artificial bee colony and simulated annealing

Symbolic circuit analysis inherits the exponential growth of transfer function complexity with the circuit size. Therefore, symbolic simplification is an NP-hard problem. Although many simplification techniques have been presented, the simplified transfer functions are not written in a factorized form, and consequently, it is difficult to assess the contribution of poles and zeros on the circuit behavior. In this paper, a swarm intelligence based methodology is presented for the simplified factorized symbolic analysis of analog circuits. In this method, an extension of the root splitting technique is utilized to rewrite the expanded transfer function of the circuit into a factorized form comprising DC-gain, poles, and zeros. Then, the derived factorized transfer function is simplified using a hybrid Global and Local search algorithm based on Artificial Bee Colony and Simulated Annealing (named GLABCSA). The objective function is defined to minimize the complexity of the symbolic factorized transfer function while minimizing the DC-gain error and pole/zero displacements. The presented approach has been successfully developed in MATLAB. The program can derive the simplified factorized symbolic transfer function automatically from the input text netlist of the circuit. Symbolic and numerical results over two analog amplifiers are given to illustrate the efficiency of the presented methodology.

A Scheme for Analysis and Design of Analogue Circuits

A Scheme for Analysis and Design of Analogue Circuits

A Scheme for Analysis and Design of Analogue Circuits

Network theorems or circuit theorems are special aids, which can reduce the amount of effort involved in circuit analysis to a considerable degree. For linear networks, there exists interdependence between various network theorems. Thus, by careful analysis, one theorem can verify in terms of another theorem and it is advantageous for pedagogical reasons. A scheme for analogue circuit analysis is presented in this paper. Here piece-by-piece or part-by-part analyzing strategy is employed which can reduce the complexity associated with analyzing or biasing design of large analogue circuits. Fixatornorator pair plays the key role in this methodology. Hybrid equivalent circuit, an alternative for Thevenin’s or Norton’s equivalent model is realized with fixator-norator pair, and is seen to be more dynamic and flexible since it contains both voltage source and current source. Thevenin’s theorem, compensation theorem and maximum power transfer theorem are analyzed in terms of fixator norator pairs, and the study indicates the importance and capabilities of fixator-norator pair and hence hybrid equivalent circuit in analogue circuit design and analysis. Keywords: Compensation Theorem, Fixator-norator Pair, Hybrid Equivalent Circuit, Maximum Power Transfer Theorem, Thevenin’s Theorem

Applications of Fixator-norator Pair in Companion Model Based Designs

This paper presents a novel approach to the accurate time domain analysis and design of analog circuits containing storage elements by making use of ‘companion models’. The emphasis is given to the design using fixator-norator pair, which is now ingenious in analog circuit design. The Backward Euler method can render a storage element to an equivalent circuit, containing only linear components viz. current source or voltage source and resistance. This distinctive feature allows us to generate equivalent companion models of the storage elements for every time step, whereby persuading the application of fixator-norator pairs in such circuits containing reactive components. This paper briefly explains the construction of equivalent circuits at desired time steps and provides a detailed explanation on the design of the gain of an op-amp differentiator for a given input by exploiting the fixator-norator method. The proposed method reveals to be much reliable and accurate in the design of circuits containing reactive elements.

Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors

Efficient performance modeling is an extremely important task for yield analysis and design optimization of analog circuits. In this paper, a novel regression modeling method based on hierarchical shrinkage priors is proposed to construct hybrid performance models with both high accuracy and low computational cost. In particular, the user-defined model templates derived from design equations and the general-purpose orthogonal polynomials are combined together to set up a hybrid dictionary. Next, in order to avoid over-shrinking large model coefficients, a novel regression method based on hierarchical shrinkage priors and variational Bayesian inference is adopted for model fitting. A rail-to-rail operational amplifier example demonstrates that the proposed method achieves up to 40% error reduction over other state-of-the-art approaches without increasing the modeling cost.