Analog-to-digital Research Articles

Twice‐input variable‐resolution single‐side switching scheme without reset energy for SAR ADC

AbstractA twice‐input variable‐resolution single‐side switching scheme without reset energy is proposed for successive approximation register (SAR) analogue‐to‐digital converters (ADCs). The proposed switching scheme is based on semi‐resting DAC technology to design a four‐array architecture capable of handling twice the swing of the signal input while reducing the capacitor array size. The technique of top‐plate sampling and monotonic shift is utilized so that no switching energy is generated for the first three comparisons. The proposed scheme utilizes full‐capacitor split, bridged switch, and C‐2C dummy capacitor technology, which reduces average switching energy consumption by 99.8% compared to conventional schemes and enables ADC variable resolution function, making the SAR ADC more suitable for IoT applications.

Unlimited sampling beyond modulo

Analog-to-digital converters (ADCs) act as a bridge between the analog and digital domains. Two important attributes of any ADC are sampling rate and its dynamic range. For bandlimited signals, the sampling should be above the Nyquist rate. It is also desired that the signals' dynamic range should be within that of the ADC's; otherwise, the signal will be clipped. Nonlinear operators such as modulo or companding can be used prior to sampling to avoid clipping. To recover the true signal from the samples of the nonlinear operator, either high sampling rates are required, or strict constraints on the nonlinear operations are imposed, both of which are not desirable in practice. In this paper, we propose a generalized flexible nonlinear operator which is sampling efficient. Moreover, by carefully choosing its parameters, clipping, modulo, and companding can be seen as special cases of it. We show that bandlimited signals are uniquely identified from the nonlinear samples of the proposed operator when sampled above the Nyquist rate. Furthermore, we propose a robust algorithm to recover the true signal from the nonlinear samples. Compared to the existing methods, our approach has a lower mean-squared error for a given sampling rate, noise level, and dynamic range. Our results lead to less constrained hardware design to address the dynamic range issues while operating at the lowest rate possible.

Measurement of thermophysical parameters of artificial skin

Computer methods for process research and methods for processing the measurement results of the parameters of these processes are widely used in biology and medicine. Therefore, the problem of automation of biophysical measurements and computer processing of the results of such experiments is relevant. In the treatment of wounds and burns with a large surface area of tissue damage, medicine has to resort to artificial skin. A procedure for studying thermal processes in artificial skin and measuring its thermophysical parameters was developed. The measurement process was described. The thermophysical parameters of the artificial skin samples used in medicine for the treatment of wounds and burns were determined. The samples of the artificial skin used were made in Ukraine. Each sample was made from six layers of skin. To control the temperature distribution in the sample between the skin adjacent layers and on the surface of the sample, thermocouples were placed. The surface of the sample was heated with an incandescent lamp. The thermocouple signals were sent to an analog-to-digital converter (ADC), amplified, and digitally transmitted to a computer. Processing was carried out using the ADC software and the MATHCAD program. A mathematical model was obtained. For this purpose, a differential equation describing thermal processes in the sample was solved. The found temperature distribution function and its changes over time are in a good agreement with experimental data. The analysis of the function allows finding the thermal conductivity coefficient of artificial skin, its volume heat capacity, thermal diffusivity coefficient, and heat exchange coefficient with the external environment. The proposed method of measuring and processing experimental data makes it possible to detect main thermophysical parameters of artificial skin. Based on these results, a theoretical model was obtained that well describes the course of thermal processes in artificial skin, which makes it possible to predict the course of these processes. Such method is based on heating the skin with optical radiation. The thermal conductivity and thermal diffusivity of artificial skin are significantly less than such parameters of human skin, which should be considered when using it.

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

Direction of Arrival Estimation Based on DNN and CNN

The accuracy of Direction of Arrival (DOA) estimation primarily depends on the precision of the data. When the receiver uses a low-precision analog-to-digital converter (ADC), traditional DOA estimation algorithms exhibit poor accuracy. To face the challenge of multi-target DOA estimation in scenarios with low-precision ADC quantized sampling, this paper proposes a novel DOA estimation algorithm for quantized signals based on classification problems. A deep learning network was constructed using Deep Neural Networks (DNNs) and Convolutional Neural Networks (CNNs), divided into the quantized signal recovery framework and the DOA estimation framework. The DNN network is utilized to recover signals that have undergone low-precision quantization, while the CNN network addresses the classification problem to estimate the DOA from received data with an unknown number of signal sources. A comprehensive analysis of the impact of signal-to-noise ratio (SNR), the number of array elements, and the number of quantization bits on the proposed algorithm was conducted. Simulation results indicate that the proposed algorithm exhibits superior DOA estimation performance in low-precision scenarios, characterized by reduced computational complexity, thereby facilitating real-time DOA estimation.

A Reconfigurable, Nonlinear, Low-Power, VCO-Based ADC for Neural Recording Applications.

Neural recording systems play a crucial role in comprehending the intricacies of the brain and advancing treatments for neurological disorders. Within these systems, the analog-to-digital converter (ADC) serves as a fundamental component, converting the electrical signals from the brain into digital data that can be further processed and analyzed by computing units. This research introduces a novel nonlinear ADC designed specifically for spike sorting in biomedical applications. Employing MOSFET varactors and voltage-controlled oscillators (VCOs), this ADC exploits the nonlinear capacitance properties of MOSFET varactors, achieving a parabolic quantization function that digitizes the noise with low resolution and the spikes with high resolution, effectively suppressing the background noise present in biomedical signals. This research aims to develop a reconfigurable, nonlinear voltage-controlled oscillator (VCO)-based ADC, specifically designed for implantable neural recording systems used in neuroprosthetics and brain-machine interfaces. The proposed design enhances the signal-to-noise ratio and reduces power consumption, making it more efficient for real-time neural data processing. By improving the performance and energy efficiency of these devices, the research contributes to the development of more reliable medical technologies for monitoring and treating neurological disorders. The quantization step of the ADC spans from 44.8 mV in the low-amplitude range to 1.4 mV in the high-amplitude range. The circuit was designed and simulated utilizing a 180 nm CMOS process; however, no physical prototype has been fabricated at this stage. Post-layout simulations confirm the expected performance. Occupying a silicon area is 0.09 mm2. Operating at a sampling frequency of 16 kS/s and a supply voltage of 1 volt, this ADC consumes 62.4 µW.

Pre-compensating digital-to-analog converter impairments with an LSTM neural network

The performance of high-speed coherent communication heavily depends on digital-to-analog converters (DACs) when they operate within bandlimited and nonlinear regimes. We examine neural network (NN) based digital pre-distortion (DPD) methods to compensate the memory effects that are intertwined with the nonlinear response of the DAC. Using a long short-term memory (LSTM) NN architecture, we examine 8-level amplitude shift keying (ASK-8) at 64 Gbaud. We demonstrate experimental improvements of 1.6 dB and 2 dB in signal-to-noise ratio (SNR) compared to the Volterra and linear solutions, respectively.

End-to-end learning of joint noise shaping and probabilistic shaping for OAM mode division multiplexing transmission.

Intensity modulation direct detection (IM/DD) orbital angular momentum (OAM) mode division multiplexing (MDM) technology can greatly expand the capacity of a communication system, which is a promising solution for the next generation of high-speed passive optical networks (PONs). However, there are serious obstacles such as mode coupling, device nonlinear impairment, and quantization noise in an IM/DD OAM-MDM system with a low-resolution digital-to-analog converter (DAC). In this Letter, we propose a novel, to the best of our knowledge, end-to-end (E2E) learning scheme based on a double residual feature decoupling network (DRFDnet) emulator with joint probabilistic shaping (PS) and noise shaping (NS) for the OAM-MDM IM/DD transmission. Our DRFDnet emulator can accurately build a complex nonlinear model of an OAM-MDM system by separating the signal impairments into linear and nonlinear. Meanwhile, a DRFDnet-based E2E scheme for joint PS and NS is presented with the aim of compensating the signal impairment for the OAM-MDM IM/DD system. An experiment is carried out on a 200 Gbit/s PON system based on the OAM-MDM IM/DD transmission. The experimental results demonstrate that the proposed DRFDnet-based joint PS and NS scheme is a promising solution to effectively mitigate nonlinear distortions and outperforms the CGAN-based joint PS and NS scheme and traditional joint PS and NS scheme with receiver sensitivity improvements of 1.2 dBm and 2.5 dBm under hard-decision forward error correction (HD-FEC) thresholds, respectively. Our experimental results demonstrate that the proposed DRFDnet emulator-based E2E learning scheme is a viable candidate for future PON.

Impacts of sampling on the artificial noise-assisted terahertz secure communication systems

In this paper, we investigate an artificial noise (AN)-assisted terahertz (THz) secure communication system. Different from previous studies, we consider a non-ideal analog-to-digital converter (ADC) in the AN-THz system. Specifically, both synchronization noise and quantization noise in ADC are investigated. The normalized distortion matric is employed to calculate synchronization noise power and the Bellman’s theory is introduced for quantization noise power. Under the constrain of limited ADC power, the secrecy performance presents a ‘U-shaped’ curve versus the sampling rate and therefore the optimal sampling rate is derived. Moreover, we validate our theoretical model in the experiment, and our experimental results in 102 GHz show the synchronization noise power varies with the square of timing error, and the quantization noise power is affected by the total data length, which agree well with the model predictions.

Self-measurement and calibration of amplitude-frequency response for coherent optical transmitters with limited DAC resolution

Precise measurement and calibration of the amplitude-frequency response (AFR) of coherent optical transmitters (Tx) are paramount for generating high-quality signals, especially when the transmitter has insufficient bandwidth. The previously proposed self-measurement and calibration (SMC) method based on multi-tone signals (MTS) is cost-effective, fast, and convenient. However, this method exhibits a compromised AFR measurement precision in high-frequency regions, especially when the digital-to-analog converters (DAC) of the Tx have a limited resolution. To solve this problem, we optimize the amplitudes and phases of the MTS by pre-emphasis and the sequential quadratic programming (SQP) algorithm to improve the accuracy in the high-frequency region. Numerical simulations show a notable reduction in AFR measurement error, from about 4 dB to 0.8 dB, when employing a DAC with a four-bit resolution. Additionally, experiments utilizing a 22 GHz 3-dB bandwidth transmitter to generate 61 GBaud dual-polarization 16QAM signals demonstrate a 60% BER reduction. The proposed SMC method is attractive for high-baud rate systems employing Tx with limited bandwidth and DAC resolution.

USE OF IIoT TECHNOLOGIES IN ENGINE MONITORING AND CONTROL SYSTEMS

Determining the operating parameters of engine systems is very important to ensure its long-term reliability. Modern power plants use a large number of modern electronic components (sensors, controllers, etc.). All systems generate a huge volume of data that must be tracked, processed and analyzed, which in turn creates calls to gateways and servers. However, the current state of development of microcontrollers and their power allow the use of fog computing, which can lead to more efficient use of both the power plant and data transmission systems. Also, the use of modern microcontrollers and fog computing allows modernizing old power plants with minimal effort and creating new information nodes for monitoring the state of nodes and engine systems and easily combining them with systems already existing on the engine. The selection of a microcontroller and justification of its type for the modernization of the fuel system of a diesel engine are considered. Rapid processes occur in the high-pressure fuel system of diesel engines, which can be determined by changes in fuel pressure. For detailed measurement of processes in the fuel system, measurements should be made with a frequency of at least 24 kHz, i.e.: if the crankshaft rotation frequency is 4000 min-1, then 24,000 measurements should be made every second (when registering data after 1 degree of crankshaft rotation). Another indicator that imposes its requirements is the bit rate of the analog-to-digital converter (ADC), which depends on the range of recorded values. For example, an ADC with a resolution of 8 bits is capable of outputting 256 discrete values (0…255). That is, the higher the bit rate, the more sensitive the converter is to signal changes, and 8 bits may not be enough. Thus, even a small number of sensors can generate a huge amount of data. Transmitting large amounts of data is irrational and can lead to data loss and "clogging" of transmission channels, which challenges the computational performance of the microprocessor.

Design of a Portable Electronic Nose for Identification of Minced Chicken Meat Adulterated With Soybean Protein Isolate

ABSTRACTThe study aimed to develop a portable electronic nose system for detecting adulteration with soybean protein isolate (SPI) in chicken meat. The system mainly consisted of three parts: the gas sensor array, the DSP28335 control board, and the upper computer. The DSP28335 control board, developed using C language, included analog to digital converter (ADC) module, digital output (DO) module, pulse width modulation (PWM) module, controller area network (CAN) module, power module, drive circuit, and so forth. The upper computer, developed using LabVIEW, facilitated user interaction with the user by primarily handling CAN configuration and monitoring, displaying and storing sensor data, temperature and flow data, and sending and monitoring electronic nose commands. The feasibility of the proposed electronic nose for characterizing adulterated chicken meat was tested on six classes of chicken meat that had been adulterated with varied quantities of SPI. The mass fractions of SPI were 0%, 5%, 10%, 15%, 20%, and 25%, respectively. On the basis of odor data from the electronic nose, K‐nearest neighbor (KNN), linear discriminant analysis (LDA), and support vector machine (SVM) were applied to qualitatively distinguish minced chicken meat with different adulteration ratios. The results showed that the SVM model had the best recognition effect. When the best parameters (c, g) were c = 16 and g = 1, the accuracy of SVM model was 97.22% and 93.75% in the training and testing sets, respectively. These results demonstrated that the portable electronic nose designed in this paper effectively identifies minced chicken meat under various adulteration conditions, enabling rapid and nondestructive detection of chicken meat adulteration.

The MIZAR ASIC: 64-channel zone-sampling based ASIC for Cherenkov light detection from sub-orbital and orbital altitudes

This work describes the implementation of a 64-channel Application Specific Integrated Circuit (ASIC) developed in a commercial 65 nm CMOS technology to readout the signals collected by a camera plane made of Silicon Photo-Multipliers. The aim of the application is the identification of Extensive Air Showers (EASs) by detecting optical Cherenkov light generated by Ultra-High Energy Cosmic Rays (UHECRs) and Neutrinos (UHENUs) from sub-orbital and orbital altitudes. In this context, the ASIC is designed to store each event into an analog memory based on 256 configurable cells per channel. Then the chip forms a hitmap sent to an Field Programmable Gate Array (FPGA) to recognize a pattern of interest. If the signal is externally validated, the digital conversion can occur on-board using an array of 12-bits Wilkinson analog-to-digital converters (ADCs) at 200 MHz of clock. The readout is realized with two serializers running at 400 MHz in double data rate (DDR). Both the number of cells and the resolution can be configured into partitions of 32, 64 or 256 cells and in the range 8–12 bits respectively, becoming a key feature of this ASIC. The chip submission and testing are planned for the forthcoming months.

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio.

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively.

An energy-efficient 16 MS/s 10-bit SAR ADC with MSB-block switching scheme

An energy-efficient MSB-block switching scheme without common-mode voltage variation for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. Benefit from a pair of extra switches embedded in the capacitive digital-to-analog converter (CDAC), the proposed MSB-block switching scheme can reduce switching energy without further reducing the capacitor unit. The proposed switching scheme can achieve 93.8 % and 49.9 % savings in switching energy compared with the conventional switching scheme and the Vcm-based switching scheme, and the simulated differential-nonlinearity (DNL) and integrated-nonlinearity (INL) are 0.160 and 0.156LSB, respectively. The proposed switching scheme is verified in a 1.2-V 10-bit 16 MS/s SAR ADC in 65 nm CMOS technology. At maximum sampling rate, the proposed SAR ADC achieves an effective number of bits (ENOB) of 9.50 and a power consumption of 103.5μW, leading to a Figure of Merit of 8.93 fJ/Conversion-step.

A 10-bit 70-MS/s SAR ADC with Reference Buffer in 40nm CMOS

Abstract A 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with reference buffer is presented in this paper. Segmented capacitive DAC with redundant 2bits is designed to relax the design of reference buffer. A hybrid switching sequence is applied to the ADC to optimize power consumption. The Measurement results Show that the core SAR ADC achieves 48.52 dB SNDR and 56.67 dB SFDR at 70 MS/s sampling rate and Nyquist input frequency, consuming 2.50mW power consumption, achieving a FoM of 163.6 fJ/step. The ADC occupies an active area of 0.017 mm2 in 40nm CMOS technology.

A Calibration Scheme for a 800-Ms/s 14 Bit Pipelined ADC in 28-nm CMOS

Abstract A calibration scheme is proposed to compensate linear and nonlinear errors including offset, cap mismatch, second- and higher-order harmonics and memory induced errors in pipelined analog-to-digital converters (ADCs). The alternating minimization (AM) algorithm is proposed to accurately estimate the coefficients of the errors. As an accurate input value is hardly acquired in practical measurements, instead, the proposed scheme estimates the input and the error coefficients jointly. Once the error coefficient was calculated, it will be recorded in a lookup table (LUT). The scheme has been demonstrated in a 800-Ms/s 14-bit pipelined ADC fabricated in a 28nm CMOS process, which features a signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) improvement of 2.49 dB and 11.49 dB at 800-Ms/s.

Designing Efficient Bit-Level Sparsity-Tolerant Memristive Networks.

With the rapid progress of deep neural network (DNN) applications on memristive platforms, there has been a growing interest in the acceleration and compression of memristive networks. As an emerging model optimization technique for memristive platforms, bit-level sparsity training (with the fixed-point quantization) can significantly reduce the demand for analog-to-digital converters (ADCs) resolution, which is critical for energy and area consumption. However, the bit sparsity and the fixed-point quantization will inevitably lead to a large performance loss. Different from the existing training and optimization techniques, this work attempts to explore more sparsity-tolerant architectures to compensate for performance degradation. We first empirically demonstrate that in a certain search space (e.g., 4-bit quantized DARTS space), network architectures differ in bit-level sparsity tolerance. It is reasonable and necessary to search the architectures for efficient deployment on memristive platforms by the neural architecture search (NAS) technology. We further introduce bit-level sparsity-tolerant NAS (BST-NAS), which encapsulates low-precision quantization and bit-level sparsity training into the differentiable NAS, to explore the optimal bit-level sparsity-tolerant architectures. Experimentally, with the same degree of sparsity and experiment settings, our searched architectures obtain a promising performance, which outperform the normal NAS-based DARTS-series architectures (about 5.8% higher than that of DARTS-V2 and 2.7% higher than that of PC-DARTS) on CIFAR10.

Analysis of the Second-Order NS SAR ADC Performance Enhancement Based on Active Gain

This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C noise and the conversion rate. After having presented the conversion principle, the theoretical analysis of the performance enhancement based on noise and other considerations is presented.

Prototype Implementation of a Digitizer for Earthquake Monitoring System.

A digitizer is considered one of the fundamental components of an earthquake monitoring system. In this paper, we design and implement a high accuracy seismic digitizer. The implemented digitizer consists of several blocks, i.e., the analog-to-digital converter (ADC), GPS receiver, and microprocessor. Three finite impulse response (FIR) filters are used to decimate the sampling rate of the input seismic data according to user needs. A graphical user interface (GUI) has been designed for enabling the user to monitor the seismic waveform in real time, and process and adjust the parameters of the acquisition unit. The system casing is designed to resist harsh conditions of the environment. The prototype can represent the three component sensors data in the standard MiniSEED format. The digitizer stream seismic data from the remote station to the main center is based on TCP/IP connection. This protocol ensures data transmission without any losses as long as the data still exist in the ring buffer. The prototype was calibrated by real field testing. The prototype digitizer is integrated with the Egyptian National Seismic Network (ENSN), where a commercial instrument is already installed. Case studies shows that, for the same event, the prototype station improves the solution of the ENSN by giving accurate timing and seismic event parameters. Field test results shows that the event arrival time and the amplitude are approximately the same between the prototype digitizer and the calibrated digitizer. Furthermore, the frequency contents are similar between the two digitizers. Therefore, the prototype digitizer captures the main seismic parameters accurately, irrespective of noise existence.