Analog Baseband Research Articles

Analysis and design of a 0.9 V 1 GHz-BW 14.6 dBm-OIP3 broadband receiver with current-mode analog baseband in 12 nm FinFET CMOS

This study introduces a wideband LNTA-based receiver employing full current mode (FCM) signal transmission, leveraging a broadband and highly linear current-mode analog baseband (CMAB). The CMAB module comprises a shunt feedback low pass filter and a programmable gain amplifier (PGA) with wide bandwidth, utilizing a regulated CG current mirror design, enriched by gm-boosting methodology and positive feedback capacitance reutilization through an identical boost amplifier. Fabricated in 12 nm FinFET CMOS process, the FCM receiver attains notable characteristics including a baseband bandwidth of 1 GHz, a conversion gain of 30 dB, a noise figure of 5.2 dB, and an OIP3 of 14.6 dBm, while operating with a low supply voltage of merely 0.9 V. Simulation results validate the efficacy of this FCM receiver for wideband communication, effectively addressing the linearity constraints associated with low supply voltages and maximizing the advantages of FinFET technology in current-mode signal transmission. The total layout area is 0.484 mm2.

UWB Microwave Breast Screening With Self- Mixed Baseband Analog Signal Processing

UWB Microwave Breast Screening With Self- Mixed Baseband Analog Signal Processing

A Reconfigurable Analog Baseband for Multistandard Wireless Receivers in 22-nm CMOS

This paper presents a low noise, and high linearity reconfigurable receiver (RX) analog baseband (ABB) with tunable bandwidth (BW) and gain for multi-standard applications. The designed ABB consists of a programmable gain amplifier (PGA) and a second-order active RC low-pass filter (LPF) with cutoff frequency range from 0.7 MHz–10 MHz, whereas the gain could be tuned between 0 dB and 49 dB. The proposed ABB is implemented in 22 nm CMOS process. The post-simulation results show that the current consumption is 3.36 mA from 1 V supply and the area occupies 571×328 μm 2. The ABB achieves 42.8 dBm in-band third-order harmonic intercept point (IIP3). The spurious-free dynamic range (SFDR) and in-band total harmonic distortion (THD) is 83.2 dBc and is -83.1 dB, respectively. The input referred in-band integrated noise (IRN) is 144.8 μVrms . A digital DCOC is used to calibrate the output DC level.

VCII based electronically tunable multi‐mode filter structure with fourth order low‐pass function for the HF band applications

SummaryIn this paper, we propose an electronically tunable multi‐mode filter structure with fourth‐order current mode low‐pass function based on second‐generation voltage conveyor (VCII) for the analog baseband applications. The fourth‐order low‐pass circuit consists of second‐order core filter structures including band and low‐pass outputs. The proposed fourth‐order circuit's cut‐off frequency can be easily varied from 1.6 up to 17.2 MHz for the high frequency (HF) applications used in multi‐standard receivers. Also, the core circuit of the fourth‐order architecture possesses current mode and transresistance mode filter functions enabling signal conversion and different signal operations. The given architecture has 116 μm × 39 μm chip area, and post layout simulations are demonstrated extensively. In addition, the performance of the proposed structure is examined based on commercial elements (AD844s). Also, detailed linearity analysis is given using post layout extractions. In fourth‐order low‐pass structure, cut‐off frequency can be safely tuned from 1.6 up to 17.2 MHz, whereas consumed power can be reduced to 0.769 μW. It can be investigated that the proposed circuit can be safely used for the analog baseband and HF operations in wireless receivers.

A D-Band Joint Radar-Communication CMOS Transceiver

A <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula> -band joint radar-communication complementary metal–oxide–semiconductor (CMOS) transceiver featuring a dual-function mode multiplexer, a power-combining PA with high output power, a current choking high-gain mixer, a two-point modulation (TPM) frequency-modulated continuous-wave (FMCW) digital phase-locked loop (PLL) with a dual-core DCO, and a wideband I/Q local oscillator (LO) generator is implemented in 28-nm CMOS technology. In the radar mode, the RF front end demonstrates 46-GHz bandwidth (BW), and the on-chip PLL/LO generated FMCW chirp achieves a BW of 30 GHz and a slope of 30 GHz/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu \text{s}$ </tex-math></inline-formula> . In the communication mode, the transceiver including the analog baseband realizes 20-GHz BW, and the image rejection ratio (IRR) is better than 40 dB. The measured transmitter (TX) saturated output power is 13 dBm, and the output 1-dB compression point (OP1dB) is 8.3 dBm. The measured typical PLL phase noise is −111.3 dBc/Hz at a 1-MHz offset from an 11.69-GHz carrier frequency. The TX-to-RX over-the-air (OTA) modulation–demodulation measurement with QPSK and 16-QAM signals shows the error vector magnitude (EVM) of −16.5 and −19.7 dB, respectively.

A power-efficient high GBW operational amplifier with its analog baseband IC implementation in 40-nm CMOS technology

A power-efficient high GBW operational amplifier with its analog baseband IC implementation in 40-nm CMOS technology

5 Gs/s 등가 시간 샘플링을 통한 K-Band UWB 레이다 송수신기

In this paper, a K-band complementary metal-oxide-semiconductor (CMOS) ultra-wide-band (UWB) radar is presented. Using an equivalent time sampling technique with a delay-locked loop (DLL), virtual 5 Gs/s high-speed sampling is implemented without using a high-speed analog–digital converter. The receiver comprises a low-noise amplifier, radiofrequency variable amplifier, mixer, and baseband analog, whereas the transmitter comprises switching and driver amplifiers. For the UWB signal, a voltage-controlled oscillator-based impulse generator provides a periodic pulse signal using a switching amplifier controlled by a DLL clock. The proposed UWB radar SoC is fabricated using a 65 nm CMOS wafer, and the measured conversion gain and noise figure of the radar receiver are 79 dB and 7.4 dB, respectively, at 24 GHz. Consequently, we confirm that the measurement of the 11.3 m standard sphere is feasible.

An electronically tunable active-C based analog baseband filter for multi-standard applications

An electronically tunable active-C based analog baseband filter for multi-standard applications

Analysis of digital pre-distortion with I/O interfaces for analog baseband signal over broadcasting satellites

Broadcasting satellite systems currently use multilevel modulation schemes, which are vulnerable to non-linear distortion, while their on-board amplifiers operate near the saturation point. We have developed a digital pre-distortion (DPD) embedded transmitter and demonstrated its effectiveness over a 12-GHz-band satellite transponder. To improve its versatility, we developed an external DPD adder, which enables existing transmitter to give an analog baseband signal its function. In this study, we confirm the effectiveness of the external DPD adder by evaluating the transmission performance of 64APSK over the satellite transponder.

Analog Baseband Self-Interference Canceler with Digitally Generated Replica Signal for Full Duplex

Analog Baseband Self-Interference Canceler with Digitally Generated Replica Signal for Full Duplex

Integrating Homogeneous Current-Saturation Graphene Transistors Into High-Linearity Amplifiers

In this work, a new type of graphene ICs only comprising multiple graphene field-effect transistor (GFET) components is first reported. Based on the GFET design that enables homogeneous electrical characteristics in batch-made devices, the practicality and functionality significances of multi-GFET integration are experimentally demonstrated via high-fidelity amplifiers for baseband analog signals. Different from the quadratic relationship of the gate-controlled current output (in saturation region) in the traditional silicon-based MOSFETs, the saturation current output of GFETs relating to the gate-controls possesses high linearity. This advantage overcomes the inherent nonlinear distortion issues in the existing silicon MOSFET amplifiers and potentially provides a promising scenario for the accurate preamplification of weak analog signals. Besides, the novel circuit configuration and signaling principle may expand the developmental paradigm of analog amplifiers and set groundwork for the development and practicalization of advanced carbon-based nanoelectronic ICs.

A 0.015mW quasi-passive reconfigurable complex band-pass filter for analog baseband

A 0.015mW quasi-passive reconfigurable complex band-pass filter for analog baseband

A Closed-Loop Reconfigurable Analog Baseband Circuitry With Open-Loop Tunable Notch Filters to Improve Receiver Tx Leakage and Close-in Blocker Tolerance

This paper presents an analog baseband (ABB) circuit in a 0.13 μm SiGe technology for transmitter leakage cancellation and close-in blocker suppressions in fully duplex (FD) frequency-modulated continuous-wave (FMCW) radar. This ABB comprises a programmable gain amplifier (PGA) and a cascaded LPF/Notch hybrid, which incorporates a closed-loop (CL) reconfigurable low-pass filter (LPF) and an open-loop (OL) tunable notch filter. The adopted key topologies include active-RC bi-quads and Gm-C ones. In an FD FMCW transceiver, Tx leakage and close-in blockers are difficult to be eliminated in the RF domain, especially when leakage/blockers are very close to desired signals or even in-band in the frequency domain. This LPF/notch hybrid is proposed to solve this issue. The LPF and PGA provide bandwidth (BW)/gain programmability, while the Gm-C bi-quad provides adaptable center frequency for a notch filter. With this adaption, the notch filter could be adjusted to match the leakage/blocker offset frequency. Thus, digitally discrete programmability and analog continuous tuning capability are combined in this solution for improving the overall front-end interference robustness without de-sensitizing the Rx. Furthermore, the order of LPF/notch hybrid is programmable from 2 to 10 with a step of 2 for different rejection levels of interferences. The measured chip achieves a -3dB bandwidth of 6 21 MHz with 4-bit digital control and 1 MHz/step programmability, and a voltage gain of 0 70 dB with 9-bit digital control (3-bit from pre-amplifier, and 6-bit from PGA with 1 dB/step). With the condition of 15 dB gain, output P-1dB is 11.8 dBm@3MHz, and the output IP3 is 20.8 dBm@3MHz.

An Analog Baseband Circuit for Wireless Local Area Networks Transceiver in 55 nm CMOS Technology

The design of the analog baseband circuit is based on 55 nm CMOS technology and is integrated in an IEEE 802.11ax concurrent dual band four antenna transceiver. A low-pass filter (LPF) of the receiver was multiplexed with an LPF-transmitter such that the last three stages of the fifth order LPF-receiver were used by the LPF-transmitter, and the first programmable gain amplifier (PGA) of the receiver was partially multiplexed with the PGA-transmitter such that the PGA-receiver and the PGA-transmitter shared the same operational amplifier and input resistance, thereby reducing the power consumption, noise, linearity, and area of intermediate frequency (IF) of the transmitter designed separately. The typical bandwidth of the IF-receiver is 10/20/40 MHz; that of the IF-transmitter is 12/24/50 MHz. The gain range of the IF-receiver and the IF-transmitter is 0.1–65.5 dB and −10.1 to 3.98 dB, respectively. Under the voltage of 1.5 V, the current of the IF-receiver is 3.86 mA. As for the IF-transmitter, the current is 1.78 mA when supply voltage is 1.5 V. The input referred noise (IRN) of the IF-receiver at 10 MHz bandwidth (BW) and 62 dB gain is 14.52 nV/√ Hz, while the IRN of the IF-transmitter at 10 MHz BW and −6 dB gain is 95.16 nV/√ Hz. The suppression ability of the DC offset cancellation circuit is 35.08/80.9/110.1/113 dB. The area of the analog baseband circuit is 0.17 mm2.

Dual-Band, Two-Layer Millimeter-Wave Transceiver for Hybrid MIMO Systems

This article presents a two-layer low-complexity fully connected (FC) RF/analog weighting multi-input–multi-output (MIMO) transceiver comprising an RF weight layer and an analog–baseband weight layer. The transceiver can serve as a small-scale MIMO system by itself and can serve as the building block in a larger hybrid MIMO system. The architecture mitigates the complexity versus spectral-efficiency tradeoffs of existing MIMO architectures and enables MIMO stream/user scalability, superior energy efficiency, and spatial-processing flexibility. A compact, reconfigurable bidirectional circuit architecture is introduced, including a new Cartesian-combining/splitting beamforming receiver/transmitter, dual-band bidirectional beamforming network, dual-band frequency translation chains, and baseband Cartesian beamforming with an improved programmable gain amplifier design. A 28-/37-GHz band, two-layer, eight-element, four-stream hybrid MIMO transceiver prototype is designed in 65-nm CMOS to demonstrate the above features. The prototype achieves accurate beam/null-steering capability, excellent area/power efficiency, and state-of-the-art TX/RX mode performance in two simultaneous bands while demonstrating multi-antenna (up to eight) multi-stream (up to four) over-the-air spatial multiplexing operation using the proposed energy-efficient two-layer hybrid beamforming scheme.

Wideband Beamforming With Rainbow Beam Training Using Reconfigurable True-Time-Delay Arrays for Millimeter-Wave Wireless [Feature

The decadal research in integrated true-time-delay arrays have seen organic growth enabling realization of wideband beamformers for large arrays with wide aperture widths. This article introduces highly reconfigurable delay elements implementable at analog or digital baseband that enables multiple Spatial Signal Processing (SSP) functions including wideband beamforming, wideband interference cancellation, and fast beam training. Details of the beam-training algorithm, system design considerations, system architecture and circuits with large delay range-to-resolution ratios are presented leveraging integrated delay compensation techniques. The article lays out the framework for true-time-delay based arrays in next-generation network infrastructure supporting 3D beam training in planar arrays, low latency massive multiple access, and emerging wireless communications standards.

Analog self-interference cancellation based on zero-forcing sampling for in band full duplex radios

A uniformly zero-forcing sampling method applied in the base-band analog domain is proposed for Self-Interference Cancellation (SIC) in Band Full-Duplex (IBFD) radios. In order to releasing the ADC dynamic range to enable the desired signal for further processing in the digital domain, the SIC is performed when ADC samples the received signal. Specifically, first, an auxiliary signal is designed to rectify the zero-crossings of the self-interference (SI) to be consistent with the ADC sampling points. Second, to achieve the auxiliary signal, a zero-forcing function is established by leveraging one-to-one mapping from the complex domain to the complex exponential domain. Meanwhile, a closed-form expression of the zero-forcing function is derived according to the Z transformation. Additionally, an orthogonal pilot structure is proposed to improve the SIC capability, and the computational complexity is investigated. Finally, simulation and experimental results show the effectiveness of the proposed method.

A 71-to-86-GHz 16-Element by 16-Beam Multi-User Beamforming Integrated Receiver Sub-Array for Massive MIMO

This article presents a 71–86 GHz 16-element array receiver application-specified integrated circuit (ASIC) for Massive multiple-input–multiple-output (MIMO) wireless uplink, featuring a multiple-output analog beamformer (BF) supporting up to 16 spatially multiplexed users at the same time. The ASIC includes 16 direct-conversion mixer-first RX front-ends, local oscillator (LO) generation and distribution, and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times 16$ </tex-math></inline-formula> fully connected baseband analog beamformer, which derives each user stream as a linear combination of all the 16 antennas. The 16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> 28 nm CMOS ASIC is packaged on an organic interposer including a linear patch antenna array. Over-the-air measurements demonstrate up to 2 Gb/s single-user data-rate, and four simultaneous links at 500 Mb/s each, with number of users and data rate only limited by setup constraints. Circuits are optimized for low power consumption in order to enable scaling to massive arrays, and consumes 1.7 W total power, for a power figure of 7 mW/antenna/user.

4th order current-mode and transresistance-mode MOSFET-C low-pass filter for multi-standard receivers

This work presents a novel 4th order current-mode and transresistance-mode low-pass filter based on MOSFET-C architecture. Proposed filter's cut-off frequency can be easily adjusted from 15 MHz up to 45 MHz for the analog baseband filters used in multi-standard receivers. The main core circuit of the filter contains only 7 transistors in order to reduce chip area and power consumption. Also, the proposed 4th order architecture have dual outputs in different modes facilitating signal conversion and different signal operations. The proposed structure has (54.3 μm × 34.1 μm) chip area and post layout simulations are examined extensively to prove performance of the filter. Also, input referred noise (IRN) characteristics of the filter outputs are shown in order to overcome thermal noise effects worsening the performance of the filter. Power consumption changes from 195.8 μW up to 1.37 mW whereas cut-off frequency is varied from 15 MHz up to 45 MHz. Provided results show that the proposed filter scheme brings a promising opportunity to designers for the analog baseband operations in multi-standard communication receivers.

Toward a fully integrated automotive radar system-on-chip in 22 nm FD-SOI CMOS

AbstractNext-generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated radar system-on-Chips (SoC). This article discusses the challenges and the opportunities of the integration of the millimeter-wave frontend along with the digital backend. A 76–81 GHz radar SoC is presented as an evaluation vehicle for an automotive, fully depleted silicon-over-insulator 22 nm CMOS technology. It features a digitally controlled oscillator, 2-millimeter-wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory. The radar SoC evaluation chip is packaged and flip-chip mounted to a high frequency printed circuit board for functional demonstration and performance evaluation.