Analog-to-digital Research Articles

Digitizing Low-Frequency Analog Control Circuit Using Bilinear Function Algorithm

In the past, low-frequency analog control circuits were largely used in analog control systems. With the rapid development of modern digital electronic technology, the digitization of traditional low-frequency analog control circuits while retaining the same functions as the original analog control systems has become an important trend in the field of electronic design. For this reason, this study aimed to develop an analog signal digitization model for control signals at a low frequency below 10 Hz. In terms of signal receiving and transmission requirements, the proposed model is configured with analog-to-digital converter (ADC), digital-to-analog converter (DAC), and pulse width modulation (PWM) functions. In the development environment, the input and output signals are first normalized and processed with PWM, enabling the digital signal processor to deal with analog signal receiving, processing, and external transmission. To replace the existing compensator in analog circuits, a digital compensator is used in the digital signal processor. Based on the bilinear function in MATLAB software, the parameter values demanded for the digital compensator can thus be obtained, achieving the automatic calculation of bilinear transformation in the system. Multisim simulation is then used to simulate analog circuit systems for comparison with the digitized outcomes. The experimental results reveal that the performance of the designed digital control circuit matches the simulation outcomes in both Bode gain (dB) and phase responses when the signal frequency is below 10 Hz. The effectiveness of the digitized analog control circuit for low-frequency control signals is therefore confirmed.

Development of a 10-bit ultra-low power SAR ADC with programmable threshold in 130 nm CMOS technology

The design and simulation results of an ultra-low power, fast 10-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) in CMOS 130 nm technology are presented. This ADC is an extension of an experimentally verified 10-bit SAR ADC (INL, DNL < 0.5 LSB, ENOB > 9.5), working up to 50 MSps and consuming 680 μW at 40 MSps. The goal of the present work was to add a programmable threshold for the processed input signal, to stop the conversion and thus greatly reduce power consumption in case the signal is below the threshold. The new ADC works up to around 40 MSps and consumes around 350 μW at 40 MSps for low particle occupancy.

Design and evaluation of UKRI-MPW1: a monolithic HV-CMOS pixel sensor with high radiation tolerance

A monolithic High Voltage CMOS (HV-CMOS) prototype, UKRI-MPW1, has been developed to further improve the radiation tolerance of this technology, which is a promising candidate for future high-energy physics experiments. UKRI-MPW1 addresses the issues of high leakage current and parasitic channels identified in its predecessor, UKRI-MPW0, by incorporating an improved chip ring structure and a custom p-shield layer. Additionally, a new pixel flavour with an NMOS-only trimming Digital-to-Analogue Converter (DAC) further improves pixel performance. This chip has demonstrated a radiation tolerance of up to 3 × 1015 neq/cm2.

Development of a TAC-based TDC in 130 nm CMOS technology

The design and measurement results of a prototype Time-to-Digital Converter (TDC) fabricated in 130 nm CMOS technology are presented. The TDC architecture with analog interpolators was chosen, which was motivated by previous experience in Analog-to-Digital Converter (ADC) design [1]. The measured time difference between the event and the trigger signal is converted to the amplitude and then digitised by a 10-bit ADC. The TDC prototype is functional and achieved good Differential Non-Linearity (DNL) and jitter (below 1 LSB), slightly dependent of the selected time precision. The obtained Integral Non-Linearity (INL) is significantly higher than simulated and should be still improved. The prototype Application-Specific Integrated Circuit (ASIC) has configurable time resolution from 15 ps to 140 ps, which gives the total possible time measure range from ±9.5 ns to ±70 ns. In this paper the architecture of the developed TDC is described, comprising the implementation of the Time-to-Analog Converter (TAC) and 10-bit ADC. The measurements of the prototype 8 channel TDC ASIC, showing its linearity and timing resolution are also shown.

The spectrometer development of CosmoCube, lunar orbiting satellite to detect 21-cm hydrogen signal from cosmic dark ages

Abstract The cosmic Dark Ages represent a pivotal epoch in the evolution of the Universe, marked by the emergence of the first cosmic structures under the influence of dark matter. The 21-cm hydrogen line, emanating from the hyperfine transition of neutral hydrogen, serves as a critical probe into this era. We describe the development and implementation of the spectrometer for CosmoCube, a novel lunar orbiting CubeSat designed to detect the redshifted 21-cm signal within the redshift range of 13 to 150. Our instrumentation utilizes a Xilinx Radio Frequency System-on-Chip (RFSoC), which integrates both Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs), tailored for the spectrometer component of the radiometer. This system is characterized by a 4096 FFT length at 62.5 kHz steps using a Polyphase Filter Bank (PFB), achieving an average Effective Number of Bits (ENOB) of 11.5 bits throughout the frequency of interest, from 10 MHz to 100 MHz. The spectrometer design is further refined through loopback tests involving both DAC and ADC of the RFSoC, with DAC outputs varying between high (+1 dBm) and low (-3 dBm) power modes to characterize system performance. The power consumption was optimized to 5.45 W using three ADCs and one DAC for the radiometer. Additionally, the stability of the ADC noise floor was investigated in a thermal chamber with environmental temperatures ranging from 5○C to 40○C. A consistent noise floor of approximately -152.5 dBFS/Hz was measured, with a variation of ±0.2 dB, ensuring robust performance under varying thermal conditions.

Differential‐sampling control algorithm and theoretical analysis for programmable‐Josephson‐voltage‐standard traceability application

AbstractThe programmable Josephson voltage standard (PJVS) provides a new way and higher accuracy for the traceability of traditional measurement standards. To improve the applicability and reduce the uncertainty of the PJVS, a PJVS‐based analog‐to‐digital converter (ADC) scheme for the alternating‐current (AC) voltage measurement is proposed and the theoretical error model is derived based on discrete Fourier transform. The influence of the amplitude and phase error of the AC voltage is simulated; an adaptive differential‐sampling control algorithm is proposed to control the relative amplitude and phase between the AC voltage and PJVS voltage, improving the error of the PJVS‐based ADC. Furthermore, the authors obtained the exponential decay algorithm error curve that varies with phase error and the M‐shaped variation curve with sampling error by simulation and a PJVS‐based ADC with different sampling DVM, which provides possibilities for optimizing the measurement error of the PJVS‐based ADC.

A Power Analysis Method for Self-Interference Signal Components in Full-Duplex Transceivers Under Constant/Nonconstant Modulus Signal Stimulation

The existence of multiple self-interference (SI) signal components, particularly the nonlinear ones, seriously constrains the performance of self-interference cancellation (SIC) methods. To decrease the complexity of SIC methods in full-duplex devices, this article proposes a power analysis method for SI signal components in a full-duplex transceiver. The proposed method comprises a separate analysis algorithm and a system-level power model. Initially, the algorithm is conducted to obtain the spectrum of the linear and nonlinear components in the power amplifier (PA) output signal. Once the linear-to-nonlinear power ratio (LNPR) has been obtained, a system-level power model is constructed by taking both the transmitter noise and analog-to-digital converter (ADC) quantization noise into account. The proposed power model allows for the allocation of SIC method performance in multiple domains during the design of full-duplex transceivers at the top level, thereby reducing the overall system complexity. The simulation results demonstrate that in a full-duplex transceiver with only antenna isolation, the power of the SI signal component is susceptible to alterations due to the operating waveform and transmission power. Finally, the accuracy of the power analysis method is verified through measurement and Simulink.

Design of Direct Digital Synthesizer of Gilbert Cell Using Chisel Generator with NCO

Numerous digital communication systems, such as digital radio and modems, digital converters, computer base stations, etc., depend on numerically controlled oscillators (NCOs). NCOs are so often utilized because of the wide range of beneficial characteristics that possess. Direct digital frequency synthesizers (DDFSs) are essential elements of modern radio electronics. These signals can be generated using either analogue circuitry or digital circuitry. These signals are generated by an NCO in a digital system, and they are then converted to analogue signals by a digital-to-analog converter (DAC). This paper presents a direct digital synthesizer (DDS) of Gilbert cell using a chisel generator with NCOs. The DDS has a sine-wave generator analogue Gilbert cell, a phase accumulator, wave-correction ROM (WCR), RAM, and DACs. Two ground-signal-ground (GSG) single-ended microwave probes and two DC probes are used to test the DDS on the wafer. The results of the test demonstrate that it can create sine waves with a frequency resolution of 23.44[Formula: see text]MHz and can operate consistently at 6[Formula: see text]GHz clock frequency.

PLC-AWG-based FBG demodulation system for high-frequency vibration measurement.

A fiber Bragg grating (FBG) demodulation system based on arrayed waveguide gratings (AWGs) is proposed. We designed the key parameters of the AWG, prepared the AWG chip based on a silica-on-silicon planar light wave circuit (PLC) platform, and integrated the AWG with a PD array. Eight AWG output channels were selected and the output signals from the photodiode (PD) array was connected to the board with gold wire bonding. The demodulation circuitry consists of transimpedance amplifiers (TIAs), analog-to-digital converters (ADCs), and a main control chip. The signal from the PDs are synchronously captured and amplified and then transmitted at high speed through an Ethernet interface. The total volume of the demodulation system is 200 × 100 × 60 mm3. Experiments show that the wavelength demodulation accuracy of the system is 4.24 pm, the demodulation rate is more than 200 kHz, and the average error of the demodulation acceleration is better than 22.8 mg. The proposed demodulation system can be applied in the field of high-frequency vibration sensing of FBGs.

Improvement of noise performance in the phase locking laser Doppler vibrometer with a low carrier frequency via harmonic locking

A heterodyne laser Doppler vibrometer (LDV) with a Bragg cell has a stationary signal carrier at a frequency of at least 35 MHz. The expensive Bragg cell with the restricted shift frequency is not an optimal solution to meet the requirements for many measurement scenarios. For vibrations with low frequencies and small amplitudes, a tens-of-megahertz carrier frequency not only wastes bandwidth at the photodetector but also requires a fast and expensive analog-to-digital converter (ADC). Compared to the Bragg-cell-based LDVs, LDVs with an optical phase-locked loop (OPLL) enable a selectable carrier and thus can provide a low carrier frequency. However, problems arise when the carrier frequency is smaller than the laser linewidth and the OPLL bandwidth. We accidentally were able to offset-lock the OPLL on the harmonic component of the heterodyne oscillator signal and explored this phenomenon, which enables carrier frequencies much smaller than the laser linewidth of the locked lasers at a smaller noise level. In this paper, we demonstrate a carrier frequency down to 3 MHz with a 3.3 dB better signal-to-noise-ratio (SNR) compared to the traditional locking technology. Our findings may enable very cost-efficient LDVs.

Multisampling with Sigma-Delta ADCs for Medium-Voltage Cascaded H-Bridge Converters

The control of medium-voltage cascaded H-bridge (CHB) converters demands precise, high-bandwidth, low-latency, and isolated measurements. Traditional analog-to-digital converters (ADCs) can facilitate multisampling methods to meet these requirements but do not provide the high-voltage galvanic isolation that may be necessary in a system operating at medium voltage. Sigma-Delta ADCs (SD-ADCs) present a promising alternative due to their superior noise rejection capabilities and direct integration with the optical fiber interface. However, the inherent latency associated with SD-ADCs, stemming from their operating principles, poses challenges when integrating them with multisampling methods. This paper analyzes the integration of multisampling techniques with SD-ADCs for medium-voltage CHB converter control. First, the impact of SD-ADC-induced delays on the control system is elucidated from the passivity perspective. Second, the practical implementation of multisampling with SD-ADCs is discussed in detail. Finally, experimental results from a 2400 Vrms medium-voltage CHB converter are presented to validate the analysis and illustrate the effectiveness of the proposed implementation.

Design and Implementation of a Smart AC Current Source for Impedance Spectroscopy Using ARM Microcontrollers

This paper explores the development of a low-cost alternating current (AC) smart current generator using ARM Cortex-M33 microcontrollers with integrated peripherals, Digital to Analog Converters (DAC) and Operational amplifiers (OPAMPS). The system generates an AC voltage signal through the DAC, which is then converted to an AC using integrated operational amplifiers and passive components. The proposed design provides a compact, low-power, cost-effective solution which is suitable for optimized embedded system sensor design. Results show a signal-to-noise ratio (SNR) of up to 70 dB and a total harmonic distortion (THD) as low as 0.2%, illustrating the potential for advanced sensing applications.

All-optical digital-to-analog conversion based on pulse walk-off effect

A novel approach for all-optical digital-to-analog conversion (DAC) based on the pulse walk-off effect is proposed and experimentally demonstrated. In this approach, an ultrafast optical pulse train is firstly spectrum-tailored by a spectrum-shaper to achieve the multi-wavelength pulses, serving as the sampling source for carrying serial input digital signals via intensity modulation. These modulated optical signals are then injected into a dispersion medium to introduce multi-wave pulse walk-off. Consequently, the modulated optical signals partially overlap in the time domain and the incoherent weighted intensity summation can be realized. The following intensity modulator driven by the selecting codes extracts the target signals in the right time slots. The proposed approach features all-optical structure, inter-channel error avoidance, and high conversion rate, offering a promising solution for achieving high-performance photonic DAC. A proof-of-concept experiment of a 3-bit DAC system with a conversion rate of 5 Gbps based on the pulse walk-off effect has been successfully carried out. Additionally, the system’s performance in terms of Effective number of bits (ENOB) versus modulator extinction ratio and dispersion fluctuations is also discussed in detail.

A power‐saving control voltage‐retention circuit for fast‐locking phase‐locked loops with sleep mode

AbstractThis study proposes a voltage‐retention circuit (VRC) for a low‐power phase‐locked loop (PLL) designed for mobile interfaces. The PLL, incorporating the proposed scheme, supports the sleep mode to achieve low power consumption and fast switching between the sleep and active modes. To facilitate rapid switching between these modes, the proposed VRC stores the filter information from the previous input during sleep mode, ensuring quick settling upon reactivation. The VRC comprises a resistor‐steering digital‐to‐analog converter (DAC), a comparator, and a counter. During the active mode, the circuit adjusts the DAC using the comparator and counter to track the loop‐filter voltage, and it holds the tracked voltage value during the sleep mode. The proposed circuit, designed using a 65‐nm CMOS process, demonstrates 54% improved settling time compared to conventional circuits. Additionally, it reduces power consumption during sleep mode by 88%.

Study and application of bridge circuit based on ratio method

Abstract A new high-precision bridge circuit based on the ratio method is proposed to solve the requirements of high-precision resistance measurement for resistive sensors. The bridge circuit based on the ratio method of the ADC’s digital output is the ratio of the ADC’s analog input voltage and reference voltage, using unbalanced bridge output which is amplified as the analog input of ADC, also using differential voltage of another bridge arm of the same side as the reference voltage of ADC, after analog-digital conversion the ADC’s digital output as the system output. Achieving the resistance signal and the output of the bridge circuit has a strictly linear relationship, overcoming the supply voltage fluctuations has a great impact on the resistance measurement results, and eliminating the system’s zero drift and temperature drift is reached, so the bridge circuit has a better high-precision performance of resistance measurement.

Development of AI‐4‐AD tools for evaluation and prognosis of AD conversion: multi‐branch network and multi‐task deep learning algorism

AbstractBackgroundAD prevention and early interventions require tools for evaluation of people during aging for diagnosis and prognosis of AD conversion. Since AD is a complicated continuum of neurodegenerative processes, developing of such tools have been difficult because it needs longitudinal and multimodal data which are often complicated and incomplete. To address this challenge, we are developing AI4AD framework using ADNI data.MethodAs shown in Fig. 1, we used the multimodal features of subjects in the initial four time points to predict the disease status after 1.5 years. The informative feature set with available multi‐modal data (MRI, PET and cognitive score (CSs)), is extracted as a multivariate time series. Then, a multi‐scale local temporal attention network (MCLAN) is constructed to extract corresponding deep features from three categories of multivariate time series respectively. Furthermore, a set of statistical features are extracted from multivariate the time series. Subsequently, fusion of selected deep features, statistical features and background knowledge (demographics, CSF, genetics feature) at baseline are performed using a DL feature network. Finally, AD and CSs predictions are realized utilizing multi‐task DL algorism with Adam optimization algorithm and the five‐fold cross‐validation method. 190 CN subjects, 347 MCI subjects and 20 AD subjects were selected according to the first visit diagnosis from TADPOLE database (Table 1a). The longitudinal data for training and ground truth of AD conversion are shown in Table 1(b).ResultThe accuracy (ACC), accuracy (PRE), recall (REC) and F1 score of the proposed AD prediction method in the AD classification were 93.57%, 93.55%, 93.68%, and 93.59%, respectively, which is greatly improved the predictive ability of those by the conventional methods (Table 2). In addition, the root mean square error (RMSE) on the CSs prediction of CDRSB, ADAS11, ADAS13 and MMSE are 0.5863, 0.5238, 0.4747 and 0.5417 respectively.ConclusionOur DL method consolidates multi‐modal medical information at different visits to predict the disease’s progression, which greatly improved AD prognosis from those using traditional DL algorithms (CNN, LeNet and ResNet). The AI4AD framework proposed here can also be tailored to other diseases with similar data characteristics.

An Imaging Marker for MCI to AD Conversion: Functional Dysconnectivity between Primary Olfactory Cortex to Default Mode Network

An Imaging Marker for MCI to AD Conversion: Functional Dysconnectivity between Primary Olfactory Cortex to Default Mode Network

An Imaging Marker for MCI to AD Conversion: Functional Dysconnectivity between Primary Olfactory Cortex to Default Mode Network

An Imaging Marker for MCI to AD Conversion: Functional Dysconnectivity between Primary Olfactory Cortex to Default Mode Network

Optimal Feedback Rate for Multi-Antenna Maximum Ratio Transmission in Single-User MIMO Systems with One-Bit Analog-to-Digital Converters in Dense Cellular Networks

Stochastic geometry has emerged as a powerful tool for modeling cellular networks, especially in dense deployment scenarios where inter-cell interference is significant. Previous studies have extensively analyzed multi-antenna systems with partial channel state information at the transmitter (CSIT) using stochastic geometry models. However, most of these works assume the use of infinite-resolution analog-to-digital converters (ADCs) at the receivers. Recent advances in low-resolution ADCs, such as one-bit ADCs, offer an energy-efficient alternative for millimeter-wave systems, but the interplay between limited feedback and one-bit ADCs remains underexplored in such networks. This paper addresses this gap by analyzing the optimal feedback rate that maximizes net spectral efficiency in dense cellular networks, modeled using stochastic geometry, with both limited feedback and one-bit ADC receivers. We introduce an approximation of the achievable spectral efficiency to derive a differentiable expression of the optimal feedback rate. The results show that while the scaling behavior of the optimal feedback rate with respect to the channel coherence time remains unaffected by the ADC’s resolution, the absolute values are significantly lower for one-bit ADCs compared to infinite-resolution ADCs. Simulation results confirm the accuracy of our theoretical approximations and demonstrate the impact of ADC resolution on feedback rate optimization.

Rapid digital background calibration of bit weights in pipelined SAR ADC based on multi-PN injection

This brief presents a digital background calibration technique based on a dual-comparator architecture, aimed at addressing capacitor mismatch, residual gain error, and residue amplifier (RA) nonlinearity in pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs). Although numerous reports have documented bit weight calibration in pipelined SAR ADCs, none have been comprehensive, with op-amp nonlinearity never previously addressed. For the first time, we also consider and resolve the randomness issue of PN sequences following window sampling. Behavioral simulation results demonstrate the effectiveness of this technique, with the SNDR and SFDR performance of a 12-bit two-stage pipelined SAR ADC improving from 52.2 dB and 65.5 dB to an average of 68.8 dB and 91.0 dB, respectively. The convergence speed of this calibration algorithm is 0.6M samples, outpacing all previously published bit weight calibration works.