Analog-to-digital Converter Design Research Articles

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC.

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio.

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively.

Advancing precision in pipeline analog-to-digital converters: Leveraging MATLAB for design and analysis in next-generation communication systems

The integration of MATLAB in designing and analyzing pipeline Analog-to-Digital Converters (ADCs) addresses the complexities of next-generation communication systems. This study reviews literature to identify trends and challenges in high-speed ADC designs. Mastery of MATLAB and its toolboxes, like Simulink and Signal Processing, is essential for advanced ADC modeling and analysis. Key challenges include maintaining accuracy with diminishing supply voltages in modern semiconductors. The study explores incorporating high-voltage analog components and develops strategies for superior accuracy using low-voltage transistors. MATLAB and pipeline architecture are crucial for advancing ADC design, providing innovative solutions for next-gen communication systems.

Study on low power ADC Design using Memristor on Embedded systems

As portable and battery-operated devices become more common, embedded systems must meet the highest standards for low power consumption. Conventional analog-to-digital converters (ADCs) add a substantial amount of power to these systems overall. The design and application of low power ADCs using memristor technology are examined in this work. Memristors present a viable substitute for traditional ADC components because of their high density and non-volatile memory capabilities. Through the utilization of memristors' special qualities—like their low voltage operation and powerlessness—this research attempts to create ADC architectures with much lower power consumption. The suggested design creates a small, effective, and power-saving solution by integrating memristors in the analog front end and digital processing stages of the ADC. According to experimental results, memristor-based ADCs can save a significant amount of power without sacrificing performance, which makes them perfect for next-generation embedded systems applications. By advancing the design of energy-efficient embedded systems, this study may prolong the lifespan of portable electronics and open up new applications in wearable and Internet of Things (IOT) technologies.

Design and Analysis of 16-bit pipelined subranging SAR ADC and TDC

Analog to digital converters plays an important role in medical and signal processing applications. This paper proposes a 16-bit time based analog to digital converter (ADC) architecture by combining SAR Analog to Digital Converter and Vernier Time to Digital Converter. SAR analog to digital Converter is best suited for low power, high resolution and moderate applications. Vernier Time to Digital Converter with a high resolution to increase the conversion gain of VTC. The SAR ADC and Vernier TDC are pipelined to increase the conversion speed and reduce the area, power dissipation significantly smaller. A 16-bit combined pipelining SAR ADC and Vernier TDC was designed and simulated in Tanner EDA Tool.

Design of Low Power SAR ADC with Novel Regenerative Comparator

This paper introduces two low-power design techniques for a successive approximation register (SAR) analog-to-digital converter (ADC) used in transmitting physiological signals. The first technique is called dual split switching, involving the use of a one-sided charge-scaling digital-to-analog converter (DAC) to minimize switching energy by reducing leakage in a dual transmission gate. The second technique, known as the set and reset phase, determines the amplification and comparison phases of the comparator. This approach reduces the delay time of the comparator through the use of a folded cascode pre-amplifier and a regenerative latch. The design includes a Serial-in-Parallel-Out (SIPO) N-bit register and SAR, implemented using negative edge-triggered D flip-flops (DFFs). To optimize power consumption, the supply voltage of the SAR ADC is set to 500 mV. The concept of a variable threshold is utilized throughout the design to enable operation with this lower supply voltage. The SAR ADC is designed to support a sampling rate of up to 1 Msps (mega-samples per second). The circuit is implemented using standard UMC180nm technology. According to the test results, the power consumption of the SAR ADC is only 29.06 uW, and the achieved sampling rate is 5 Ksps (kilo-samples per second). The maximum differential non-linearity (DNL) is measured to be +0.9/−0.82 least significant bits (LSBs).

Wavelet decomposition and reconstruction-based INL method for testing high-precision ADC

In traditional analog-to-digital converter (ADC) linearity testing, the cost of testing escalates in tandem with the increase in ADC resolution. This research proposes a time-efficient method for testing the integral nonlinearity (INL). Drawing on the wavelet decomposition and reconstruction technique in conjunction with sine wave histogram, our approach facilitates swift and accurate testing of high-precision ADC linearity compared to conventional methods. Our approach acquiring the initial INL result by sampling the sinusoidal histogram using a modest number of samples. Subsequently, we employ wavelet decomposition to break down the initial result into high-frequency and low-frequency portions. Setting thresholds for these components and reconstruct them to derive an accurate INL result. Experimental findings demonstrate that our proposed method effectively enhances the accuracy of high-precision ADC linearity testing. Furthermore, it reduces the linearity testing time by over tenfold and diminishes estimation errors by more than 30%. Consequently, our method establishes a more dependable means of testing for ADC design and manufacturing.

A Bit-Serial, Compute-in-SRAM Design Featuring Hybrid-Integrating ADCs and Input Dependent Binary Scaled Precharge Eliminating DACs for Energy-Efficient DNN Inference

The major challenge faced by modern compute-in-memory (CIM) designs is that they rely heavily on mixed-signal data converters such as digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) that contribute to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 15% area and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim$</tex-math> </inline-formula> 50% energy of the overall macro and are susceptible to non-linearities, leakage, and process variations, which causes deep neural network (DNN) inference/training accuracy loss. As DNN models increase in size, the number of DACs steps required per inference increases exponentially. This work proposes a four-pronged approach to address the challenges in CIM designs: 1) binary-weighted-bitline-precharge scheme utilizing dedicated reference voltages to perform input bit-serial multiplication in the charge domain, eliminating the need for dedicated DAC circuits; 2) leakage-tolerant, input-dependent-bitline-keeper circuits that maintain the local-bitline voltages; 3) hybrid-charge-sharing-based integrating-ADCs to improve the ADC conversion time by leveraging the reference voltages, thereby improving ADC latency while achieving a compact ADC design; and 4) efficient data movement and utilization of analog-to-digital co-computation. Fabricated in TSMC 65 nm, the experimental results for the compute-in-static-RAM (CISRAM) silicon prototype show an average macro energy efficiency of 153–2453.76 TOPs/W. The average macro energy efficiency is 2.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> more than the latest state of the art mentioned in the comparison table.

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

This article details the design and measurement of a digital-to-analog converter (DAC)-based source-series terminated (SST) transmitter (TX) for wireline applications in 4-nm FinFET CMOS technology. The DAC achieves 8-bit resolution and high analog output bandwidth by using a segmented architecture along with a single-ended LSB. Strength adjustment of the lower four DAC LSBs relative to the upper four DAC MSBs is accomplished with a hybrid analog/digital tuning approach, which overcomes minimum device-size limitations that can limit the effectiveness of pure digital tuning for SST drivers. The resulting DAC design achieves well-matched MSB/LSB segments with −0.63/0.67 LSB integral nonlinearity (INL) and −0.16/0.43 LSB differential nonlinearity (DNL). Time-domain modulation of 216-Gb/s PAM8 and frequency-domain modulation of 212-Gb/s orthogonal frequency-division multiplexing (OFDM) are reported, demonstrating the capability of CMOS DACs to support frequency-domain modulation for wireline applications. The TX consumes 288 mW from a 0.95-V power supply.

180 nm FLASH ANALOG TO DIGITAL CONVERTOR

In this paper, Threshold Inverter Quantizer (TIQ) is a novel idea which can effectively replace the reference voltage generator, resistive/capacitive voltage divider network and array of differential comparators in a conventional flash Analog to Digital Converter (ADC) by an internal reference comparator array constructed of Complementary Metal Oxide Semiconductor (CMOS) inverters. The inverter threshold voltage serving as the reference voltage, this architecture claims large improvements in terms of silicon area, power consumption and operating speed. Perturbations due to sensitivity of the inverter threshold voltage to operating temperature/process variations pose impediments in such ADC designs and strongly demand a compensation scheme to such variations. This paper presents a TIQ based flash ADC, with inverter threshold voltage compensation. In this project 5 bit flash adc using TIQ Comparator is designed and simulated using TANNER EDA in 180nm technology. Key Words: flash, adc, tiq(threshold inverter quantization)

High-Speed Fully Differential Two-Step ADC Design Method for CMOS Image Sensor

The application requirements of high frame rate CMOS image sensors (CIS) in the industry have not been satisfied due to the speed limitations in traditional single-slope and serial two-step analog-to-digital converters (ADCs). In this paper, a high-speed fully differential two-step ADC design method for CIS was proposed. The proposed method was based on differential ramp and time-to-digital conversion (TDC) technology. A parallel conversion mode was formed that is different from serial conversion, and the robustness of the system was ensured due to the existence of differential ramps. Aiming at the inconsistency between traditional TDC technology and single-slope ADC, a TDC technology based on level coding was proposed. The proposed technology achieves the TDC in the last clock cycle of analog-to-digital conversion, and realized a two-step conversion process at another level. This paper presents a complete circuit design, layout design, and test verification of the proposed design method based on the 55 nm 1P4M CMOS experimental platform. Under the design environment of the analog voltage of 3.3 V, the digital voltage of 1.2 V, the clock frequency of 100 MHz, and a dynamic input range of 1.6 V, this design was a 12-bit ADC with a conversion time of 480 ns, column-level power consumption of 62 μW, differential nonlinearity (DNL) of +0.6/-0.6 LSB, and integral nonlinearity (INL) of +1.2/-1.4 LSB. Furthermore, it achieved a signal-to-noise distortion ratio (SNDR) of 70.08 dB. The proposed design provided a large area array with a high frame rate, and compared with the existing advanced single-slope ADC, its conversion speed increased by more than 52%. It provides an effective solution for the implementation of high frame frequency CIS.

A novel capacitor recombination calibration method applied to 18-bit SAR ADC

In this paper, a calibration method applied to Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) is designed, especially applied to the capacitive array in resistive–capacitive combined SAR ADC. Conventionally, auxiliary Digital-to-Analog Converter (DAC) foreground calibration, dynamic element matching (DEM) or digital background calibration are widely used to enhance linearity of data converters. This paper proposes an off-line capacitor selection calibration method that uses an optimal sequence of unity elements for an overall improvement of Signal to Noise and Distortion Ratio (SNDR), Spurious-Free Dynamic Range (SFDR), differential nonlinearity (DNL) and integral nonlinearity (INL). It is worth mentioning that the capacitor mismatch only needs to be calibrated after power on, this kind of foreground calibration will not increase the power consumption of ADC during the normal operation, while the background calibration will consume power consumption all the time. It is important that the calibration proposed is highly relied on a high resolution comparator. This paper provides a high resolution comparator design, the resolution of the comparator reaches 8.35 μV, which already satisfies the demand of a 18-bit differential SAR ADC. During the process of calibration, all capacitors are divided into unit capacitors, and then the capacitors are sorted, reorganized to form each bit. The calibration method is verified by simulating a 18-bit SAR ADC with 500 Monte-Carlo runs, the simulation results show that the average value of SFDR is enhanced by about 36 dB and the average value of SNDR is enhanced by about 27 dB. Therefore, the proposed method is simple and significantly improves the static and dynamic performance of the ADC without obvious additional hardware, and greatly saves area and power consumption. Finally, it is worth mentioning that in high-precision SAR ADCs design, especially above 16 bits, comparator noise and the voltage coefficient of capacitors are the main factors limiting ADC performance, which are not considered in this work.

Low Area and High Bit Resolution Flash Analog to Digital Converter for Wide Band Applications: A Review

: This work reviews the design challenges of CMOS flash type Analog-to-Digital Converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter (DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

Echo Signal Receiving and Data Conversion Integrated Circuits for Portable High-Frequency Ultrasonic Imaging System.

Ultrasonic imaging has become a very promising technology, and it has been widely applied in biomedicine, geology, and other fields due to its advantages of safety, nondamaging, and real time. Especially, the portable high-frequency (>20 MHz) ultrasonic imaging system (UIS) has been generally used in biomedical detection and diagnosis. In the complex actual environment, the effect of integrated circuits (ICs) on the performance of portable high-frequency UIS is obvious. In the echo signal transmission link, the analog front end (AFE) and the analog-to-digital converter (ADC) are the two most critical modules, where AFE is used to receive and preprocess the analog ultrasonic echo signals and ADC to convert the analog signals from the AFE output to digital. The structure and performance of the ICs integrated into terminal equipment and in-probe for the portable high-frequency UIS are introduced and discussed. Some typical commercial ICs are also summarized. Based on the requirements and challenges of portable high-frequency UIS, the future development directions of ICs mainly include high integration, ultralow power consumption, high speed, and high precision, which can provide valuable reference and advice for the design of AFE and ADC for portable high-frequency UIS.

Low-Power SAR ADC Design: Overview and Survey of State-of-the-Art Techniques

This paper presents an overview for low-power successive approximation register (SAR) analog-to-digital converters (ADCs). It covers the operation principle, error analysis, and practical design issues. Furthermore, this paper provides a comprehensive survey of state-of-the-art low-power design techniques for every circuit block in the SAR ADC, including comparator, capacitive digital-to-analog converter (DAC), and SAR logic. The goal of this paper is to provide a useful overview to SAR ADC designers who want to improve the energy efficiency targeting low-to-medium speed applications.

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs

Conventional von Neumann architectures cannot successfully meet the demands of emerging computation and data-intensive applications. These shortcomings can be improved by embracing new architectural paradigms using emerging technologies. In particular, Computation-In-Memory (CiM) using emerging technologies such as Resistive Random Access Memory (ReRAM) is a promising approach to meet the computational demands of data-intensive applications such as neural networks and database queries. In CiM, computation is done in an analog manner; digitization of the results is costly in several aspects, such as area, energy, and performance, which hinders the potential of CiM. In this article, we propose an efficient Voltage-Controlled-Oscillator (VCO)–based analog-to-digital converter (ADC) design to improve the performance and energy efficiency of the CiM architecture. Due to its efficiency, the proposed ADC can be assigned in a per-column manner instead of sharing one ADC among multiple columns. This will boost the parallel execution and overall efficiency of the CiM crossbar array. The proposed ADC is evaluated using a Multiplication and Accumulation (MAC) operation implemented in ReRAM-based CiM crossbar arrays. Simulations results show that our proposed ADC can distinguish up to 32 levels within 10 ns while consuming less than 5.2 pJ of energy. In addition, our proposed ADC can tolerate ≈30% variability with a negligible impact on the performance of the ADC.

A novel noncoupling capacitor split capacitor array structure for high resolution SAR ADC

In order to achieve high resolution in Successive Approximation Register (SAR) Analog to Digital Converter (ADC), a novel noncoupling capacitor split capacitor array structure is proposed, which solves the coupling capacitor mismatch problem in the traditional split capacitor array structure. This paper analyzes the structure and its capacitor array mismatch. Based on the structure and analysis, a 12-bit SAR ADC is designed and implemented in GSMC 0.11 [Formula: see text]m CMOS process. The measured results show that the Signal to Noise Ratio (SNR) is 72.61 dB and Effective Number Of Bits (ENOB) is 11.77 bit, which prove the advantages of this structure in the design of high resolution SAR ADC.

Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

A Folding Approach for Multiple Antenna Arrays Using Low-Resolution ADCs

Both massive multiple-input multiple-output (MIMO) and millimeter wave (mmWave) systems are receiving much attention for 5G and beyond-5G wireless access. When using a large antenna array, there are numerous challenges in designing low-power and cost-effective hardware. Most notably, the traditional approach of using high-resolution analog-to-digital converters (ADCs) at each element leads to both costly and high-power consumption devices. This has motivated research on multiple antenna arrays that use a low-resolution ADC at each element. We present a new framework for designing a multiple antenna array using a low-resolution ADC at each element, with the low-resolution ADC composed of simple shift and modulo analog processing and a sign quantizer. This modulo technique, called folding, has previously been utilized in the design of high-speed high-resolution ADCs. Using theory from folded ADCs, we show how to jointly design the modulo processing used across the elements. We show that our framework can provide substantial rate improvements including providing a linear growth in rate with the number of antennas at high SNR, as opposed to the logarithmic growth with the number of antennas provided by a sign-based low-resolution ADC array. We also explore how antenna ordering strategies can be used. We utilize Monte Carlo simulations to back our analysis.