Analog-to-digital Converter Power Research Articles

A 1.5 mm2 4-Channel EEG/BIOZ Acquisition ASIC With 15.2-Bit 3-Step ADC Based on a Signal-Dependent Low-Power Strategy.

This article presents a multichannel EEG/BIOZ acquisition application specific integrated circuit (ASIC) with 4 EEG channels and a BIOZ channel, a switch resistor low-pass filter (SR-LPF). Each EEG channel includes a frontend, and a 4-channel multiplexed analog-to-digital converter (ADC), while the BIOZ channel features a pseudo sine current generator and a pair of readout paths with multiplexed SR-LPF and ADC. The ASIC is designed for size and power minimization, utilizing a 3-step ADC with a novel signal-dependent low power strategy. The proposed ADC operates at a sampling rate of 1600 S/s with a resolution of 15.2 bits, occupying only 0.093 mm2. With the help of the proposed signal-dependent low-power strategy, the ADC's power dissipation drops from 32.2 μW to 26.4 μW, resulting in an 18% efficiency improvement without performance degradation. Moreover, the EEG channels deliver excellent noise performance with a NEF of 7.56 and 27.8 nV/√Hz at the expense of 0.16 mm2 per channel. In BIOZ measurement, a 5-bit programmable current source is used to generate pseudo sine injection current ranging from 0 to 22 μApp, and the detection sensitivity reaches 2.4 mΩ/√Hz. Finally, the presented multichannel EEG/BIOZ acquisition ASIC has a compact active area of 1.5 mm2 in an 180nm CMOS technology.

Massive MIMO Systems with Low-Resolution ADCs: Achievable Rates and Allocation of Quantization Bits

In massive multiple-input multiple-output (MIMO) systems, the large number of high-resolution analog-to-digital converters (ADCs) lead to high hardware cost and power consumption. In this work, the uplink achievable rates of massive MIMO systems with low-resolution ADCs are studied with consideration of both “Uniform-ADC” that uses ADCs with the same number of quantization bits and “Mixed-ADC” that allows the use of ADCs with different resolutions. By leveraging an additive quantization noise model (AQNM), the asymptotic achievable rates are obtained for maximum ratio combining (MRC), zero-forcing (ZF), and linear minimum mean squared error (LMMSE) receivers in very simple forms. Taking advantages of the theoretical results, we propose two criteria for allocation of quantization bits. It is found that the optimal quantization bits allocation for LMMSE is Mixed-ADCs with number of quantization bits that are polarized, while Uniform-ADC is optimal for MRC and ZF. When there is a constraint on the total ADC power consumption, the proposed quantization-bit allocation scheme for LMMSE becomes Uniform-ADC when the transmit signal-to-noise ratio (SNR) is below a threshold, which is related to the system scale and the ADC power consumption. The theoretical results are verified by Monte-Carlo simulations.

A Large-Swing High-Linearity Fully-Dynamic Amplifier With Automatic Calibration

In high-speed pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs), the residue amplifiers dominate the overall ADC speed, power, and accuracy. To improve the ADC performance, this brief proposes a large-swing high-linearity fully-dynamic open-loop amplifier. By setting the cascode input transistors in linear region, both the input/output swing and the linearity are improved significantly. By clamping the drain voltages of input transistors, the amplifier gain is PVT insensitive. These drain voltages of input transistors are clamped through a dynamic comparator with small size, which helps save energy. The comparator offset is automatically canceled out through a novel thermal-noise-based technique. Designed in a 40nm CMOS process, the proposed amplifier achieves an output swing of 400mVpp, a settling accuracy of 8-bit ENOB, and a voltage gain of 16X, under a 100MHz clock frequency. It is fully-dynamic and only consumes 1.15mW of power under a 1.1V supply. Compared to the state-of-the-art dynamic amplifiers, the output swing is increased by 4 times; the settling accuracy is improved by 2 bits; the voltage gain is increased by 4 times; the PVT sensitivity of voltage gain is reduced by 4.7 times; and the power consumption is decreased by 45% with fully-dynamic operation.

A Wireless Headstage System Based on Neural-Recording Chip Featuring 315 nW Kickback-Reduction SAR ADC.

Wireless neural-recording instruments eliminate the bulky cables in multi-channel signal transmission, while the system size should be reduced to mitigate the impact on freely-moving animals. As the battery usually dominates the system size, the neural-recording chip should be low power to minimize the battery in long-termly monitoring. In general, a neural-recording chip consists of an analog front end (AFE) and an 8 bit -10 bit analog-to-digital converter (ADC), while it's challenging to design an ADC with an 8 -10 effective number of bits (ENOB) and sub- μ W power consumption due to the kickback noise. In this work, we propose a kickback-reduction technique for a successive-approximation-register (SAR) ADC based on neural-recording chip. Fabricated in 65 nm CMOS process, the proposed technique reduce the ADC power to 315 nW, resulting in an 8-channel neural-recording chip with 249 μW in total. Measured results show that the chip achieves an ADC ENOB of 9.73 bits, as well as an AFE gain of 43.3 dB and input-referred noise (IRN) of 9.68 μVrms in a bandwidth of 0.9 Hz -7.2 kHz. Combined with a BLE chip and a PCB antenna, the chip is implemented into a 2.6 g wireless headstage system (w/o battery), and an in-vivo demonstration is conducted on a male Sprague-Dawley rat with Parkinson's disease. The headstage system transfers the in-vivo neural signals to a commodity smartphone through BLE, and the miniature size induces little impact on freely-moving activities.

CODEX: Stochastic Encoding Method to Relax Resistive Crossbar Accelerator Design Requirements

A stochastic input encoding scheme (CODEX) is presented that aims to relax the analog-to-digital converter (ADC) design requirements in memristor crossbar systems. CODEX reduces the ADC input range by encoding the input bits using Bernoulli statistics so that the bit-line current distribution becomes a narrow Gaussian. By reducing ADC input range, CODEX can be used to reduce ADC power and area or increase ADC resolution to reduce the number of epochs required for in-situ training. Besides input data encoding, CODEX includes probability thresholding for sparse input data as well as a random re-sampling method for dealing with ADC overflow. CODEX is evaluated on CIFAR-10 dataset image classification and reconstruction, sentiment classification, and audio classification. The results show an averaged 68.5% reduction in ADC power, 35.5% reduction in ADC area, and 25.8% reduction in training epochs required for in-situ training when applied to the state-of-the-art ISAAC and PUMA accelerators.

Low power consumption detectors for mmWave massive MU-MIMO-GFDM systems

ABSTRACT The International Mobile Telecommunications-2020 (IMT-2020) specifies the data rates for enhanced mobile broadband (eMBB) is approximately 10 Gb/s. Millimetre-wave (mmWave) has a vast spectrum and can be used with only slight authorisation, making it an ideal solution for eMBB. This paper proposes optimal detectors with low cost, low power consumption, and low complexity for mmWave massive multi-user multiple-input multiple-output (MU-MIMO) communication. The mmWave broadband communication faces many challenges in system implementation. One of the challenges of mmWave broadband systems is using the analog-to-digital converter (ADC) in the receiver. The ADC power consumption will significantly increase with the frequency bandwidth. The ADC power consumption will also considerably increase with the bit number used in the conversion simultaneously. The mmWave broadband communication also challenges the cost of transmitters, especially wideband linear amplifiers are costly. Hence, it is necessary to transmit a signal with a low peak-to-average power ratio (PAPR) to relax the linearity of the power amplifier. The radio-frequency (RF) port connects to two high-precision ADCs in conventional MIMO systems. Scaling such architectures to massive multiple-input multiple-output (MIMO) with hundreds or thousands of active antenna elements would lead to excessive-high power consumption and hardware costs. Hence, this paper proposes optimal detections for massive multi-user (MU) MIMO-GFDM communications with coarse quantisation. It achieves substantial cost and power savings and provides a high system capacity. The optimal detections for coarse quantisation in large-scale MU-MIMO-GFDM systems have minimal capability loss compared with the ideal case. There is no additional base-band processing complexity. The simulation results show that the SNR gap between the second mismatched quantiser and the precise quantiser is small. When the ratio of receiving and transmitting antennas is the same, the larger the number of antennas, the smaller the SNR difference between the second mismatch quantiser and the precise quantiser.

Low Bit-Depth ADCs for Multi-bit Quanta Image Sensors

A 1024 $\times $ 896 test chip is presented in this article to explore a low-power readout circuit for a multi-bit quanta image sensor (QIS). Five well-known analog-to-digital converter (ADC) approaches [flash, pipeline, successive approximation register (SAR), cyclic, and single-slope (SS)] are studied, and two types of ADCs, namely, SAR ADCs and SS ADCs, are implemented in the sensor. The ADC power dissipations are compared under the condition of constant imaging throughput in counting photoelectrons. In QIS devices, one LSB corresponds to one photoelectron. Measurement results show that the power consumption of SAR ADC is better than that of the SS ADC and decreases by a factor of 17 when the resolution is changed from 1 b to 6 bits. By contrast, the power consumption of the SS ADCs decreases by a factor of 2.5. Thus, SAR ADCs seem more suitable for use in low-power multi-bit QIS.

A Design of 44.1 fJ/Conv-Step 12-Bit 80 ms/s Time Interleaved Hybrid Type SAR ADC With Redundancy Capacitor and On-Chip Time-Skew Calibration

A 12-bit 80 MS/s hybrid type analog-to-digital converter (ADC) for high sampling speed and low power applications is presented in this paper. It has a subranging architecture with a front end of 6-bit Flash ADC with five channels of 6-bit time interleaved synchronous Successive Approximation Register (SAR) ADC. The proposed architecture with a shared 6-bit Flash ADC and time interleaved SAR ADC provides a power and area efficient high speed ADC. The proposed Time-skew calibration is implemented to minimize the discrepancy between the output of Flash ADC and SAR ADC’s channels. To rectify the decision error of the Flash ADC and extract the time-skew information, 1-bit redundancy is included in the CDAC of the SAR conversion. The decision error between the Flash ADC and the SAR ADC is covered with designed redundancy and the mismatch between the ADCs is covered with the time-skew calibration. To reduce the offset mismatch between Flash and SAR ADC and within SAR ADCs, all comparators are calibrated to minimize their absolute offset by utilizing background offset calibration. The modified dynamic strong ARM comparator is used for flash ADC and dynamic latched comparator is used for SAR ADCs. For fine offset calibration and low power consumption, the comparator’s offset calibration circuit is implemented. To reduce the kickback noise and enhance the overall energy efficiency for fast operation of SAR ADCs, rail-to-rail dynamic latch comparator with modified adaptive power control (APC) is implemented. The proposed ADC structure has been implemented in 130 nm CMOS process. The ADC has an effective number of bit (ENOB) of 10.97 bits while consuming 7.08 mW current consumption from the 1.2 V supply voltage.

Dynamic ADC Resolution-Mapping for Millimeter-Wave Massive MIMO Systems

The radio-frequency (RF) chains, phase shifters (PSs), and analog-to-digital converters (ADCs) play the dominant role of power consumption in the uplink hybrid millimeter-wave (mmWave) massive multiple-input multiple-output (MIMO) networks. To mitigate power consumption, an energy-efficient switch and inverter (SI) based partially-connected (PC) architecture with the Gram-Schmidt (GS) antenna selection strategy is addressed. The design of a variable-resolution ADC configuration is addressed under an independent upper bound of power consumption for each ADC in this paper. However, the resulting ADC resolution mapping becomes more complicated due to variant ADC power bounds. A simple ADC bit-allocation algorithm, namely, the sum-resolution (SR) ADC, is proposed. By replacing the total power constraint on ADCs to improve both the achievable sum-rate (ASR) and energy efficiency (EE) performance of the hybrid mmWave massive MIMO system. The SR-ADC solutions in closed form reveal that the optimal ADC resolution is proportional to the square power of the signal-to-noise ratio (SNR) in RF chains. Simulation results demonstrate that the proposed SR-ADC approach offers enhanced improvements on the ASR and EE, and exhibits prominent advantages on the number of activated RF chains compared with the fixed total power system.

A 7-bit 2 GS/s Time-Interleaved SAR ADC With Timing Skew Calibration Based on Current Integrating Sampler

This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rd</sup> Nyquist zone. The converter's front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers' inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC's power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step.

A Successive Approximation Register Analog to Digital Converter for Low Power Applications

In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less die area poses a stringent requirement in designing and fabricating an ultra-low power ADCs. Among the diverse converter architectures existing, Successive Approximation Register (SAR) type converter architecture has shown better capabilities in terms of ultra-low power operation, medium resolution, less form factor and less silicon area. In this described paper a novel power effective, better resolution SAR type ADC to be used for biomedical related applications. The proposed work consists of capacitive type Digital to Analog Converter (DAC) based on charge distribution, a CMOS comparator, and SAR logic implemented using D-flip-flops. The different blocks of SAR architecture are simulated using EDA tools in CMOS 180 nm N-well process operated at VDD = 1.5 V voltage (VDD). The circuit is measured under various input frequencies with a sampling speed of 50 MHz and it consumes 22.6 μW. The proposed ADC technology shows SNDR of 48.6 dB and occupies a circuit area of 0.11 mm2 and the measured INL and DNL is calculated to be fewer than 0.54 LSB and 0.45 LSB respectively.

A Suggestive Low Power TIQ Comparator Architecture using Adiabatic Logic for Implementation of 3-bit Flash type ADC.

Power consumption is prime concern for the designers in modern day scenario. For the devices that are power-driven by tiny rechargeable or non-rechargeable batteries over the entire life period, such as medical transplant devices or portable medical instruments, necessitates lowest possible power consumption. In these devices Analog-to-Digital Converter (ADC) isdynamic component to provide connectionamongstAnalog and Digital system. The paper is aimed to report the design contests and tactics for low power ADCs which are used in biomedical graft devices and instruments. A comparator module of ADCs used in designing of such devices requires more power than other blocks in the device, a low power comparator is suggested for Threshold-Inverter-Quantizer (TIQ)usingDiode-Free-Adiabatic-Logic (DFAL) to implement Flash type ADCs. The projected 3-bit Flash ADC is simulated using Cadence ® Virtuoso IC616 with TSMC 65nm technology. The ADC was simulated atpeak to peak voltage of 1.2V andcapacitive load of 1fF,results in consumption of5.53 μW of average power, which is 66.03 % lesser relative toconservative CMOS-TIQ based comparator. Observed static parameters are: DNL is equal to-0.62 / + 0.57 LSB and INL is equal to- 0.44/ +0.41 LSB.Dynamic parameters observed results are as: THD = -25.25dB, SNR=19.45 dB, SNDR=18.39 dB, ENOB=2.76 bits, SFDR = 23.4 dB.

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS

The emergence of four-level pulse amplitude modulation (PAM-4) standards to increase data rates motivates the use of receiver front ends that utilize high-speed analog-to-digital converters (ADCs) followed by digital signal processing (DSP) to provide robust digital equalization. This paper presents an ADC-based PAM-4 receiver employing a 32-way time-interleaved, 2-bit/stage, 6-bit successive approximation register (SAR) ADC with a single capacitive reference digital-to-analog converter (DAC) and a digital equalizer consisting of a 12-tap feed-forward equalizer (FFE) and a two-tap decision-feedback equalizer (DFE). A new digital DFE architecture that reduces the complexity of a PAM-4 DFE to that of a binary non-return-to-zero (NRZ) DFE, while simultaneously nearly doubling the maximum achievable data rate, is presented. Partial analog equalization is provided in the receiver front end in the form of a programmable two-stage continuous-time linear equalizer (CTLE) and a three-tap FFE that is embedded in the ADC using a non-binary FFE DAC to improve the FFE coefficient coverage space. This partial analog equalization allows placement of the digital baud-rate clock and data recovery (CDR) system's Mueller-Muller phase detector directly at the ADC output to avoid excessive loop delay. Fabricated in GP 65-nm CMOS, the receiver achieves 32-Gb/s operation at a bit error rate (BER) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> with a 30-dB loss channel and 52-Gb/s operation at a BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> with a 31-dB loss channel without utilizing any transmit equalization. The complete ADC-based receiver achieves a 52-Gb/s power efficiency of 8.06 pJ/bit, including all the front end, ADC, and DSP power.

A 6.9-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC

In this paper, we report on a back-illuminated, global shutter, CMOS image sensor (CIS) with a pixel-parallel, single-slope analog-to-digital converter (ADC). We adopted a digital bucket relay transfer with multistage flip-flop connection, a pixel unit Cu–Cu connection, and positive-feedback circuitry, to realize a 6.9- $\mu \text{m}$ pixel-pitch, 1.46-Mpixel pixel-parallel ADC. By operating the comparator with a bias current in the subthreshold region of 7.74–111 nA, we succeeded in reducing the peak current during simultaneous ADC. In combination with an ADC standby operation, we succeeded in further reducing the pixel-parallel ADC power consumption. With these techniques, we realized a normalized figure of merit of 0.24 nJ $\cdot \text{e}-$ rms/step calculated by dividing the entire sensor power by the effective ADC resolution at a subthreshold current of 111 nA during 660 frames/s operation.

Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs Using a Memristive Neuromorphic Architecture

The analog-to-digital converter (ADC) is a principal component in every data acquisition system. Unfortunately, modern ADCs tradeoff speed, power, and accuracy. In this paper, novel neuroinspired approaches are used to design a smart ADC that could be trained in real time for general purpose applications and break through conventional ADC limitations. Motivated by artificial intelligent learning algorithms and neural network architectures, the proposed ADC integrates emerging memristor technology with CMOS. We design a trainable four-bit ADC with a memristive neural network that implements the online gradient descent algorithm. This supervised machine learning algorithm fits multiple application specifications such as full-scale voltage ranges and sampling frequencies. Theoretical analysis, as well as simulation results, demonstrate highly powerful collective properties, including reconfiguration, mismatch self-calibration, adaptation to dynamic voltage and frequency scaling, noise tolerance, and power consumption optimization. The proposed ADC achieves 8.25 fJ/conv FOM, 3.7 ENOB, 0.4 LSB INL, and 0.5 LSB DNL. These promising properties make it a leading contender for general purpose and emerging data driven applications.

A 18.5 nW 12-bit 1-kS/s Reset-Energy Saving SAR ADC for Bio-Signal Acquisition in 0.18-μm CMOS

This paper presents three low-power design techniques for successive approximation registers (SAR) analog-to-digital converter (ADC) for bio-potential signal acquisition: skip-reset, delta ( $\Delta$ ) readout with MSB-rounding, and tri-level split monotonic switching. The skip-reset scheme reduces not only reference energy but also digital switching energy for the ADC reset. The $\Delta$ -readout process with the proposed MSB-rounding technique shifts the location of the resolvable range using the previous digital code to increase the hit-rate. Finally, the tri-level split monotonic switching scheme minimizes the CDAC switching activity in predictive residue generation for the $\Delta$ -readout process. A prototype ADC was fabricated in a 0.18- $\mu \text{m}$ CMOS technology and occupies an active area of 0.17 mm2. At a 1.5-V supply voltage and a 1-kS/s sampling-rate with the electrocardiogram signal input, the ADC power consumption could be reduced to 18.5 nW, corresponding to 71% power saving, and owing to the proposed techniques from a conventional SAR ADC consuming 63.5 nW.

A 2.24-mW, 61.8-dB SNDR, 20-MS/s Pipelined ADC With Charge-Pump-Based Dynamic Biasing for Power Reduction in Op Amp Sharing

A high-speed dynamic biasing technique is presented for reducing op amp power in discrete-time, multistage, analog circuits employing op amp sharing. To exploit typical power scaling in such circuits, a charge pump, of which the on-times of up and down currents are controlled by two comparators, performs rapid change of the op amp bias condition between a low-current mode and a high-current mode during nonoverlapping clock periods of the two phase clocks. The errors caused by finite comparator delay are compensated for by embedding intentional offset voltages in the comparators, which are implemented by using asymmetric differential input pairs in the comparators. To verify the efficacy of the proposed biasing technique, an 11-b pipelined analog-to-digital converter (ADC) has been implemented using 0.15-μm devices in a 28-nm CMOS technology. With a 20-MHz sampling clock, the ADC achieves a 61.8-dB SNDR while consuming a 2.24-mW power from a 1.8-V supply. The MDAC and ADC power are reduced by about 45% and 30%, respectively, compared with a conventional pipelined ADC employing an op amp in each MDAC. Owing to the simple structure of the proposed dynamic biasing, the prototype ADC occupies only 0.052 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A 12-b, 650-MSps time-interleaved pipeline analog to digital converter with 1.5 GHz analog bandwidth for digital beam-forming systems

This paper presents the design of a very low power 12-bit 650-MSps time-interleaved pipeline analog-to-digital converter (ADC) for digital beam forming applications. A novel mixed-signal calibration technique is used to compensate for sample-time error between interleaved channels. A front-end sample-and-hold amplifier (SHA) is also designed as an alternative to demonstrate the effectiveness of the proposed technique. The ADC is designed in IBM BiCMOS 8HP 0.13 um. With the SHA the total power consumption of the ADC is 422 mW and SNDR of 65 dB is achieved up to 61 MHz of signal bandwidth. Using the proposed calibration scheme, there would be no need for SHA and the ADC power consumption is reduced to 335 mW in the normal operation of the ADC while SNDR is increased to 70.8 dB with the same input frequency. Simulation results also show that the proposed technique is able to improve the SNDR of a 12-bit time-interleaved ADC by 29 dB at 37 % of the Nyquist rate frequency.

A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization

While analog-to-digital converter (ADC)-based serial link receivers enable powerful digital equalization for high data rate operation, the ADC and digital equalization power consumption is a key concern in applications that support operation over a wide range of channels with varying amounts of intersymbol interference (ISI). This paper presents a hybrid ADC-based receiver architecture which employs a 3-tap analog feed-forward equalizer (FFE) embedded inside a 6 bit asynchronous successive approximation register (SAR) ADC and a per-symbol dynamically enabled digital equalizer, resulting in both reduced equalizer complexity and power consumption. Fabricated in general purpose (GP) 65 nm CMOS, the hybrid ADC-based receiver occupies $0. 81\; \text{mm}^{2}$ area. 10 Gb/s operation is verified for FR4 channels with up to 36.4 dB attenuation, with the proposed dynamic enabling of the digital 4-tap FFE and 3-tap decision feedback equalizer (DFE) on a per-symbol basis resulting in nearly 30 mW savings and an overall receiver power less than 90 mW.