Analog Signal Processing Systems Research Articles

An FPGA-based parallel deconvolution application envisaging high-energy calorimeters operating under severe pile-up conditions

Signal pileup may arise when the system response time is larger than what would be required by the event rate in the application. In this condition, information superposition occurs, and signal estimation is deteriorated due to such information distortion. For online applications, mitigating such a pileup distortion usually requires embedded digital signal processing, which often involves FPGA-based designs when high event rates are a concern. Recently, high-energy particle experiments started facing an unprecedented increase in pileup conditions, which demanded new approaches for signal estimation. This work proposes a dedicated parallel signal processing system embedded on an FPGA platform that implements different filtering techniques for online energy reconstruction in calorimeters (energy measurement) operating under severe pileup conditions. Each designed filter is an inverse approximation of the calorimeter readout channel's impulse response, performing deconvolution of the incoming signals. Such a deconvolution approach for energy estimation was recently introduced, and the proposed filters were implemented in this work. Evaluation of the digital system design was performed using a data set that considers a typical high-energy calorimeter front-end response, as high-luminosity particle collider experiments produce high pileup distortions in calorimeter signals when processing the subproducts of the collisions. As the Large Hadron Collider (LHC) provides the most demanding conditions in terms of signal pileup, the acquisition system of the proposed solution is synchronous with its collision rate (40 MHz). The results showed that the proposed implementation may be applied as a preprocessing (pileup reduction) step in calorimeter instrumentation and could reduce the signal pileup within the fast response time required by such experiments.

Electronically Tunable Grounded and Floating Capacitance Multipliers Using a Single Active Element

A capacitance multiplier is an active circuit designed specifically to increase the capacitance of a passive capacitor to a significantly higher capacitance level. In this paper, the use of a voltage differencing differential difference amplifier (VDDDA), an electronically controllable active device for designing grounded and floating capacitance multipliers, is proposed. The capacitance multipliers proposed in this study are extremely simple and consist of a VDDDA, a resistor, and a capacitor. The multiplication factor (Kc) can be electronically controlled by adjusting the external bias current (IB). It offers an easy way of controlling it by utilizing a microcontroller for modern analog signal processing systems. The multiplication factor has the potential to be adjusted to a value that is either less than or greater than one, hence widening the variety of uses. The grounded capacitance multiplier can be easily transformed into a floating one by utilizing Zc-VDDDA. PSpice simulation and experimentation with a VDDDA realized from commercially available integrated circuits were used to test the performance of the proposed capacitance multipliers. The multiplication factor is electronically adjustable, ranging in approximation from 0.56 to 13.94. The operating frequency range is approximately three frequency decades. The realization of the lagging and leading phase shifters using the proposed capacitance multiplier is also examined and proven. The results reveal that the lagging and leading phase shifts are electronically tuned via the multiplication factor of the proposed capacitance multipliers.

Cost-Effective Quasi-Parallel Sensing Instrumentation for Industrial Chemical Species Tomography

Chemical species tomography (CST) has been widely applied for the imaging of critical gas-phase parameters in industrial processes. To acquire high-fidelity images, CST is typically implemented by the line-of-sight wavelength modulation spectroscopy measurements from multiple laser beams. In this article, we present a novel quasi-parallel sensing technique and electronic circuits for industrial CST. Although the acquisition and processing of these multiple beams using a fully parallel data acquisition and signal processing system can achieve maximized temporal response in CST, it leads to a highly complex and power-consuming instrumentation with electronics-caused inconsistency between the sampled beams, in addition to a significant burden on data transfer infrastructure. To address these issues, the digitization and demodulation of the multibeam signals in the proposed quasi-parallel sensing technique are multiplexed over the high-frequency modulation within a wavelength scan. Our development not only maintains the temporal response of the fully parallel sensing scheme but also facilitates the cost-effective implementation of industrial CST with very low complexity and reduced load on data transfer compared with the fully parallel sensing technique. The proposed technique was analytically proofed and then numerically examined by noise-contaminated CST simulations. Finally, the designed electronics was experimentally validated using a lab-scale CST system with 32 laser beams.

Design of multi-channel data acquisition system for real-time perception lidar

Lidar is the most effective means for real-time environmental awareness. Based on the demand of multi-channel perception lidar with large amount of data, real-time data transmission and miniaturization, a multi-channel parallel signal acquisition and processing system was designed based on FPGA and DSP. A self-developed three-dimensional lidar was designed, including mechanical scanning, linear array detection, data acquisition and control system. The system was implemented and verified in the three-dimensional point cloud imaging experiments. In this system, FPGA was responsible for multi-channel lidar data acquisition, control and transmission. DSP was used for data calculation and uploading the point cloud data to the upper computer through the network to realize the real-time display of point cloud. The experiments of lidar show that the proposed real-time data acquisition system could meet the requirements of point cloud calculation at 2 Mpts/s, with real time data acquisition and procession at 20 fps. The rapid calculation of lidar point cloud of the environment and obstacles is realized. It can be applied to automatic driving, navigation obstacle avoidance, perimeter security and etc.

Differentiation of Optical Signals with Dielectric Ridges on Top of a Slab Waveguide

We propose two simple planar structures that enable spatial differentiation of the profile of optical beams propagating in a slab waveguide. The differentiator operating in transmission consists of a single subwavelength dielectric ridge on the surface of a slab waveguide. The differentiator operating in reflection consists of two grooves on the surface of a slab waveguide. In both cases the differentiation is performed at oblique incidence of the beam and is associated with the resonant excitation of the considered structures eigenmodes localized at the ridge or at the ridge between two grooves. It is shown that the required balance between the differentiation quality and the amplitude of the differentiated beam can be achieved by manipulating the quality factor of the resonance. The presented numerical simulation results demonstrate high-quality differentiation. The proposed differentiator may find application in ultrafast analog computing and signal processing systems.

Spatial integration and differentiation of optical beams in a slab waveguide by a dielectric ridge supporting high-Q resonances.

We show that a very simple structure consisting of a single subwavelength dielectric ridge on the surface of a slab waveguide enables spatial integration and differentiation of the profile of optical beams propagating in the waveguide. The integration and differentiation operations are performed in reflection and in transmission, respectively, at oblique incidence of the beam impinging on the ridge. The implementation of these operations is associated with the resonant excitation of a cross-polarized eigenmode of the ridge. We demonstrate that the quality factor of the resonances strongly varies along the dispersion curves and allows one to achieve the required tradeoff between the integration (or differentiation) quality and the amplitude of the resulting beam. The presented rigorous numerical simulation results confirm high-quality integration and differentiation. The proposed integrated structure may find application in ultrafast all-optical analog computing and signal processing systems.

Analog and digital signal processing method using multi-time-over-threshold and FPGA for PET.

The goal of this study was to develop an analog and digital signal processing method using multi-time-over-threshold (MTOT) and field programmable gate arrays (FPGAs) to extract PET event information by using the internal clock of FPGA (~350 MHz), without ADC and TDC. The PET detector modules were composed of a 4 × 4 matrix of 3 × 3 × 20 mm3 LYSO and 4 × 4 SiPM array. Output charge signals of PET detector modules were amplified and fed into four comparators to generate trigger signals. The energy of the detected gamma ray was calculated by integrating the digitized pulse and the arrival time was determined from the time stamp of the lowest trigger signal by FPGA. The data packet containing energy, time, and position information was stored in list mode on the host computer. The performance of analog and digital signal processing circuits using MTOT method and FPGA was evaluated by measuring energy and time resolution of the proposed method and the values were 19% and 900 ps, respectively. This study demonstrated that the proposed MTOT method consisting of only FPGA without ADC and TDC could provide a simple and cost-effective analog and digital signal processing system for PET.

Planar two-groove optical differentiator in a slab waveguide.

We propose a simple planar optical differentiator consisting of two grooves on the surface of a slab waveguide. The studied differentiator operates in reflection and enables temporal and spatial differentiation of optical pulses and beams propagating in the waveguide. The differentiation is associated with the excitation of an eigenmode localized at the ridge located between the grooves. The presented numerical simulation results demonstrate high-quality spatial, temporal and the so-called spatiotemporal differentiation. The proposed differentiator may find application in ultrafast analog computing and signal processing systems.

Loss-Gain Equalized Reconfigurable C-Section Analog Signal Processor

We present a loss-gain equalized reconfigurable phaser for dynamic radio analog signal processing (R-ASP). Such a phaser provides real-time tunable group delay response with all-pass transmission. We propose a lumped loss-gain implementation, where tuning and equalization are mostly easily achieved. A theoretical study derives the transfer function and the fundamental characteristics of the device. The phaser is finally experimentally demonstrated, first using a single loss-gain pair and finally a three cascaded loss-gain pair structure with full reconfigurability , where up-chirp and down-chirp group delays are shown for illustration. It is expected that this phaser will find wide applications in radio analog signal processing (R-ASP) systems requiring dynamic adaptability.

Current-programmable Universal Biquad Filter Based on Modified Current Differencing Transconductance Amplifier

This paper presents a new current programmable active element called Modified Current Differencing Transconductance Amplifier (MCDTA). The parameters of the circuit - input resistance and transconductance - can be tuned by control currents. The circuit with several external components - diodes and grounded capacitors - makes it possible to build basic analog circuits: first order and second order tunable active filters, rectifiers, peak detectors and others. This paper discusses a universal biquad filter based on the MCDTA with different tuning capabilities. The simulation results show that it can be used as a part of a programmable analog signal processing system.

A Multiplexer with Split Devices for High Channel Isolation

A multiplexer with split devices for high channel isolation was proposed in this paper. The multiplexer is the most essential circuitry for multi-channel video signal acquisition systems. In the multi-channel applications, high isolation performance is required basically for the efficient signal processing. The noise propagation between channels is unexpected. The split devices technique is employed in the design work. Redundant transistors are inserted between the split cells to realize the noise grounded. This multiplexer is simulated and verified in the commercial CMOS process, and the isolation of more than 70dB was achieved. It has been embedded in a multi-channel analog signal processing system.

16NM BULK CMOS DOCCCII BASED CONFIGURABLE ANALOG BLOCK DESIGN FOR FIELD PROGRAMMABLE ANALOG ARRAY

Field programmable analog array (FPAA) is a rapidly growing technology for fast prototyping of analog signal processing systems facilitating the quick innovation at industry level with saving in terms of both time and cost. Analog signal processing is much faster and consumes less power than conventional digital signal processing, justifying the need for FPAA. Here we propose a Dual output current controlled current conveyor (DOCCCII) in 16nm bulk CMOS technology using PTM (High Performance 16nm Metal Gate / High-K / Strained-Si parameter) and discuss its characteristic. DOCCCII is superior in design among Current Conveyors because it requires no additional resistance for activation, it has it’s own parasitic resistance tunable through biasing current and has high bandwidth (GHz range). A configurable analog block (CAB) is also proposed which mainly consists of the DOCCCII readily configurable to realize an application. This cab is used here for the realization of 2 nd order filters.

Design of RF MEMS Based Oscillatory Neural Network for Ultra High Speed Associative Memories

Microelectromechanical systems are utilized alongside with transistor amplifiers and resistive connections for implementing of oscillatory associative memories. Phase locking is studied in such a network and all requirements of the circuit level implementation are satisfied. A very high gain trans-impedance amplifier operating in 1 GHz in addition to a novel automatic amplitude control circuit is employed to remove amplitude dynamics of the system. Requiring resonator characteristics are extracted and calculated as well. A new method for initialization of the network is proposed. Each neuron consumes 1.08 mW from a 1.8 V power supply. The convergence time of a typical network trained by Hebbian rule is less than 1.5 ns which results in an ultra high speed analog signal processing system.

Analog Filter Design Using Ring Oscillator Integrators

Integrators are key building blocks in many analog signal processing circuits and systems. The DC gain of conventional opamp-RC or Gm- C integrators is severely limited by the gain of operational transconductance amplifier (OTA) used to implement them. Process scaling reduces transistor output resistance, which further exacerbates this issue. We propose applying ring oscillator integrators (ROIs) in the design of high order analog filters. ROIs implemented with simple CMOS inverters achieve infinite DC gain at low supply voltages independent of transistor non-idealities and imperfections such as finite output impedance. Consequently, ROIs scale more effectively into newer processes. A prototype fourth order filter designed using the ROIs was fabricated in 90 nm CMOS and occupies an area of 0.29 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Operating with a 0.55 V supply, the filter consumes 2.9 mW power and achieves bandwidth of 7 MHz, SNR of 61.4 dB, SFDR of 67.6 dB and THD of 60.1 dB. The measured IM3 obtained by feeding two tones at 1 MHz and 2 MHz is 63.4 dB.

A High-Level Simulink-Based Tool for FPAA Configuration

With the rapid increase in size and complexity of analog systems being implemented on field-programmable analog arrays (FPAAs), the need for synthesis tools is becoming a necessity. In this paper, we present Sim2spice, a tool that automatically converts analog signal-processing systems from Simulink designs to a SPICE netlist. This tool is the top level of a complete chain of automation tools. It allows signal-processing engineers to design analog systems at the block level and then implement those systems on a reconfigurable-analog hardware platform in a matter of minutes. We will provide detailed descriptions of each stage of the design process, elaborate on a custom library of analog signal-processing blocks, and demonstrate several examples of systems automatically compiled from Simulink blocks to analog hardware.

Increased Group-Delay Slope Loop System for Enhanced-Resolution Analog Signal Processing

A novel increased group-delay slope loop scheme is proposed to enhance the time-frequency resolution of dispersive delay structure (DDS) components for microwave analog signal processing systems. In this scheme, the signal at the output of the DDS is regenerated by an amplifier and reinjected via a nondispersive delay line toward its input along a loop. At each pass across the DDS, the effective group-delay slope of the system is increased so that, after <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> turns along the loop, the time-frequency resolution has been enhanced by a factor <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> . This approach provides a solution to the unpractical approach of cascading <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> DDS units, which would lead to excessively large device footprint, unacceptably high insertion loss, and severe signal-to-noise reduction. The proposed scheme is implemented in a proof-of-concept circuit using a C-section all-pass network DDS and demonstrated experimentally in a frequency meter and in a frequency discriminator. Possible improvements for higher performance are discussed.

Low-Cost Optical Flowmeter With Analog Front-End Electronics for Blood Extracorporeal Circulators

The design and realization of a new low-cost instrument for real-time measurement of blood flow particularly developed for extracorporeal blood circulator systems are presented. A self-mixing interferometric technique combined with a dedicated analog signal processing system was adopted to perform an accurate flow measurement. The developed system exhibits an accuracy lower than 3%. The cost of the entire measuring system has been estimated to be about 50 euros.

Reflection-Type Artificial Dielectric Substrate Microstrip Dispersive Delay Line (DDL) for Analog Signal Processing

A reflection-type artificial dielectric substrate (ADS) microstrip dispersive delay line (DDL) for analog signal processing is presented. This DDL is realized by nonuniformly alternating conventional and ADS microstrip sections with a linearly increasing period (linear group delay or constant chirp) so that the different spectral components of a modulated signal incur different delays proportional to their frequency to be discriminated in time. Design guidelines are provided. The proposed DDL is demonstrated theoretically, numerically, and experimentally, and is fully characterized in terms of reflective level, bandwidth, group delay, and chirping coefficient for excitation at both ports. The DDL is then demonstrated in a frequency discriminator. Finally, it is compared with a stepped-impedance DDL and a sinusoidal-impedance DDL, and shown to exhibit superior symmetry along to smaller overall loss due to dramatically mitigated radiation, thereby leading to superior performances in various analog signal-processing systems such as impulse delay lines, real-time Fourier transformers, and compressive receivers.

Novel Conventional Standard Linear Element Based Complete Passive Equivalent Circuit Models of the Practical OTA-Based Inductors

In this research, the practical OTA-based inductors of all structures have been studied and their complete passive equivalent circuit models, where the effects of both parasitic elements and finite opened-loop bandwidth have been taken into account, also contain only the conventional standard linear elements i. e. the ordinary resistor, inductor and capacitor, without any infeasible high order element e. g. super inductor etc., have been proposed. The resulting models have been found to be excellently accurate, excellently straight forward, far superior to the previously proposed ones and completely realizable by the passive elements. Hence, the proposed passive equivalent circuit models have been found to be the convenience and versatile tools for the implementation of any analog and mixed signal processing circuits and systems.

Substrate model extraction using finite differences and parallel multigrid

Substrate noise in integrated circuits is one of the most important problems in high-frequency mixed-signal designs, such as communication, biomedical and analog signal processing circuits and systems. Fast-switching digital blocks inject noise into the common substrate, hindering the performance of high-precision sensible analog circuitry. Miniaturization trends require increasing the accuracy in substrate coupling simulation environments. However, model extraction and evaluation times should not increase, which demands for fast and still accurate substrate model extraction tools. In this work, a three-dimensional finite difference extraction methodology is presented. The resulting three-dimensional mesh is efficiently reduced to a circuit-level contact-based model by means of a fast multigrid-based algorithm. Moreover, this contact-based model extraction is shown to be efficiently computed in a parallel environment, resulting in extremely useful extraction speedups. Extraction results prove the proposed method to be very efficient, providing linear time and space complexity, and a constant number of iterations, outperforming competing algorithms.