Analog Shift Register Research Articles

One-dimensional discrete-time CNN with multiplexed template-hardware

This paper presents a novel discrete-time and fully programmable cellular neural network (CNN) suitable for processing one-dimensional (1-D) signals. As 1-D signals are typically very long sequences, the system consists of a linear analog shift register for data I/O coupled to a 1/spl times/n CNN array. In addition to the 1-D CNN architecture, a unique feature of our implementation is that the number of multipliers needed to implement both CNN templates has been minimized. This is conceivable because the multipliers are multiplexed between the A*y and B*u products during alternating phases of the controlling clock. The CNN system has been implemented in current mode based on the S/sup 2/I technique using MOSIS Orbit 2 /spl mu/m CMOS technology. The paper presents a thorough behavioral analysis of the new architecture, circuit-level implementations, and corresponding measured experimental results.

2-D analog filters for real time video signal processing

A practical hardware design of a two-dimensional (2D) analog filter proposed by M.A. Sid-Ahmed (IEEE Circ. and Syst., vol.36, p.153-4, Jan. 1989) is developed. The structure is implemented using charge coupled device (CCD) analog shift registers and wideband operational amplifiers. The operation of the filter is demonstrated by processing TV video images in real time. The 2D analog approach is evaluated by comparison with a 2D distributed arithmetic digital filter. The analog approach offers realization at lower cost, less power consumption, higher resolution, and inherent true real-time capability independent of filter order. >

Electronic audio signal processor

An electronic audio signal processor especially suitable for electrical instruments such as electric guitars is provided including a controlled distortion and tone alteration portion and a reverb portion. The controlled distortion and tone alternation portion in one form comprises in cascade a compression stage which compresses the amplitude level of an inputted audio signal, a mid band pass filter, a distortion amplifier for adding controlled distortion to said signal and a complex filter having a roll-off of increased attenuation with increased frequency range in the lower and upper audio frequency ranges, and a generally flat response in the middle audio frequency range except with a dip followed by a peak in the upper portion of the mid audio frequency range. The reverb circuit includes a synthetic doubler which provides an output cyclicly varying in pitch from its input and a stereo analog shift register reverb device having two summers which combine staggered adjacent output lines from an analog shift register in different combinations. Two output mixers in conjunction with a switch provide reverb alone, doubling alone or reverb with doubling.

Active analog pipeline delays for high signal rates in multistation flow cytometers.

Flow cytometers with sequential measuring stations require alignment of event timing information to assure that multiparameter data for each cell are properly correlated. Information from the first detector must be delayed until signals are produced at the last detector, with adjustments to align them in time for simultaneous digitization after the last measurement is completed. By using an analog "pipeline" delay, the deadtime between the first and last measuring stations can be minimized. The described device is capable of acquiring and propagating many signals within the delay period, with good fidelity at high signal rates. An integrated circuit charge-coupled device (CCD), which is an analog shift register, is shown to be useful as a signal delay in the time range from 22 microseconds to several milliseconds.

Chorus generator system

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A Fast Multichannel Analog Storage System

A Multichannel Analog Storage System based on a commercial 32-channel parallel in/serial out (PISO) analog shift register is described. The basic unit is a single width CAMAC module containing 512 analog cells and the associated logic for data storage and subsequent readout. At sampling rates of up to 30 MHz the signals are strobed directly into the PISO. At higher rates signals are strobed into a fast presampling stage and subsequently transferred in block form into an array of PISO's. Sampling rates of 300 MHz have been achieved with the present device and 1000 MHz are possible with improved signal drivers. The system is well suited for simultaneous handling of many signal channels with moderate numbers of samples in each channel. RMS noise over full scale signal has been measured as 1:3000 (≈11 bit). However, nonlinearities in the response and differences in sensitivity of the analog cells require an elaborate calibration system in order to realize 11 bit accuracy for the analog information.

A Dual Parameter Discriminator for Use with Gas Scintillation Proportional Counters

A new diagnostic tool has recently been developed at Los-Alamos for use in optimizing the performance of gas scintillation proportional counters. The instrument is a Dual Parameter Discriminator which allows for discrimination of nuclear pulses either by height, risetime, or both. This makes possible the generation of risetime spectra for different pulse height ranges, and pulse height spectra for different risetime ranges. The Dual Parameter Discriminator will easily measure risetimes up to about 45 microseconds. It has a lower risetime threshold of 100 nanoseconds, and will discriminate over the entire risetime range in 100 nanosecond increments, selected by front-panel thumbwheel switches. This wide dynamic range makes it useful in measuring the characteristics of large gas scintillation proportional counters which produce signals with risetimes too long to be measured using conventional techniques. The discriminator also has provision to store 0 to 5 volt pulse heights directly in an analog shift register, eliminating the need for capacitive holding circuits which are subject to droop and repeatability errors. The instrument contains both analog and digital outputs for connection either to a pulse height analyzer or computer.

Analog processing system for real‐time conversion of the frequency of analog signals

An analog signal processing system is described for changing the frequency of analog signals in a real-time manner. The system includes at least two analog shift registers, (specifically, three analog shift registers), an input circuit connecting the input end of all the registers in parallel, an output circuit selectively connectable to the output ends of the registers, a high frequency clock pulse source, a lower frequency clock pulse source, and cyclically operable switching means effective to load from the input circuit at least one analog shift register at the rate corresponding to the frequency of one of the clock pulses, while unloading at least one other register into the output circuit at the rate corresponding to the frequency of the other clock pulses. Two applications are described, for purposes of example. One application is as a hearing aid device to reduce the frequency of audio signals in a real-time manner for a person having a limited-frequency audibility. The other application is a communication device for the real-time transmission and reception of audio signals rendering them unintelligible except by receivers equipped with a processing system for reducing the frequency of the received signals.

A high speed tapped CCD photodiode linear image sensor

A tapped charge-coupled photodiode (CCPD) array for high speed document scanning applications has been developed. This linear sensor array is comprised of 1024 photodiode elements divided into 8 sections of 128 elements each and accessed by 16 CCD analog shift registers. This arrangement allows the device to operate at a maximum output data rate of 160 MHz. Utilizing diffused photodiodes for photosensing and CCD registers for low-noise signal extraction, this device has a dynamic range of 1000:1 and spectral response from .2 µm to 1.1 µm. The modular design also permits arrays of 512 or 256 elements.

Sound synthesizing apparatus

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Speech compressor with gap filling

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Charge-transfer filtering

Linear discrete-time (sampled-data) filters can be implemented in monolithic form on an MOS chip using a variety of recently developed and newly emerging techniques without requiring analog-to-digital conversion. An analog signal sample can be represented by an isolated quantity of charge and such packets of charge can be stored, transferred, and manipulated in other ways to perform signal processing operations. Best known of these techniques is the use of a charge-coupled device (CCD) to operate as an analog shift register. A simple modification of the CCD shift register allows the realization of transversal filters. Other techniques can implement recursive filter operations offering a great flexibility for filter design. The possibilities and limitations of charge-transfer filtering are reviewed and examined.

Fast Event Recorder Utilizing a CCD Analog Shift Register

A system of electronics has been developed to allow the capture and recording of relatively fast, low-amplitude analog events. The heart of the system is a dual 455-cell analog shift register charge-coupled device, Fairchild CCD321ADC-3. The CCD is operated in a dual clock mode. The input is sampled at a selectable clock rate of .25-20 MHz. The stored analog data is then clocked out at a slower rate, typically about .25 MHz. The time base expansion of the analog data allows for analog-to-digital conversion and memory storage using conventional medium-speed devices. The digital data is sequentially loaded into a static RAM and may then be block transferred to a computer. The analog electronics are housed in a single-width NIM module, and the RAM memory in a single-width CAMAC module. Each pair of modules provides six parallel channels. Cost is about $200.00 per channel. Applications are described for ionization imaging (TPC, IRC) and long-drift calorimetry in liquid argon.

A dual-differential analog shift register with a charge-splitting input and on-chip peripheral circuits

A very high degree of stability and the elimination of external support circuitry are requirements for many signal-processing applications of analog charge-coupled devices. A device that meets these requirements has been designed and fabricated. The device requires a single clock input signal and achieves a gain-temperature stability of /spl plusmn/0.015 dB over 0-50/spl deg/C and a gain-voltage stability of /spl plusmn/0.05 dB over a power-supply variation of /spl plusmn/10 percent. The NMOS device demonstrates the compatibility of digital, linear, and charge-coupled devices on a single chip.

New approaches to analog music synthesis

Analog, voltage-controlled electronic music synthesizers have been developed over a period of about ten years into a fairly standard commercial product. While these synthesizers are unquestionably useful for certain types of music, they are also limited in many ways. A number of fairly simple “new modules” involving conventional circuitry and conventional electronic components can be developed and added to the conventional set of synthesizer modules. New types of excitation sources for driving processing type modules are also possible. Beyond these, new developments in electronics make possible entirely new synthesis devices and suggest new approaches to older unsolved problems. As one example, digital control of analog synthesis based on a microprocessor approach makes it possible to realize musical structures and developments of a greater complexity than is possible with manual control alone. As a second example, charge-transfer analog shift registers provide, analog delay in a compact and inexpensive form, thus making possible new approaches to special musical effects, reverberation, and pitch extraction, to name a few.

An Analog Delay Circuit for On-Line Visual Confirmation of Discriminated Neuroelectric Signals

An analog delay circuit which utilizes an inexpensive commercially available analog shift register is described. The delay circuit when used in conjunction with a window discriminator will display on-line visual confirmation of single neural events from extracellular recordings containing more than one spike class. The delay can be changed to include the entire spike waveform by adjusting a potentiometer in the delay circuit.

Charge-coupled devices: The analog shift register comes of age

Charge-coupled devices: The analog shift register comes of age

Moat-etched two-phase charge-coupled devices

A novel technique for fabricating two-phase charge-coupled devices is described. The structure requires only thermally grown SiO 2 and makes use of moats etched into the silicon which in conjunction with a single layer metallization achieve small interelectrode spacings and directionality of charge transport. The feasibility of the technique is demonstrated experimentally. The devices fabricated were successfully operated as both digital and analog shift registers. The method described offers certain advantages in ease of fabrication and reliability along with the capability for high speed operation.

Charge Coupling; An All Electronic Approach to Position Sensitive Particle Detection

A review of the workings of charge coupled devices is given with the intention of bringing out the essential features and characteristics essential to understanding their capabilities and limitations as analog shift registers and imaging devices. While attention is focused on three phase devices, some attention is given to two and four phase devices as well as the bucket brigade devices. The special advantages of these devices as compared to existing imaging devices is discussed.

A memory system based on surface-charge transport

The surface-charge transistor (SCT) is an integrated-circuit element and involves a new concept for controlling the transfer of stored electrical charge along the surface of a semiconductor. The experimental transient response of a large-geometry SCT is presented. Linear high-density arrays of surface-charge transistors may be utilized to form digital or analog shift registers. The experimental performance of a 14-bit shift register, which has been operated in both these modes, is given. By forming these units in a serpentine fashion, charge (information) may be transported back and forth between refresh circuits to form an array of cells. An experimental circuit of this type is presented. Using these techniques a digital serial memory of high density may be constructed. Using standard metalization linewidths and tolerances a cell size of 2 mil/SUP 2/ per bit is shown to be feasible.