Nonvolatile Analog Memory Research Articles

An 8-bit-resolution, 360-/spl mu/s write time nonvolatile analog memory based on differentially balanced constant-tunneling-current scheme (DBCS)

This paper describes a fast and accurate nonvolatile analog memory (NVAM) and its programming scheme. Both constant programming rate and single-pulse programmability have been achieved, which drastically enhance programming speed and accuracy. A prototype chip containing 8/spl times/128 NVAM cells (cell size of 9/spl times/13.6 /spl mu/m/sup 2/) has been fabricated using 0.8-/spl mu/m CMOS. Each cell is measured to store more than eight bit levels within 360 /spl mu/s.

A 128-pixel CMOS image sensor with integrated analog nonvolatile memory

A 128-pixel complementary metal-oxide-semiconductor (CMOS) image sensor array with analog nonvolatile storage for each pixel has been realized in a 1.5-/spl mu/m single-poly standard CMOS/EEPROM technology and successfully tested. The integrated nonvolatile memory allows an offset correction for each sensor element, cancellation of the fixed pattern noise, and compensation of the background illumination. The sensor array can also learn a presented pattern and store it in its analog nonvolatile memory just by "seeing". The stored pattern can be read out directly or, in combination with the optical input, it can be used for pattern recognition or motion detection. The required programming circuitry for the analog memory has been integrated on the same chip.

A user's guide to non-volatile, on-chip analogue memory

On-chip, non-volatile analogue memory is essential in hardware implementations of many of the early stages of signal processing, including neural network preprocessors and other adaptive sensor fusion amplifiers. Such storage is also desirable for trimming analogue circuits electronically and for parameter retention on power-down. This paper reviews the current state-of-the-art from a designer's perspective, highlighting the promises and problems associated with a range of approaches.

Trimming smart imagers for an image converter with a non-volatile analog memory

Abstract Trimming of the pixels in an image converter is presented in this work. It is based on the tunnel effect and can be used simultaneously for many pixels with only one common trimming control for all the pixels. The charge injection control is done locally, automatically and independently in each pixel, so the trimming time is independent of the number of pixels. A prototype of this image converter has been fabricated in a CMOS 2.4 μm technology and the experimental results show that the trimming is efficient and that the linearity of the converter image is unchanged.

Trimming CMOS smart imager with tunneleffect nonvolatile analogue memory

Amplified MOS imagers (AMIs) have the advantage of being compatible with conventional CMOS analogue/digital circuit design. One of the major problems in AMIs is their large fixed pattern noise compared to CCD imagers. The Letter presents the structure of a nonvolatile tunnel-effect analogue memory which is fully compatible with a standard CMOS process and which can reduce significantly the offset-like fixed pattern noise in AMI arrays.

Analogue Memory Effects in Metal/ a-Si:H /Metal Thin Film Structures

The ac conductivities of non-volatile analogue memory states are measured in electro-formed Cr/p+/V amorphous silicon structures for a broad frequency range (from 0.1 Hz to 32 MHz). The results suggest that the memory action is associated with electronic processes.

Floating gate structures as nonvolatile analog memory cells in 1.0μm-LOCOS-CMOS technology with PZT dielectrica

In this paper a new floating gate structure of a nonvolatile analog memory cell in 1.0 μm-LOCOS-CMOS-technology is proposed. The new floating gate transistor with Pb(Zr; Ti) O 3 as dielectrica between the control and floating gate needs no additional coupling area. After the description of the device fabrication basic characteristics of the ferroelectric material PZT and the new transistor cell are presented. In comparison to measurements on standard floating gate structures it is pointed out that the use of PZT increases or preserves the programming efficiency in spite of a considerable reduction in cell area. In the face of high leakage currents through PZT the memory cells without an additional coupling area can be programmed. For a sufficient support of the tunnel mechanism and for an utilization of the high dielectric constant of Pb(Zr; Ti) O 3 a dielectric combination of SiO 2 and PZT in analog memory cells seems to be efficient to avoid the occured leakage current.

A modifiable weight circuit for use in adaptive neuromorphic networks: [formula omitted]. Code 551, Naval Ocean Systems Center, San Diego, CA 92152-5000, USA

Abstract : The Naval Ocean Systems Center is involved in a collaborative effort with the Naval Weapons Center to implement neuromorphic networks in analog integrated circuitry using CMOS technology. We are investigating the use of a floating-gate charge storage device as a modifiable, non-volatile analog memory element for representing and storing interconnection weights between processing units, and have designed a simple circuit to sense this charge and perform the multiplicative 'synaptic' function. We employ the mechanism of avalanche or hot- carrier injection to move charge onto a floating-gate structure. This mechanism was first used in the mid-1970's for digital memory applications in the 'FAMOS' (floating gate avalanche injection MOS) device, which consisted of a p-channel MOSFET with an isolated gate. At an appropriate biasing voltage, 'hot' electrons are generated in avalanche breakdown, which have sufficient energy to conduct across the gate oxide and charge the gate. In an n-channel device, a complementary process takes place, with holes rather than electrons injected onto the floating gate. The potential due to the charge influences the state of the transistor under the gate just as would an externally applied voltage. Multimedia Reprint, Naval document. (RRH)

A New Tuning System With Non-Volatile Analog Memory

Electronic tuning systems are roughly classified into two categories. One is a frequency synthesizer system and the other is a voltage synthesizer system. The system described in this paper is the latter one.

New thin-film resistive memory

A new thin-film metal-insulator-metal device is described. After the insulator has undergone a forming process, which consists of the electrolytic introduction of gold ions from one of the electrodes, its conductivity is observed to have increased quite markedly. In addition the sample displays negative-resistance and memory phenomena. It is shown that under the appropriate switching conditions the device can be used as a non-volatile analogue memory with non-destructive read-out. The theory of operation of the device is also presented.