Analog Mixed Signal Circuits Research Articles

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts

Well island generation and well tap placement is an important problem in analog/mixed-signal (AMS) circuits. Well taps can only prevent latchups within a certain radius of influence within a well island, and hence must be appropriately inserted to cover all devices. However, existing automated AMS layout paradigms typically defer the insertion of well taps and creation of well islands to a post-processing step after placement. This alters the placement, resulting in increased area and wire length, as well as circuit performance degradation. Therefore, there is a strong need for a solution that generates well islands and inserts well taps during placement so the placer can account for well overheads in optimizing placement metrics. In this work, we propose a modular solution using a graph-based optimization scheme that can be used within multiple placement paradigms with minimal intrusion. We demonstrate the integration of this scheme into stochastic, analytical, and designer-driven row-based placement. The method is demonstrated in advanced FinFET technologies. Layouts generated using this scheme show better area, wire length, and performance metrics at the cost of a marginal runtime degradation when compared to the post-processing approach. Using our scheme, there is an average improvement of 3% and 4% and a maximum improvement of 23% and 11% in area and wirelength, respectively, of layouts of various classes of AMS circuits at the cost of 17% average and 29% maximum increase in total runtime.

A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example

We propose a speculative divide-and-conquer (SDnC) method that enables optimization of a large analog/mixed-signal (AMS) circuit. Because modules of AMS circuits strongly interact with neighbor modules, they cannot be optimized individually. Therefore, design parameters of all modules must be co-optimized for the global optimization, and thus, the design space exponentially grows with the circuit size. Although metaheuristic algorithms can enhance optimization efficiency, they cannot handle very large circuits due to the exponentially increased size of design space to explore. The proposed method utilized the divide-and-conquer (DnC) strategy in the circuit optimization while taking into account modules’ interactions, allowing modules to be individually evaluated and optimized. Therefore, this DnC-based optimization method hierarchically and systematically reduces both the optimization complexity and the evaluation complexity, and thus, this method is very scalable with the circuit size. The proposed method can also be combined with other metaheuristic algorithms such as particle swarm optimization (PSO) or artificial intelligence for faster optimization. In experiment, the proposed method enabled optimization of a high-speed link transmitter that has 2400–15 000 transistors and 45–47 independent design parameters for the first time. The optimization time was improved by 43 and three orders of magnitudes compared to parameter sweep and PSO, respectively. The penalties of speed-up by DnC were only 3.4% and 9.3% estimation errors in power consumption and eye height, respectively. Because of the greatly improved speed, the proposed method also enables quantitative analysis on performance-power tradeoff of a large AMS circuit.

A Robust Automated Analog Circuits Classification Involving a Graph Neural Network and a Novel Data Augmentation Strategy.

Analog mixed-signal (AMS) verification is one of the essential tasks in the development process of modern systems-on-chip (SoC). Most parts of the AMS verification flow are already automated, except for stimuli generation, which has been performed manually. It is thus challenging and time-consuming. Hence, automation is a necessity. To generate stimuli, subcircuits or subblocks of a given analog circuit module should be identified/classified. However, there currently needs to be a reliable industrial tool that can automatically identify/classify analog sub-circuits (eventually in the frame of a circuit design process) or automatically classify a given analog circuit at hand. Besides verification, several other processes would profit enormously from the availability of a robust and reliable automated classification model for analog circuit modules (which may belong to different levels). This paper presents how to use a Graph Convolutional Network (GCN) model and proposes a novel data augmentation strategy to automatically classify analog circuits of a given level. Eventually, it can be upscaled or integrated within a more complex functional module (for a structure recognition of complex analog circuits), targeting the identification of subcircuits within a more complex analog circuit module. An integrated novel data augmentation technique is particularly crucial due to the harsh reality of the availability of generally only a relatively limited dataset of analog circuits' schematics (i.e., sample architectures) in practical settings. Through a comprehensive ontology, we first introduce a graph representation framework of the circuits' schematics, which consists of converting the circuit's related netlists into graphs. Then, we use a robust classifier consisting of a GCN processor to determine the label corresponding to the given input analog circuit's schematics. Furthermore, the classification performance is improved and robust by involving a novel data augmentation technique. The classification accuracy was enhanced from 48.2% to 76.6% using feature matrix augmentation, and from 72% to 92% using Dataset Augmentation by Flipping. A 100% accuracy was achieved after applying either multi-Stage augmentation or Hyperphysical Augmentation. Overall, extensive tests of the concept were developed to demonstrate high accuracy for the analog circuit's classification endeavor. This is solid support for a future up-scaling towards an automated analog circuits' structure detection, which is one of the prerequisites not only for the stimuli generation in the frame of analog mixed-signal verification but also for other critical endeavors related to the engineering of AMS circuits.

Low-voltage low-noise gate driven quasi-floating bulk self-cascode current mirror operational transconductance amplifier.

A gate driven quasi-floating bulk self-cascode current mirror operational transconductance amplifier operable at ±0.9 V supply voltage with DC gain (70 dB), gain bandwidth (250 kHz), noise (2.8 µV/√Hz at 1 Hz), and power consumption (2.96 µW) simulated in 0.18 µm technology has been introduced. Results obtained are superior in comparison to gate driven self-cascode current mirror and regular current mirror OTAs, which can be utilized to improve the performance of analog-mixed signal circuits and systems.

Design of efficient delay block for low frequency application

In recent years researchers have been focusing on the design of low power and small size oscillator for emerging areas of interest such as the internet of things (IoT) and biomedical applications. In this paper a new delay block for ring oscillator is proposed using CMOS inverter cascaded with inverted current starved inverter (CICSI). The designed delay block provides approximately 50% more delay with a smaller number of transistors than the conventionally designed circuits. Furthermore, a ring oscillator and a non-overlapping clock (NOC) generator are designed using it. The designed circuits can be used in switched capacitor (SC) circuits, analog mixed signal circuits to meet the need for low frequency portable biomedical applications. The designed circuits are simulated on Generic 90nm 1.2V Process Design Kit (GPDK90) using Cadence Virtuoso Design Environment. The simulation result shows the delay of the CICSI delay block is 592ps. The ring oscillator using 101 stages of delay block is designed and it is shown that it operates at a frequency of 17MHz with a power consumption of 420?W.

Automated pre-placement phase as a part of robust analog-mixed signal physical design flow

A new pre-placement phase of integrated circuits (IC) analog-mixed-signal (AMS) physical design flow, introduced in this paper, automatically sorts electrical devices used in planar IC technologies according to their topological, structural and electrical properties. The presented design phase replaces human labour and allows to save design time and prevent human mistakes. Software implementation of the proposed method works with virtual objects of layout instances which are moved only once at the end of the script when creating the final pre-placement matrix. Algorithm complexity is decreased by a new way of virtual objects matrix indexing. The automatic pre-placement phase has been used during design of AMS circuits in 160 nm BCD8sP and SOIBCD8S technologies from STMicroelectronics and has been faster in the range of 3164 to 20099 times compared to manual sorting. The estimation of ratio between manual sorting time and automatic pre-placement time shows a growing time saving with increasing circuit complexity compared to standard layout flow. The introduced enhanced layout flow is able to prevent a creation of hardly detectable errors occurring at the beginning of AMS physical design, especially the wrong bulk connection errors of semiconductor devices. The automatic pre-placement phase saves hours of reworks and speeds up the entire design process.

Efficient and Reliable Small-Signal Estimate of Quantization Noise Contribution to Phase Noise in $\Delta \Sigma $ Fractional- $N$ PLL

The effect of the quantization noise introduced by $\Delta \Sigma $ modulators in fractional- $N$ phase locked loop is studied in the time domain through a variational model of the corresponding analog mixed signal circuits. The latter can be interpreted as hybrid dynamical systems involving discontinuity boundaries and switching in the vector field. Discontinuity mapping is used to define an accurate high order model to propagate perturbations at discontinuity boundaries. This novel approach is more efficient than computing power spectral density of large-signal waveforms from long lasting time domain simulations. Furthermore, with respect to established macro-modeling techniques, it provides a better understanding of how electric elements influence the noise performance. The inherent features of the circuit components turn out to be directly embedded both in the system fundamental matrix and in the discontinuity mapping involved in its dynamical evolution. The validity of the approach is verified through numerical simulations.

A 65 nm Programmable ANalog Device Array (PANDA) for Analog Circuit Emulation

Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for rapid prototyping and validation of analog circuits. This paper presents design and synthesis methodology of a PANDA design on 65 nm CMOS technology, consisting of a 24 $\times$ 25 cell array, reconfigurable interconnect, configuration memory and serial programming interface. To implement AMS circuits on the PANDA platform, this paper further proposes a CAD tool for technology mapping, placement, routing and configuration bit-stream generation. Several representative building blocks of AMS circuits, such as amplifiers, voltage and current references, filters, are successfully implemented on the PANDA platform. Dynamic reconfiguration capability of PANDA is demonstrated through input offset cancellation of an operational amplifier using an FPGA in a closed loop. Initial measurement results of PANDA implemented circuits demonstrate the potential of the methodology for rapid prototyping and hardware validation of analog circuits.

Accurate and Efficient PSD Computation in Mixed-Signal Circuits: A Time-Domain Approach

The aim of this brief is twofold. On one side, the time-domain technique presented by Vasudevan to obtain the average and instantaneous power-spectral density of electrical variables in analog circuits characterized by (non)stationary noise sources is rigorously extended to the wide class of analog mixed-signal circuits modeled as hybrid dynamical systems. On the other side, an efficient numerical implementation is proposed to overcome the computational effort required by the original approach. The reliability of the method is first tested through the analog ring oscillator analyzed by Vasudevan. A fractional delta-sigma phase-locked loop with dithering is then simulated and the obtained results are partially validated through experimental measurements.

Stochastic Behavioral Modeling and Analysis for Analog/Mixed-Signal Circuits

It has become increasingly challenging to model the stochastic behavior of analog/mixed-signal (AMS) circuits under large-scale process variations. In this paper, a novel moment-matching-based method has been proposed to accurately extract the probabilistic behavioral distributions of AMS circuits. This method first utilizes Latin hypercube sampling coupling with a correlation control technique to generate a few samples (e.g., sample size is linear with number of variable parameters) and further analytically evaluate the high-order moments of the circuit behavior with high accuracy. In this way, the arbitrary probabilistic distributions of the circuit behavior can be extracted using moment-matching method. More importantly, the proposed method has been successfully applied to high-dimensional problems with linear complexity. The experiments demonstrate that the proposed method can provide up to 1666X speedup over crude Monte Carlo method for the same accuracy.

FPGA based chip emulation system for test development of analog and mixed signal circuits: A case study of DC–DC buck converter

Prototyping on FPGA has become a main stream verification methodology for hardware design, test development, software co-design, etc. in the area of digital VLSI. In the case of test development, FPGA serves as a virtual DUT (Design Under Test) and test patters are applied from automatic test equipment (ATE). This verifies not only the chip with design for test (DFT) circuitry and test program but also the entire test setup involving virtual DUT, load board, interconnections with ATE, etc. Although, FPGA based platform is used widely for test program verification of digital ICs, this technique is not used for analog/mixed signal (AMS) circuits because of the difficulty in implementing AMS circuits in FPGAs. This work is concerned with the development of a test emulation platform, termed as hand-in-hand test flow, of AMS circuits based on FPGA. The proposed methodology exploits fixed-point modeling and DSP implementation techniques facilitated by latest FPGAs to model the AMS circuits. The proposed hand-in-hand test flow for AMS circuits will help the test engineers to start their test plan concurrently with the design engineers and validate them much prior to the first silicon. We have illustrated the proposed scheme using the case study of a current programmed buck type switching converter on Xilinx® Virtex™-5 FPGA. The FPGA emulation measurement results show that performance of the emulated DC–DC buck converter (e.g., duty ratio test, line transient, load step) matches well with that of SPICE simulation.

Phase Noise Simulation in Analog Mixed Signal Circuits: An Application to Pulse Energy Oscillators

Noise simulation of oscillators modeled in an analog mixed signal environment is challenging since both conventional steady-state simulation methods, such as shooting and harmonic balance ones, cannot be used. This brief proposes an improved approach based on saltation matrices and an extended formulation that considers the registers of the digital part of the circuit as state variables to determine the steady-state solution and phase noise. The proposed approach allows the correct computation of the fundamental matrix evaluated on the steady-state solution and therefore of the left eigenfunctions that are a key aspect in determining phase noise by exploiting the variational model of the oscillator and Floquet theory. The proposed approach is applied to compute the phase noise of an archetype circuit that implements an energy-restore pulsed oscillator. In these oscillators, the energy lost by the tank is refilled at peculiar time instants determined by a digital controller to maximize efficiency and minimize effects due to flicker noise sources.