Analog Memory Cell Research Articles

Enhanced regularization for on-chip training using analog and temporary memory weights

In-memory computing techniques are used to accelerate artificial neural network (ANN) training and inference tasks. Memory technology and architectural innovations allow efficient matrix–vector multiplications, gradient calculations, and updates to network weights. However, on-chip learning for edge devices is quite challenging due to the frequent updates. Here, we propose using an analog and temporary on-chip memory (ATOM) cell with controllable retention timescales for implementing the weights of an on-chip training task. Measurement results for Read–Write timescales are presented for an ATOM cell fabricated in GlobalFoundries’ 45 nm RFSOI technology. The effect of limited retention and its variability is evaluated for training a fully connected neural network with a variable number of layers for the MNIST hand-written digit recognition task. Our studies show that weight decay due to temporary memory can have benefits equivalent to regularization, achieving a ∼33% reduction in the validation error (from 3.6% to 2.4%). We also show that the controllability of the decay timescale can be advantageous in achieving a further ∼26% reduction in the validation error. This strongly suggests the utility of temporary memory during learning before on-chip non-volatile memories can take over for the storage and inference tasks using the neural network weights. We thus propose an algorithm-circuit codesign in the form of temporary analog memory for high-performing on-chip learning of ANNs.

Designing MoS2 channel properties for analog memory in neuromorphic applications

In this paper, we introduce analog nonvolatile random access memory cells for neuromorphic computing. The analog memory cell MoS2 channel is designed based on the simulation model including Fowler–Nordheim tunneling through a charge-trapping stack, trapping process, and transfer characteristics to describe a full write/read circle. 2D channel materials provide scaling to higher densities as well as preeminent modulation of the conductance by the accumulated space charge from the oxide trapping layer. In this paper, the main parameters affecting the distribution of memory states and their total number are considered. The dependence of memory state distribution on channel doping concentration and the number of layers is given. In addition, how the nonlinearity of memory state distribution can be overcome by variation of operating conditions and by applying pulse width modulation to the bottom gate voltage is also shown.

On the Accuracy of Analog Neural Network Inference Accelerators

Specialized accelerators have recently garnered attention as a method to reduce the power consumption of neural network inference. A promising category of accelerators utilizes nonvolatile memory arrays to both store weights and perform $\textit{in situ}$ analog computation inside the array. While prior work has explored the design space of analog accelerators to optimize performance and energy efficiency, there is seldom a rigorous evaluation of the accuracy of these accelerators. This work shows how architectural design decisions, particularly in mapping neural network parameters to analog memory cells, influence inference accuracy. When evaluated using ResNet50 on ImageNet, the resilience of the system to analog non-idealities - cell programming errors, analog-to-digital converter resolution, and array parasitic resistances - all improve when analog quantities in the hardware are made proportional to the weights in the network. Moreover, contrary to the assumptions of prior work, nearly equivalent resilience to cell imprecision can be achieved by fully storing weights as analog quantities, rather than spreading weight bits across multiple devices, often referred to as bit slicing. By exploiting proportionality, analog system designers have the freedom to match the precision of the hardware to the needs of the algorithm, rather than attempting to guarantee the same level of precision in the intermediate results as an equivalent digital accelerator. This ultimately results in an analog accelerator that is more accurate, more robust to analog errors, and more energy-efficient.

Time Domain Analog Neuromorphic Engine Based on High-Density Non-Volatile Memory in Single-Poly CMOS

Increasing the energy efficiency of deep learning systems is critical for improving the cognitive capability of edge devices, often battery operated, as well as for data centers, constrained by the total power envelope. Specialized architectures accelerated by analog vector-matrix multipliers (VMMs) can reduce by orders of magnitude the energy per operation, since the reduced precision of analog computation does not undermine the classification accuracy of the neural network. We show an analog vector-matrix multiplier fabricated with industry-standard 0.18 μm CMOS process, exploiting a single-transistor non-volatile analog memory cell and dedicated technology circuit co-design. The design is focused on implementation in neural networks performing offline training. The VMM performs the analog multiplication of a vector of inputs, encoded in the duration of time pulses, times a matrix of weights, encoded in the programmable currents of the memory cells. A 1.72 μm2 memory cell is realized with a single transistor with floating gate, which can be operated as a two-terminal analog memristive device with more than 64 programmable current levels and high Ihigh/Ilow ratio (> 103), tuned by the charge injected in the floating gate. A small-area charge amplifier is used to convert the multiply and accumulate operation result into a voltage. System-level projections based on our measurements and simulations provide a throughput of 333.17 GOps/s and an energy efficiency of 122.3 TOps/J, higher than comparable-precision VMMs reported in the literature, and an equivalent area per cell down to 2.15 μm2, lower than any similar state-of-the-art solution. Of critical importance in view of translation to industry, our proposal uses in a new way an industry-standard low-cost single-poly CMOS process flow.

Operation of silicon microstrip detector with integrating readout for fast time-resolved experiments

New detector prototype is being developed for the “Plasma” scattering station of the VEPP-4M synchrotron radiation source at the Budker Institute of Nuclear Physics. The prototype is based on p-in-n silicon microstrip sensor with metal strips galvanicaly coupled to the p-implants. Each strip is connected to the input of low-noise integrator with 32 analogue memory cells. This approach allows to record time evolution of one-dimensional image of diffraction pattern with frame rate up to 10 MHz, spatial resolution of ∼130 μm (FWHM) and maximum photon flux of about 200 photons/channel.

Time-to-Voltage Converters Based on the Time-Sharing Principle

The authors offer a new approach to the creation of linear and nonlinear pulse width modulated (PWM) signal demodulators. The proposed approach is based on the time-sharing principle in feedback and feedforward circuits. The demodulators are characterized by ease of manufacturing due to the decreased need for analog element precision. The following circuits have been designed and presented: a PWM signal demodulator performing linear conversion of a PWM signal into voltage; calculating demodulators with the function of sum of products and simple fraction; and a demodulator with a fractional rational function. All these circuits are based on the principle of continuous signal averaging by the active Miller integrator with the storing of the intermediate result in an analog memory cell. The designed demodulators are investigated during modeling and full-scale experiments. The reviewed set of demodulators can be enlarged by adding similar circuits to the proposed structures with a larger number of inputs and new functional possibilities. The proposed solutions follow the modularity principle and can be used in fully integrated implementations.

Tightly Coupled Machine Learning Coprocessor Architecture With Analog In-Memory Computing for Instruction-Level Acceleration

Low-profile mobile computing platforms often need to execute a variety of machine learning algorithms with limited memory and processing power. To address this challenge, this work presents Coara, an instruction-level processor acceleration architecture, which efficiently integrates an approximate analog in-memory computing coprocessor for accelerating general machine learning applications by exploiting analog register file cache. The instruction-level acceleration offers true programmability beyond the degree of freedom provided by reconfigurable machine learning accelerators, and also allows the code generation stage of a compiler back-end to control the coprocessor execution and data flow, so that applications do not need high-level machine learning software frameworks with a large memory footprint. Conventional analog and mixed-signal accelerators suffer from the overhead of frequent data conversion between analog and digital signals. To solve this classical problem, Coara uses an analog register file cache, which interfaces the analog in-memory computing coprocessor with the digital register file of the processor core. As a result, more than 90% of data conversion overhead with ADC and DAC can be eliminated by temporarily storing the result of analog computation in a switched-capacitor analog memory cell until data dependency occurs. Cycle-accurate Verilog RTL model of the proposed architecture is evaluated with 45 nm CMOS technology parameters while executing machine learning benchmark computation codes that are generated by a customized cross-compiler without using machine learning software frameworks.

A Low-Power Analog Delay Line Using a Current-Splitting Method for 3-D Ultrasound Imaging Systems

We propose an analog delay line (ADL) that adopts a current-splitting method (CSM) to reduce power consumption. The proposed ADL employs a pipelined sample-and-hold architecture and includes a buffer in the analog memory cell to prevent a charge sharing problem. The CSM reduces power consumption without distorting the sampled data by dividing the current source of the buffer into a holding current source and a buffering current source, which are, respectively, located inside and outside of the analog memory cell. The simulated power consumption of the proposed ADL without and with the CSM is 1080 and $90~{\mu }\text{W}$ , respectively, indicating that the CSM reduces power consumption by 91.7%. The proposed ADL was fabricated using a 0.18- ${\mu }\text{m}$ CMOS process with a 1.8-V supply voltage and occupies an active area of $120 \times 140~{ \mu }\text{m}^{ 2}$ . The sampling capacitor in the analog memory cell was implemented with MOS capacitors instead of metal-insulator-metal capacitors, resulting in an area per unit delay of the proposed ADL of only $600~{ \mu }\text{m}^{ 2}$ , which is much smaller than that in prior works. The measurement results show that the delay of the proposed ADL is accurately controlled from 25 to 475 ns with a unit delay step of 25 ns at a sampling frequency of 40 MHz.

Development of a silicon microstrip detector with single photon sensitivity for fast dynamic diffraction experiments at a synchrotron radiation beam

Time-resolved experiments on the diffraction of synchrotron radiation (SR) from crystalline materials provide information on the evolution of a material structure after a heat, electron beam or plasma interaction with a sample under study. Changes in the material structure happen within a microsecond scale and a detector with corresponding parameters is needed. The SR channel 8 of the VEPP-4M storage ring provides radiation from the 7-pole wiggler that allows to reach several tens photons within one μs from a tungsten crystal for the most intensive diffraction peak. In order to perform experiments that allow to measure the evolution of tungsten crystalline structure under the impact of powerful laser beam, a new detector is developed, that can provide information about the distribution of a scattered SR flux in space and its evolution in time at a microsecond scale. The detector is based on the silicon p-in-n microstrip sensor with DC-coupled metal strips. The sensor contains 1024 30 mm long strips with a 50 μm pitch. 64 strips are bonded to the front-end electronics based on APC128 ASICs. The APC128 ASIC contains 128 channels that consist of a low noise integrator with 32 analogue memory cells each. The integrator equivalent noise charge is about 2000 electrons and thus the signal from individual photons with energy above 40 keV can be observed. The signal can be stored at the analogue memory with 10 MHz rate. The first measurements with the beam scattered from a tungsten crystal with energy near 60 keV demonstrated the capability of this prototype to observe the spatial distribution of the photon flux with the intensity from below one photon per channel up to 0∼10 photons per channel with a frame rate from 10 kHz up to 1 MHz.

The adaptive gain integrating pixel detector

The adaptive gain integrating pixel detector (AGIPD) is a development of a collaboration between Deustsches Elektronen-Synchrotron (DESY), the Paul-Scherrer-Institute (PSI), the University of Hamburg and the University of Bonn. The detector is designed to cope with the demanding challenges of the European XFEL. Therefore it comes along with an adaptive gain stage allowing a high dynamic range, spanning from single photon sensitivity to 104 × 12.4 keV photons and 352 analogue memory cells per pixel. The aim of this report is to briefly explain the concepts of the AGIPD electronics and mechanics and then present recent experiments demonstrating the functionality of its key features.

Upgrade of the Detector for Imaging of Explosions

Methods of dynamic imaging of explosions at a synchrotron radiation (SR) beam and small-angle X-ray scattering experiments with exploding samples are being developed in the Siberian Synchrotron Radiation Center (SSRC) at the Budker Institute of Nuclear Physics for more than fifteen years. The detector for imaging of explosions (DIMEX) was developed for these purposes and successfully operating at the beam line 0 at the VEPP-3 storage ring and at the beam line 8 at the VEPP-4M storage ring. The DIMEX is based on gas technology and allow to measure SR flux as a function of position and time with spatial resolution of ∼200 μm (FWHM), maximum frame rate of 2MHz and time resolution of ∼80ns. Maximum value of the SR flux that can be measured by the present detector corresponds to ∼5000 photons/(channel*bunch) (20 keV average energy, channel area 0.1x0.5 mm2, bunch revolution frequency 4MHz). Maximum number of frames that can be stored in the present detector is 32 and the number of channels with 0.1mm width is 512. In order to significantly improve the precision of data obtained by the DIMEX an upgrade of the detector has been started. The electronics of the gaseous version of the detector has been changed such that the new detector is able to operate with frame rate of 8MHz and store data in up to 100 frames. A new ASIC was developed for this purpose called DMXG64A that includes 64 channels with low noise integrator and 100 analogue memory cells in each channel. Input charge can be stored to and read out from analogue cells with maximum frequency 10MHz. This new version of the detector is called the DIMEX-G and is planned to be used at the VEPP-3 storage ring and for SAXS studies at the VEPP-4M storage ring. For imaging of explosions at the beam line 8 at the VEPP-4M storage ring, where SR flux is expected to be about 10-100 times higher than at the VEPP-3, a new detector based on Si micro-strip technology is being developed. Si micro-strip sensors with special design have been manufactured by Hamamatsu Photonics company. Each sensor contains 1024 30mm long strips with 50μm pitch. The sensor thickness is 320μm and it will be positioned at an angle of 1.7 degrees with respect to the SR beam plane in order to get effective Si thickness along the beam close to 10mm. The new detector called DIMEX-Si will have spatial resolution of 50μm (FWHM) and time resolution close to 10ns. The new ASIC is under development for this project that will allow to operate with the frame rate of 50MHz and record maximum charge that corresponds to the flux close to 106 photons/(chan*bunch), i.e. about 100 times higher than with present detector.

AGIPD, a high dynamic range fast detector for the European XFEL

AGIPD—(Adaptive Gain Integrating Pixel Detector) is a hybrid pixel X-ray detector developed by a collaboration between Deutsches Elektronen-Synchrotron (DESY), Paul-Scherrer-Institut (PSI), University of Hamburg and the University of Bonn. The detector is designed to comply with the requirements of the European XFEL. The radiation tolerant Application Specific Integrated Circuit (ASIC) is designed with the following highlights: high dynamic range, spanning from single photon sensitivity up to 104 12.5keV photons, achieved by the use of the dynamic gain switching technique using 3 possible gains of the charge sensitive preamplifier. In order to store the image data, the ASIC incorporates 352 analog memory cells per pixel, allowing also to store 3 voltage levels corresponding to the selected gain. It is operated in random-access mode at 4.5MHz frame rate. The data acquisition is done during the 99.4ms between the bunch trains. The AGIPD has a pixel area of 200× 200 μ m2 and a 500μ m thick silicon sensor is used. The architecture principles were proven in different experiments and the ASIC characterization was done with a series of development prototypes. The mechanical concept was developed in the close contact with the XFEL beamline scientists and is now being manufactured. A first single module system was successfully tested at APS.

A single-chip 32-channel analog beamformer with 4-ns delay resolution and 768-ns maximum delay range for ultrasound medical imaging with a linear array transducer.

A single-chip 32-channel analog beamformer is proposed. It achieves a delay resolution of 4 ns and a maximum delay range of 768 ns. It has a focal-point based architecture, which consists of 7 sub-analog beamformers (sub-ABF). Each sub-ABF performs a RX focusing operation for a single focal point. Seven sub-ABFs perform a time-interleaving operation to achieve the maximum delay range of 768 ns. Phase interpolators are used in sub-ABFs to generate sampling clocks with the delay resolution of 4 ns from a low frequency system clock of 5 MHz. Each sub-ABF samples 32 echo signals at different times into sampling capacitors, which work as analog memory cells. The sampled 32 echo signals of each sub-ABF are originated from one target focal point at one instance. They are summed at one instance in a sub-ABF to perform the RX focusing for the target focal point. The proposed ABF chip has been fabricated in a 0.13- μ m CMOS process with an active area of 16 mm (2). The total power consumption is 287 mW. In measurement, the digital echo signals from a commercial ultrasound medical imaging machine were applied to the fabricated chip through commercial DAC chips. Due to the speed limitation of the DAC chips, the delay resolution was relaxed to 10 ns for the real-time measurement. A linear array transducer with no steering operation is used in this work.

A Hybrid Verilog-A and Equation-defined Subcircuit Approach to MOS Switched Current Analog Cell Simulation

Conventional modeling and simulation of two-phase switched current MOS-integrated circuits is normally undertaken at semiconductor device level. This allows primary and secondary circuit effects to be studied and characterized. However, with the growing complexity of these circuits, transient domain simulation times can become prohibitively long, restricting the size of circuit that can be easily investigated. Measurable reductions in transient simulation run times can be achieved by modeling part, or all, of a switched current design as a macromodel. This paper introduces a hybrid approach to MOS switched current circuit modeling that combines the primary features of compact device modeling with functional circuit macromodeling. To illustrate the proposed hybrid modeling procedure the properties, and simulation model, of a MOS switched current analog memory cell are described. The material presented also demonstrates how recent trends in “Quite universal circuit simulator” (QUCS) technology promote embedded Verilog-A models and equation-defined subcircuits as integral elements in mixed-mode circuit and system design.

Design of Analog Pixel Memory for Low Power Application in TFT-LCDs

Two types of analog memory cells realized in a 3-μm low temperature polycrystalline silicon (LTPS) technology are proposed to achieve low power application for thin film transistor liquid crystal displays (TFT-LCDs). By employing the inversion signal in the storage capacitor with complementary source follower, the frame rate to refresh the static image can be reduced from 60 to 3.16 Hz with the output decay less than 0.1 V under the input data from 1 to 4 V. To further diminish threshold voltage drop from source follower structure, a compensation technique is implemented to the proposed analog memory cells. In addition, asymmetric output voltage can be also minimized by adding a reference voltage to achieve symmetric output waveform.

Experimental characterization of the 192 channel Clear-PEM frontend ASIC coupled to a multi-pixel APD readout of LYSO:Ce crystals

In the framework of the Clear-PEM project for the construction of a high-resolution scanner for breast cancer imaging, a very compact and dense frontend electronics system has been developed for readout of multi-pixel S8550 Hamamatsu APDs. The frontend electronics are instrumented with a mixed-signal Application-Specific Integrated Circuit (ASIC), which incorporates 192 low-noise charge pre-amplifiers, shapers, analog memory cells and digital control blocks. Pulses are continuously stored in memory cells at clock frequency. Channels above a common threshold voltage are readout for digitization by off-chip free-sampling ADCs. The ASIC has a size of 7.3 × 9.8 mm 2 and was implemented in a AMS 0.35 μ m CMOS technology. In this paper the experimental characterization of the Clear-PEM frontend ASIC, reading out multi-pixel APDs coupled to LYSO:Ce crystal matrices, is presented. The chips were mounted on a custom test board connected to six APD arrays and to the data acquisition system. Six 32-pixel LYSO:Ce crystal matrices coupled on both sides to APD arrays were readout by two test boards. All 384 channels were operational. The chip power consumption is 660 mW (3.4 mW per channel). A very stable behavior of the chip was observed, with an estimated ENC of 1200 – 1300 e - at APD gain 100. The inter-channel noise dispersion and mean baseline variation is less than 8% and 0.5%, respectively. The spread in the gain between different channels is found to be 1.5%. Energy resolution of 16.5% at 511 keV and 12.8% at 662 keV has been measured. Timing measurements between the two APDs that readout the same crystal is extracted and compared with detailed Monte Carlo simulations. At 511 keV the measured single photon time RMS resolution is 1.30 ns, in very good agreement with the expected value of 1.34 ns.

Optimization of Tracking Performance of CMOS Monolithic Active Pixel Sensors

CMOS Monolithic Active Pixel Sensors (MAPS) provide an attractive solution for high precision tracking of minimum ionizing particles. In these devices, a thin, moderately doped, undepleted silicon layer is used as the active detector volume with the readout electronics implemented on top of it. Recently, a new MAPS prototype was fabricated using the AMS 0.35 mum OPTO process, featuring a thick epitaxial layer. A systematic study of tracking performance of that prototype using high-energy particle beam is presented in this work. Noise performance, signal amplitude from minimum ionizing particles, detection efficiency, spurious hit suppression and spatial resolution are shown as a function of the readout pitch and the charge collecting diode size. A test array with a novel readout circuitry was also fabricated and tested. Each pixel circuit consists of a front-end voltage amplifier, capacitively coupled to the charge collecting diode, followed by two analog memory cells. This architecture implements an on-pixel correlated double sampling method, allowing for optimization of integration independently of full frame readout time and strongly reduces the pixel-to-pixel output signal dispersion. First measurements using this structure are also presented

Application-specific architectures of CMOS monolithic active pixel sensors

Several development directions intended to adapt and optimize monolithic active pixel sensors for specific applications are presented in this work. The first example, compatible with the STAR microvertex upgrade, is based on a simple two-transistor pixel circuitry. It is suited for a long integration time, room-temperature operation and minimum power dissipation. In another approach for this application, a specific readout method is proposed, allowing optimization of the integration time independently of the full frame-readout time. The circuit consists of an in-pixel front-end voltage amplifier, with a gain on the order of five, followed by two analog memory cells. The extended version of this scheme, based on the implementation of more memory cells per pixel, is the solution considered for the outer layers of a microvertex detector at the international linear collider. For the two innermost layers, a circuit allowing fast frame scans together with on-line, on-chip data sparsification is proposed. The first results of this prototype demonstrate that the fixed pattern dispersion is reduced below a noise level of 15 e −, allowing the use of a single comparator or a low-resolution ADC per pixel column. A common element for most of the mentioned readout schemes is a low-noise, low power consumption, layout efficient in-pixel amplifier. A review of possible solutions for this element together with some experimental results is presented.

SAM: A new GHz sampling ASIC for the H.E.S.S.-II front-end electronics

The H.E.S.S.-II front-end electronics, with its 20 GeV energy threshold, will require a much higher acquisition rate capability and a larger dynamic range than was relevant for H.E.S.S.-I. These constraints led to the development of a new ASIC, called SAM for Swift Analogue Memory, to replace the ARS used for H.E.S.S.-I. The SAM chip features 2 channels for the low and high gain outputs of a PMT, each channel having a depth of 256 analogue memory cells. The sampling frequency is adjustable from 0.7 up to 2 GS/s and the read-out time for one event is decreased from 275 down to 2.3 μs. The SAM input bandwidth and dynamic range are increased up to 300 MHz and more than 11 bits, respectively.

Fault Detection in Switched Current Circuits Using Built-in Transient Current Sensors

Switched current (SI) circuits use analogue memory cells as building blocks. In these cells, like in most analogue circuits, there are hard-to-detect faults with conventional test methods. A test approach based on a built-in dynamic current sensor (BIDCS), whose detection method weights the highest frequency components of the dynamic supply current of the circuit under test, makes possible the detection of these faults, taking into account the changes in the slope of the dynamic supply current induced by the fault. A study of the influence of these faults in neighbouring cells helps to minimize the number of BICS needed in SI circuits as is shown in two algorithmic analogue-to-digital converters.