Analog Integrator Research Articles

High Accuracy On-Line Calibration System for Current Transformers Based on Clamp-Shape Rogowski Coil and Improved Digital Integrator

To solve the problems of the existing on-site calibration methods, for instance, the methods need power off, and the standard transformers have large volume, heavy weight and small dynamic range, this paper proposes a high accuracy on-line calibration method for current transformers. By using a clamp-shape Rogowski coil as the standard current transformer, instead of traditional electromagnetic transformer, the volume and weight are reduced greatly, and the power of the line needn’t to be interrupted. The output signal of the clamp-shape Rogowski coil needs to be integrated, and to overcome the problems of analog integrator, which have temperature and zero drift, a high accuracy digital integrator is proposed in the paper to improve the accuracy and stability of the signal processing circuit. Test results indicate that the accuracy of the whole calibration system can reach up to 0.05 accuracy class. The on-line calibration system can calibrate the traditional and electronic current transformers when the line is energized.

A precision analogue integrator system for heavy current measurement in MFDC resistance spot welding

In order to control and monitor the quality of middle frequency direct current (MFDC) resistance spot welding (RSW), precision measurement of the welding current up to 100 kA is required, for which Rogowski coils are the only viable current transducers at present. Thus, a highly accurate analogue integrator is the key to restoring the converted signals collected from the Rogowski coils. Previous studies emphasised that the integration drift is a major factor that influences the performance of analogue integrators, but capacitive leakage error also has a significant impact on the result, especially in long-time pulse integration. In this article, new methods of measuring and compensating capacitive leakage error are proposed to fabricate a precision analogue integrator system for MFDC RSW. A voltage holding test is carried out to measure the integration error caused by capacitive leakage, and an original integrator with a feedback adder is designed to compensate capacitive leakage error in real time. The experimental results and statistical analysis show that the new analogue integrator system could constrain both drift and capacitive leakage error, of which the effect is robust to different voltage levels of output signals. The total integration error is limited within ±0.09 mV s−1 0.005% s−1 or full scale at a 95% confidence level, which makes it possible to achieve the precision measurement of the welding current of MFDC RSW with Rogowski coils of 0.1% accuracy class.

A 0.022 mm<formula formulatype="inline"><tex Notation="TeX">$^{{2}}$</tex></formula> 98.5 dB SNDR Hybrid Audio <formula formulatype="inline"><tex Notation="TeX">$\Delta \Sigma$</tex></formula> Modulator With Digital ELD Compensation in 28 nm CMOS

This work presents a compact-area hybrid continuous-time delta-sigma modulator (CTDSM) with a shared 6 bit asynchronous successive approximation register (ASAR) quantizer for audio application. It is implemented in a 28 nm CMOS process. The modulator incorporates an analog integrator and a digital filter. Signal is digitized after the analog first stage and processed digitally thereafter. Only the first stage is left in the analog domain. Because of high integration of digital circuitry, it could benefit from process advancement such as low power consumption and small area. Moreover, the excess loop delay (ELD) is compensated in the digital domain, and the conventional analog local feedback DAC for ELD compensation is no longer needed. In addition, resistive DAC (R-DAC) is adopted for low flicker noise. The measured DR and SNDR in 24 kHz BW are 100.6 dB and 98.5 dB, respectively, while occupying 0.022 mm 2 and achieving FOMs (SNDR + 10 $*$ log(BW/Power)) of 171.8 dB.

Introduction to the special issue on “High performance analog circuits and design methodologies”

This special issue of the SPRINGER Journal of Analog Integrated Circuits and Signal Processing includes a special section composed of four papers related to ‘‘High performance analog circuits and design methodologies’’. They are selected among those presented at the Joint Conference of 4S-2014/2014 International Conference on Analog VLSI Circuits (AVIC 2014). This conference was jointly organized by Vietnam National University HCMC (VNU-HCM) Integrated Circuit Design Research and Education Center (ICDREC) and Institute of Electrical Engineers of Japan (IEEJ) as an event for commemorating the 20 anniversary of VNU-HCM and 10th anniversary of ICDREC. The conference is the successor of the former International Analog VLSI Workshop. Its purpose is to exchange information, ideas and recent research results on analog VLSI circuits and their applications. The first paper, ‘‘An Improvement of the Current– Voltage Conversion Technique in Over-Current Sensing Circuit for Low-Power Low Dropout Linear Voltage Regulators’’, by Ho Quang Tay, proposes a resistance-less over-current sensing circuit using current–voltage conversion technique for CMOS low dropout linear voltage (LDO) regulators with PMOS as pass device. The second paper, ‘‘Delta-Sigma DAC with Jitter-Shaper-Reducing Jitter Noise’’, by Yuki Watanabe et al., describes a novel delta-sigma digital-to-analog converter (DSDAC) using a jitter shaper to augment the noise caused by clock jitter. The third paper, ‘‘Design of a Symmetry-type Floating Impedance Scaling Circuits for a Fully Differential Filter’’, by Fujihiko Matsumoto et al., proposes the impedance scaling techniques in order to realize a small-size low frequency active filter. The final paper, ‘‘A Low-Power and Low-Gm Linear Transconductor Utilizing Control of a Threshold Voltage’’, by Takeshi Ohbuchi et al., proposes a linear transconductor that is realized by the scheme that the threshold voltages of the transistors are changed by the attenuated input voltage using body effect and reverse short-channel effect. On behalf of the editorial committee of this special section, we would like to express our great thanks to all the authors of the submitted manuscripts and all the reviewers for their great contribution and helpful effort. We also would like to thank all of the committee members for their valuable effort expended in this editorial work. Finally, we would like to express our special thanks to the Guest Editorial Secretary, Professor Cosy Muto, Nagasaki University and Professor Hiroo Sekiya, Chiba University, and the Advisor, Professor Takeshi Shima, Kanagawa University, for all their contributions and efforts.

Pulsed-field magnetometry for rock magnetism

An improved method is proposed for measuring dynamic magnetizations of bulk volcanic rock samples induced by a pulsed-field of 0.7 T and a duration of 10 ms. The transient magnetization is measured by a sensing system that consists of a pair of inductive differential coils, an analog preamplifier and integrator, and a high-speed digital storage scope. The system was calibrated using a paramagnetic salt (Gd2O3) and was tested to different kinds of volcanic rocks with their magnetic properties well-documented previously. The results were comparable with those measured by a quasi-static method using a vibrating sample magnetometer, although there were small discrepancies in hysteresis parameters suggesting the time-dependence of the magnetic properties. The proposed system provides not only the magnetization over the short interval of a pulse but also the rapid (~3 ms) exponential decay after a pulse. The decay time constant was different among the samples under study, indicating the variations of their magnetic relaxation time. Although the present system is not sensitive enough to characterize varieties of natural samples including sediments, it has the potential as a versatile and convenient tool for rock magnetism.

Enhanced integrators for WEST magnetic diagnostics

The WEST project consists of implementing a divertor configuration in the Tore Supra Tokamak. This modification requires to renew the magnetic diagnostics and especially adding new magnetic sensors in the divertor region. This has provided an opportunity to consider some enhancements to the existing integrator modules of the magnetic diagnostics. Two prototypes have been produced using different combinations of technical solutions, aiming to achieve lower drift and higher common mode rejection ratio (CMRR). This paper presents the explored and tested ways we followed in order to create enhanced analogue integrators for long pulses. The results of extensive and comprehensive tests are summarized. The achieved performances are analyzed regarding the WEST project specifications and furthermore, the latest ITER requirements for magnetic diagnostics integrators are also considered.

FBCT fast intensity measurement using TRIC cards

At the CERN PS complex, precise fast intensity measurements are very important in order to optimize the transfer efficiencies between the different accelerators. Over the last two years a complete renovation has been ongoing, where the old electronics, based on analogue integrators, have been replaced by a fully digital system enclosed in a single VME based card. This new system called TRIC (Transformer Integration Card) is based on a 12 bit, 212 MS/s ADC and an FPGA for the signal processing. Also located on the same board one finds a 250 V/1.5 W DCDC converter used to generate precise calibration pulses.

Spatial mode control of surface plasmon polariton excitation with gain medium: from spatial differentiator to integrator.

In optical analogue computation, optical differentiator and integrator are the key element devices for ultrafast parallel data processing. Here we demonstrate that a Kretschmann configuration prism can directly perform spatial differentiation for the incident beam profile. Additionally, we realize all-optical reconfiguration from differentiator to integrator by modulating the propagation loss of surface plasmon polariton with optical pump. The feature of reconfiguration opens directions to ultrafast beam transformation, reconfigurable imaging processing, and all-optical analogue computing.

Guest Editors' Introduction: Speeding Up Analog Integration and Test for Mixed-Signal SoCs

The seven articles in this special section initiatives to standardize methods, measurements, and tools that support mixed-signal design. The papers are organized along the lines of the overall design-to-test flow, covering verification, selection of test content, defect level estimation, silicon validation, and data-driven test optimization and yield recovery. Presents examples on how to perform comprehensive verification, how to measure and ensure adequate analog test coverage, and how to create and track a specification compliance matrix across the entire design-to-manufacturing flow.

Speeding Up Analog Integration and Test for Mixed-Signal SoCs [From the EIC

Presents an editorial that addresses the main topics discussed in this issue focusing on the complex challenges of design, verification, and test of analog and mixed-signal circuits and SoCs.

Special issue: Highlights from the flagship Latin American Symposium on Circuits and Systems: selected papers from LASCAS 2013

It is a pleasure and a privilege to present to the readers of the Springer Journal on Analog Integrated Circuits and Signal Processing (ALOG) a selection of the papers from the 4th edition of the Latin America Symposium on Circuits and Systems—LASCAS 2013, held in February 2013 in the historical Peruvian city of Cuzco. The LASCAS Symposium is the premier event in circuits and systems in that region of the Americas. The papers selected by the Guest Editors fall in the focus of this Journal, and are among the 10 % top quality of the 155 papers submitted to LASCAS 2013, and were selected by rigorous reviewing. While LASCAS contemplates applications and digital systems, most of the papers in this Special Issue address analog circuits and systems, the themes of interest to ALOG Journal readers. From the 119 papers which were accepted and published in the IEEE LASCAS Proceedings, a total of 27 works were nominated and invited to submit a substantially improved manuscript on the same subject to this Special Issue of LASCAS 2013. The quality screening took advantage of the reviews and paper ratings for each of those 119 papers, which were narrowed down to 23 extended manuscripts. These went through a second-round of peer-review process and 14 papers, substantially extended versions from the LASCAS Symposium, were finally selected for this Special Issue, as the highlights from the flagship Latin American Symposium on Circuits and Systems. The papers in this Special Issue come from the Americas (North and South) and Europe. The 14 selected papers cover a wide range of topics, from analog circuits design at ultra-low voltages, to amplifiers design, integrated circuits, wireless, and digital systems design, and up to topics at the application of communications and arithmetic circuits. The first 3 papers in the Special Issue deal with low voltage analog CMOS design. The paper ‘‘Fully Integrated Inductive Ring Oscillators Operating at VDD below 2kT/ q’’ by M. Machado et alli presents oscillators with two inductive loading schemes to work under extremely low DC supplies. H. Hernandez et alli propose and show in their paper a silicon implementation of ‘‘A fully Integrated Boost Converter For Thermoelectric Energy Harvesting’’ which upconverts from very low voltage supplies. The paper ‘‘Sub-1 V Band-Gap Based and MOS ThresholdVoltage Based Voltage References in 0.13 lm CMOS’’ by D.M. Colombo et alli explores and compares low-voltage DC reference circuits with different circuit approaches possible in standard CMOS, compared to diode-based BGRs. Two papers on DC and instrumentation amplifiers designs target improvements on either DC gain or CMRR. H. Gomez-Ortiz introduces a ‘‘Robust to PVT Enhanced DC Gain Amplifier Using No Miller Capacitor Feedforward Compensation’’ in his paper, where a feedforward scheme improves DC gain and common mode range. C. Silva-Cardenas Maestria de Ingenieria de las Telecomunicaciones, Pontificia Universidad Catolica del Peru, Ave. Universitaria 1801, Lima 32, Peru e-mail: csilva@pucp.edu

Introduction to the special issue on “High performance analog circuits and design methodologies”

This special issue in the SPRINGER Journal of Analog Integrated Circuits and Signal Processing is published with four papers. We called for papers related to ‘‘High performance analog circuits and design methodologies’’ mainly from those presented at the 2013 International Conference on Analog VLSI Circuits (AVIC 2013). Two papers are selected from this conference. The Research Committee on Electronic Circuits of the Institute of Electrical Engineers of Japan (IEEJ) organized AVIC 2013 in Montreal, Canada on October 16–18, 2013, in cooperation with the IEEE Montreal Section. This conference is the successor of the former International Analog VLSI Workshop. Its purpose is to exchange information, ideas and recent research results on analog VLSI circuits and their applications. The first paper, ‘‘IC Implementation of an Interstitial Cell-based CPG Model,’’ by Saeki et al. suggests a central pattern generator (CPG) model in which swing and stance patterns produced by interstitial cells generate low-frequency patterns through a low-capacitance 0.18 lm CMOS process. It is demonstrated that this model method can generate five basic quadruped locomotion patterns (walk, pace, trot, bound, and gallop) at a frequency suitable for controlling a quadruped locomotion robot. The second paper, ‘‘A Digitally Calibrated Dynamic Comparator Using Time-Domain Offset Detection,’’ by Okazawa et al. presents a self-calibrating dynamic latched comparator that does not require additional static current or load capacitors to reduce its offset voltage. The proposed comparator uses a reconfigurable differential pair at the input stage; the configuration is determined by a digital calibration scheme that automatically matches the differential pair, resulting in a low offset voltage. The third paper ‘‘A Chopper-Stabilized Instrumentation Amplifier Using Area-Efficient Self-Trimming Technique,’’ by Akita and Ishida presents an area-efficient self-trimming technique for precision chopper-stabilized instrumentation amplifier. The amplifier uses a reconfigurable differential pair for the input stage and it is automatically configured to reduce the mismatch of the differential pair, suppressing the chopper ripple. The last paper ‘‘A 0.3-V Power Supply 2.4-GHz-Band Class-C VCO IC with Amplitude Feedback Loop in 65-nm CMOS,’’ by Yang et al. proposes a Class-C VCO IC with an amplitude feed-back loop for ultra-low-voltage application. The Class-C VCO consists of an LC-VCO circuit and an amplitude feedback loop to shift LC-VCO bias condition from initial Class-AB start-up to steady Class-C low current oscillation.

A new swarm-SVM-based fault diagnosis approach for switched current circuit by using kurtosis and entropy as a preprocessor

This paper presents a new fault diagnosis method for switched current (SI) circuits. The kurtoses and entropies of the signals are calculated by extracting the original signals from the output terminals of the circuit. Support vector machine (SVM) is introduced for fault diagnosis using the entropies and kurtoses as inputs. In this technique, a particle swarm optimization is proposed to optimize the SVM to diagnose switched current circuits. The proposed method can identify faulty components in switched current circuit. A low-pass SI filter circuit has been used as test beached to verify the effectiveness of the proposed method. The accuracy of fault recognition achieved is about 97 % although there are some overlapping data when tolerance is considered. A comparison of our work with Long et al. (Analog Integr Circuit Signal Process 66:93---102, 2011), which only used entropy as a preprocessor, reveals that our method performs well in the part of fault diagnostic accuracy.

Research on High Bandwidth Rogowski Coil for Measuring Lightning Traveling Wave Current on Double Circuit Transmission Line

Double circuit transmission line is an important part of the power grid, which is vulnerable to lightning and may endanger the security and stability of the power grid. In order to design a sensor which can monitor the lightning traveling wave current on double circuit transmission line, simulations of lightning on the double circuit transmission line were conducted. The simulation result shows that besides high frequency components, the traveling wave contains a lot of low frequency components. Based on the equivalent model and the frequency response of the self-integrated Rogowski coil, it turns out that the widely used self-integrated Rogowski coil is not suitable for this application as the problem of low frequency distortion. In this paper, through theoretical analysis and simulations in Matlab, an improved Rogowski coil with analog integrator is proposed which can correct the low frequency distortion of the self-integrated Rogowski coil. All the simulations, experiments and operating data installed to a double circuit transmission line in China verify the validity of the high bandwidth Rogowski coil.

Synthesis of poly(ester-carbonate) with a pendant acetylcholine analog for promoting neurite growth

The modification of biodegradable polyesters with bioactive molecules has become an important strategy for controlling neuron adhesion and neurite outgrowth in nerve regeneration. In this study we report a biodegradable poly(ester-carbonate) with a pendant acetylcholine analog, which a neurotransmitter for the enhancement of neuron adhesion and outgrowth. The acetylcholine-functionalized poly(ester-carbonate) (Ach-P(LA-ClTMC)) was prepared by copolymerizing l-lactide (LA) and 5-methyl-5-chloroethoxycarbonyl trimethylene carbonate (ClTMC), followed by quaternization with trimethylamine. The acetylcholine analog content could be modulated by changing the molar feeding fraction of ClTMC. The incorporation of the acetylcholine analog improved the hydrophilicity of the films, but the acetylcholine analog content did not significantly influence the surface morphology of the acetylcholine-functionalized films. The results of PC12 cell culture showed that the acetylcholine analog promoted cell viability and neurite outgrowth in a concentration-dependent manner. The longest length of neurite and the percentage of cells bearing neurites were obtained on the Ach-P(LA-ClTMC)-10 film. All the results indicate that the integration of the acetylcholine analog at an appropriate fraction could be an effective strategy for optimizing the existing biodegradable polyesters for nerve regeneration applications.

High-accuracy and low signal distortion on-chip auto-calibrating architecture for continuous-time filters

A high-accuracy on-chip auto-calibrating architecture is presented to compensate the process and temperature parameter variations in high-linearity continuous-time filter. The on-chip auto-calibrating architecture consists of a clock generating circuit, a voltage comparator, a digital tuning engine, and an analog integrator with similar time-constants as the tuned filter. Discrete capacitor arrays are utilized to tune filter automatically for preserving a high linearity. A fourth-order RC filter for GNSS receivers is fabricated in 0.18 µm CMOS process to verify the performance of proposed tuning architecture. With adjustment, this filter achieves less than 5 % frequency uncertainty. The whole circuit consumes 5.2 mA under a 1.8 V supply and occupies a die area of 0.55 mm2. Both the post-layout simulation and measured results indicate that the auto-calibrating architecture is a useful and adequate solution to compensate the errors caused by factors such as fabrication tolerances, changes in operating conditions, parasitic effects and aging.

Two high accuracy digital integrators for Rogowski current transducers

The Rogowski current transducers have been widely used in AC current measurement, but their accuracy is mainly subject to the analog integrators, which have typical problems such as poor long-term stability and being susceptible to environmental conditions. The digital integrators can be another choice, but they cannot obtain a stable and accurate output for the reason that the DC component in original signal can be accumulated, which will lead to output DC drift. Unknown initial conditions can also result in integral output DC offset. This paper proposes two improved digital integrators used in Rogowski current transducers instead of traditional analog integrators for high measuring accuracy. A proportional-integral-derivative (PID) feedback controller and an attenuation coefficient have been applied in improving the Al-Alaoui integrator to change its DC response and get an ideal frequency response. For the special design in the field of digital signal processing, the improved digital integrators have better performance than analog integrators. Simulation models are built for the purpose of verification and comparison. The experiments prove that the designed integrators can achieve higher accuracy than analog integrators in steady-state response, transient-state response, and temperature changing condition.

A time-domain noise-coupling technique for continuous-time sigma-delta modulators

In this paper, a time-domain noise-coupling technique based on the pulse width modulation is proposed. The time-domain quantization error is digitally extracted and shaped by an asynchronous digital filter. This digitally filtered quantization error is applied to the quantizer input to increase the modulator's noise-shaping order. By using this technique in continuous-time sigma-delta modulators, the modulator's shaping property is significantly enhanced. Comparative analytical calculations and simulation results are presented to estimate the performance of modulators employing the proposed quantizer. System-level simulation results reveal a (L + 2)th order noise-shaping capability of the proposed modulator while it employs only L analog integrators. The effects of main circuit non-idealities in the modulator's performance are analytically investigated and confirmed by the simulation results.

Introduction to the special issue on Low-power circuit techniques

This special issue of ‘‘Low-power circuit techniques’’ in the Springer Journal of Analog Integrated Circuits and Signal Processing is published with six papers, which are selected from presented papers at the 2012 International Conference on Analog VLSI Circuits (AVIC 2012). This conference is believed to be the only conference that bares the key word ‘‘Analog VLSI’’, and have accepted very wide range of papers concerning analog circuits. Among them, we called for papers related to low-power circuit techniques for this special issue. The Research Committee on Electronic Circuits of the Institute of Electrical Engineers of Japan (IEEJ) was sponsoring and cooperating with Analog Devices Inc., the University of Valencia and the Polytechnic University of Valencia to hold the 2012 International Conference on Analog VLSI Circuits in Valencia, Spain, on October 24–26, 2012. This conference is the successor of former International Analog VLSI Workshop, which had been successfully held for 14 years. The purpose of the conference is to exchange information, ideas and recent research results on analog VLSI circuits and their applications. This workshop has formed a long-standing community for various analog VLSI circuit specialists from both industry and academia worldwide, and promoted active brainstorming among them at the site. The first two papers are related to power supply circuits and DC–DC converter circuits. The first paper by Nomura et al. presents photovoltaic cell design, oscillator, and bootstrap charge pump circuit integrated on an 0.18 lm CMOS chip, to provide power generation and voltage boost functions on stand-alone microsystems. Sato et al. present a theoretical analysis of efficiency in charge pumps for LED drivers and describe a novel procedure to minimize power loss by applying adiabatic process to charge pump circuits. The third paper by Tanimoto et al. presents a fullydifferential OTA operating from 1-V power supply. The OTA consists from CMOS cascode inverters to obtain a high voltage gain while maintaining rail-to-rail input common-mode range at 1-V power supply. They also fabricated a test chip by using 0.15 lm CMOS technology and confirmed the design techniques to be useful. The fourth and the fifth papers are concerning to high speed communication signal processing. Nakagawa et al. present a passive complex filter design approach, which is relevant to low power analog signal processing at very high frequency. The concept is exemplified with two complex filters operating at 100 kHz and 10 MHz but maybe extended beyond tens of GHz. The fifth paper by Yazaki et al. presents a design of a 20-Gbps CMOS optical receiver, which does not require inductor to suppress power supply noise by a unique design of power supply noise canceling circuit. The designed chip was fabricated in 90 nm CMOS technology and demonstrated effectiveness of the design. The last paper by Carbajo et al. presents a new version of the well known Goertzel algorithm for discrete Fourier J. Calpe-Maravilla Analog Devices S.L., Edificio 8F, Planta 3, Campus UPV, 46022 Valencia, Spain e-mail: javier.calpe@analog.com

Introduction to the Special issue on IEEE-Latin American Symposium on Circuits and Systems

This special issue of the Springer Analog Integrated Circuits and Signal Processing (ALOG) presents the selection of best papers from the Third IEEE Latin American Symposium on Circuits and Systems (LASCAS 2012). The symposium, a forum for discussion of the latest technical novelties on circuits and systems topics, was held in Playa del Carmen, Mexico, from February 29 to March 2, 2012. 112 papers from 20 countries and 3 continents were submitted to the conference. 69 papers were accepted based on the reviews from international experts. These contributions made up a high-quality technical program covering a wide variety of subjects in the areas of analog and digital circuits and systems, computer aided design, modeling and simulation, signal processing, sensor systems, high-frequency systems, voltage references, processor architectures and control theory. From the papers presented at the conference, 12 papers were pre-selected for journal publication based on the evaluations of the Program Committee members and the corresponding session chairs. After a thorough revision of the extended papers, 7 papers were finally accepted for publication in this special issue. These contributions are: (1) an ultra low power consumption millimeter-wave voltage controlled oscillator in a 65 nm CMOS-SOI technology; (2) a rail-to-rail differential quasi-digital converter for low-power applications; (3) analog sigma-delta modulation with op-amp gain compensation for nanometer technologies; (4) design of an integrated single-input dualoutput 3-switch buck converter based on sliding mode control; (5) offset and gain calibration circuit for MIMISFET devices; (6) parallel algorithm for evolvable-based boolean synthesis on GPUs; (7) neural inverse optimal control applied to type 1 diabetes mellitus patients. We thank the researchers from around the world who have chosen LASCAS 2012 for presenting their recent developments. We are deeply thankful to the reviewers for their contribution to the creation of the LASCAS 2012 technical program and for their involvement in the revision of the selected papers for this special issue. Finally, we thank the session chairs who not only contributed to the successful development of the symposium, but also helped in the selection of the best papers for journal publication.